Digital Communication (EC 691) Lab Manual Protected PDF

DIGITAL COMMUNICATION LAB (CODE:EC691)
LABORATORY MANUAL
Course Objectives:
1. To understand and analyze the signal flow in a digital communication system.
2. To perform the time and frequency domain analysis of the signals in a digital
communication system.
3. To analyze the performance of a baseband and pass band digital communication
system in terms of error rate and spectral efficiency.
4. To understand the building blocks of digital communication system.
5. To analyze error performance of a digital communication system in presence of noise
and other interferences.
Narula Institute of Technology Department of ECE

LABORATORY MANUAL
SYLLABUS
Digital Communication Lab (EC 691)
Contact: 3P
Credit: 2
(Students are required to perform at least ten experiments taking 3 from Group A, 3 from Group B, 3
from Group C and 1 from Group D)
GROUP - A (At least three experiments)
1. Design, implementation and studies of the properties of 15 bit P.N. Sequence using shift register
2. Studies of the properties of A/D and D/A converter (AD7820/ADC0820 and ICL 8018A/8019A/8020A).
(Properties like transfer characteristics, code central line method of nonlinearity study, differential
nonlinearity, integral nonlinearity, resolution etc).
3. Study of pulse amplitude modulation and demodulation.
(Studies of distortion factor of the constructed signal as a function of signal frequency & amplitude. Further
study of distortion factor of filtered reconstructed signal as a function of sampling frequency and thus verify
the sampling theorem).
4. Studies of PCM transmitter and receiver.
(To measure the bit rate, bandwidth requirement and distortion factor of the reconstructed signal in presence
of channel noise).
5. Study of line coders: UPNRZ, PRZ, BPRZ, PNRZ
(To study the nature of waveform in CRO and its spectrum by spectrum analyzer. At least any one of the
line coders has to design, fabricated and tested).
6. Studies of Manchester coding and decoding technique.
(Studies of the nature of waveform, spectrum and self-synchronizing characteristic).
GROUP - B (At least three experiments)
7. Studies of PSK modulator and demodulator, connected by physical channel.
8. Studies on FSK modulator and demodulator, connected by simulated channel
9. Studies on ASK modulator and demodulator, connected by physical channel
10. Studies on QPSK modulator and demodulator, connected by either physical or simulated channel (In all
above experiments, nature of the modulated waveform is to be studied by a CRO. The spectrum is to be
studied with a spectrum analyzer and the essential bandwidth is to be determined; finally the reception
quality is to be analyzed by cross co-relation characteristics and measurement of bit error rate in presence of
channel noise).
GROUP - C (At least three experiments)

11. Studies on Delta modulator & Demodulator using trainer kits
12. Studies on Adaptive delta modulation using trainer kits
13. Studies on delta signal modulation using trainer kits
14. Studies on PCM/TDM system (Multiplexing/Demultiplexing)
(Object is to measure distortion factor of the demodulated signal with variable signal amplitude and
frequency, measure the essential B.W. of the modulated signal
15. Studies of PCM/TDM system (Multiplexer & Demultiplexer)
(To study the interchannel interference and synchronization problem in multiplexer and demultiplexer
system
GROUP - D (At least one experiment)
16. Studies of direct sequence spread spectrum modulation and demodulation
17. Studies of frequency hopped spread spectrum modulation and demodulation
(To study spreading and dispersing, effect of channel noise, single tone interference etc.
18. Study of features of ISDN network.
19. Study of ISDN Emulator and its programming, using appropriate communication software (like protocol
analyzer software).
Total 30 hours minimum (10 experiments each of 3 periods)

LABORATORY MANUAL
EXPERIMENT NO. – 1
EXPERIMENT TITLE: DESIGN, IMPLEMENTATION AND STUDIES OF THE

PROPERTIES OF 15 BIT P.N. SEQUENCE USING SHIFT REGISTER
OBJECTIVE: This experiment will enable one to understand the pseudo noise(pn) sequence
with certain autocorrelation properties.
THEORY : In spread spectrum system, the signal spreading code is the so called the pseudo
noise(pn) sequence which is generally periodic and consists of a periodic coded sequence of
1’s and 0’s with certain autocorrelation properties. These signals are pseudo random is as
much as they appear to be unpredictable to be an outsider, though they appear or can be
generated by deterministic means by the person for whom they are intended. When a shift
resister has a non-zero initial state and the output is fed back to the input , the unit acts as
periodic sequence generation. In general the longest possible sequence from a resister n
stages is N= (2n – 1).The corresponding output is called a maximum length sequence or PN
sequence.
The names pseudo noise comes from the correlation properties of sequence of N, is very
large and Tb is very small, then the pn signal acts essentially like white noise with a small DC
component and hence is called Pseudo Noise Sequence.

LABORATORY MANUAL
SL. SHIFT RESISTER FEED BACK SHIFT STATE SHIFT O/P

NO. STATE I/P XOR
M1 M2 M3 M4 GATE O/P M1 M2 M3 M4
01 1 1 1 1 0 0 1 1 1 1
02 0 1 1 1 0 0 0 1 1 1
03 0 0 1 1 0 0 0 0 1 1
04 0 0 0 1 1 1 0 0 0 1
05 1 0 0 0 0 0 1 0 0 0
06 0 1 0 0 0 0 0 1 0 0
07 0 0 1 0 1 1 0 0 1 0
08 1 0 0 1 1 1 1 0 0 1
09 1 1 0 0 0 0 1 1 0 0
10 0 1 1 0 1 1 0 1 1 0
11 1 0 1 1 0 0 1 0 1 1
12 0 1 0 1 1 1 0 1 0 1
13 1 0 1 0 1 1 1 0 1 0
14 1 1 0 1 1 1 1 1 0 1
15 1 1 1 0 1 1 1 1 1 0
RESULTS:
The output sequence is ….. 111100010011010

Auto Correlation: Zoth = 2.44V
Z1th = 1.74 V
Z2nd = 1.72V
Z3rd = 2.44V

LABORATORY MANUAL
PIN DIAGRAM OF IC 7495 ,7486:-
CITCUIT DIAGRAM:-

LABORATORY MANUAL
ARATUS USED:
SL. ITEM
NO.
1 Bread Board
2 CRO
3 Connecting Wires
4 IC 7495, IC 7486
PROCEDURE:-
1). Mount the IC 4795 and 7486 on the bread board.

2). Do the connection as given in the diagram.
3). Give the clock from the function generation.
4). Check the sequence generated the circuit and verify the truth table.
CONCLUTION:-
PRECAUTIONARY MEASURE TO BE TAKEN:
1) Check the +5V supply, GND supply, Power Connectors.

2) Connection should be tight
3) Component should be tested before performing the practical.
4) Check the data sources.
5) Check the data testers.
6) Check all the terminals.

LABORATORY MANUAL
EXPERIMENT NO: 2
EXPERIMENT TITLE:
STUDIES OF THE PROPERTIES OF A/D AND D/A CONVERTER
(AD7820/ADC0820 AND ICL 8018A/8019A/8020A). (PROPERTIES LIKE TRANSFER
CHARACTERISTICS, CODE CENTRAL LINE METHOD OF NONLINEARITY
STUDY, DIFFERENTIAL NONLINEARITY, INTEGRAL NONLINEARITY,
RESOLUTION ETC).
OBJECTIVE: This experiment will enable one to sense that to every input digital word a
single output analog value corresponds.
THEORY:-
The digital to analog converters compose the devices transforming a digital word binary
encoded and generated for example by a computer, into a discrete analog signal, in the sense
that to every input digital word a single output analog value corresponds.
The ideal characteristic of a 3 bit DAC is shown in Fig.1 and it is represented by the straight
line that connects the output discrete values corresponding to the single input digital data

LABORATORY MANUAL
An output voltage value depending on the converter full scale range

Corresponds to everyone of the 8 input stages, normally indicated with FSR
(Full Scale Range). If we define "quantum" Q the smallest variation of the output voltage, it
results
Q = FSR/2n where n is the bit number composing the input code: it is therefore evident that
the resolution of the digital number conversion depends on the n value.
The maximum FS (Full Scale) value of the output voltage is, on the contrary:
FS = (1-2n) FSR = (2n -1) Q
In Fig., in the hypothesis of FSR = 10 V, it results therefore
Q = 10 / 23 = 1.25 V
FS= (23-1) 1.25 = 8.75 V
Weighted Resistor D/ A Converter
The simplest D/ A converter is obtained by means of a summing circuit with input resistances
whose value depends on the bit weight that are associated to. We obtain in this way the
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LABORATORY MANUAL
weighted resistors converter whose diagram is shown in Fig.2 for the 4 bit case, where the
switches S3 -So are driven from the digital information so that every resistance is connected
to the reference voltage V REF or to ground in accordance with the fact that the
corresponding bit is at logical level 1 or o.
Let's consider now the possibility where only the most significant bit (MSB)
S3 is at level in the R resistance the current 13 = V REF / R will flow and therefore at the
operational amplifier output we will have the voltage
V 03 = -13 (R / 2) = -V REF /2
Analogously the contribution to output voltage provided by the immediately less significant
digit will result
V 02 = -12 (R / 2) = -(VREF / 2R) (R /2) = -VREF/ 4
and so on
Vo1=-II(R/2) -(VREF 14R) (R 12) = -VREFI 8
V 00 = 10 (R / 2) = -(VREF / 8R) (R / 2) = -VREF / 16
The operational amplifier works as current to voltage converter, by summing the currents in
the branches where the switch Si = 1, and it provides in output a voltage proportional to the
total current and therefore to the binary value of the input signal:
V0 = -VREF (8 .S3 + 4. S2 + 2 .Sl + 1 .So)
When all the bits are at logical level 1 the output voltage assumes the maximum full scale
value
VOFS = -0.9375 VREF
While the quantum that represents the minimum increase of the output voltage in
correspondence to the least significant bit (LSB) results Q = -0.0625 VREF The main
disadvantage of this converter is that resistances of different value in a very wide field are
demanded, above all at the increasing of the bit number, and therefore that can be carried out
with limited accuracy.
Note: In ST2602 the switches S3 -So are carried out with mechanical switches only for
simplicity and for educational reasons; in reality the integrated DAC use static switches
carried out in bipolar or CMOS technology.
D/ A CONVERTER WITH LADDER NETWORK:-
The weighted resistances converter has been among the first ones studied and carried
out but it has been then abandoned in favor of the configuration with ladder network that uses
only resistances of two values, one the double of the other. The converter with ladder
network (R -2R ladder) eliminates the disadvantages of the weighted resistances converter
since it is characterized by the presence of only two types of resistances, even if the
resistance number, with bit equality, now results double, as it is shown in Fig.3 for the 4 bit
possibility, where the switches S3 -So connect the corresponding resistance to the reference
voltage V REF or to ground in accordance with the fact that the corresponding bit finds itself
to logic level 1or o.
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LABORATORY MANUAL
If we suppose at first that all the input bits are at low level (S3 S2 Sl So = 0000) every
switch grounds the respective resistance 2R; in these conditions, since point V is a virtual
ground, the nodes A,B,C,D see toward ground, and in every direction, always the same
resistance 2R. Let's consider now the possibility where only the most significant bit S3 is at
level 1: the current 13, delivered from the reference voltage V REF, will divide in node A
into two identical currents but equal to the half of the incoming one, as it is shown in Fig.4
Being
I3 = VREF/2R+(2R//2R) = VREF/3R
The potential of node A against ground is equal to
VA3 =2R. 13/2 = (1/3).VREF
And therefore at the operational amplifier output the voltage results
V03 = -3 R/ 2R. (1/3) .VREF = -V REF/2
Analogously the contribution to the output voltage of the immediately less significant digit is
determined by noticing that the current delivered from the reference voltage V REF is equal
to
12 = VREF/2R+(2R//2R) = VREF/3R = I3
And it divides itself in node B into two identical currents of value 12/2: this now current will
split equally at node A so the potential of node A against ground is now equal to
VA2 = 2R. (12/4) = (1 16) .VREF
And therefore at the operational amplifier output the voltage results
V02 = -3R 12R. 1/6 VREF = -VREF /4
With analog reasoning we obtain.

I1= VREF /3R
VAl = 2R .(I1/8) = (1/12) VREF
V01 = -V REF / 8
And at the end
I0= VREF/3R
VAO = 2R (Io / 16) = (1 /24) VREF
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LABORATORY MANUAL
V00 = -V REF / 16
By applying the principle of effect superposition the output voltage results at the end
Vo = -V REF (8.S3 + 4. S2 + 2.S1 + I.So) /16
When all the bits are at logic level 1 the output voltage assumes the maximum full scale value
VOFS = -0.9375 VREF
While the quantum that represents the increase of the output voltage in correspondence of the
least significant bit (LSB), results
Q = -0.0625 V REF
PROCEDURE:
a). Connect the D0- D3 of the logic switches respectively to the B0- B3 of the converter.
b). Switch ON the power supply.
c). Connect the multi-meter as a voltmeter for DC, to the output V0 of the converter.
d). Connect the VREF to +5V.
e). Switch the logic switches in binary progression & measure & record the output voltage in
correspondence of every combination of the input code.
f). With input code S3 S2 S1 S0 =0000 the output voltage V0 has to be null:
Eventual little deviations against zero are due to the operational amplifier offset.
g). Repeat the test with sinusoidal signal.
h). Switch off the power supply.
OBSERVATION TABLE:-
S3 S2 S1 S0 V0 (V)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
ANALOG TO DIGITAL CONVERTER:-
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LABORATORY MANUAL
THEORY:-
The digital systems have been spreading considerably since they allow realizing
Complex functions accurately, low cost and in a way comparatively simple to implement.
Analog/digital converters are the natural interface between the world of physical quantities
that vary analogically i.e. in a continuous way and that of the digital control systems which
vary with finite increases. AID converters have numerous applications and consequently have
a high diffusion. Just think for example of the digital multi-meters. Each one of this contains
an AID converter for converting the analog quantity that has to be measured to corresponding
numerical value.
The analog/digital conversion is a logical process that requires conceptually two-steps: the
quantizing and the coding. Quantization is the process that performs the transformation of a
continuous analog signal in a set of discrete levels. Soon afterwards we combine through the
coding each discrete levels with a digital word.
The figure 1 shows what just said.
111
110
101 Q
100
011
010
001
000
1.25 2.5 3.75 5 6.25
The straight line is the continuous analog signal, while the staircase line is the quantized
corresponding signal. If we assume a binary code, the 8 quantized states are coded through a
3 bits digital word and this corresponds to the output of a 3 bits AID converter. The
sequences of binary numbers starting from "000" and reaching "111" are assigned to the 8
output states. Let us anal# in detail a few aspects of the quantized Signal. The first aspect is
the “ution'" defined as the number of output states that can be coded through a binary word of
n bits; with n bits we can code 2 n output states. In this case we have a 3 bits quantizer;
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LABORATORY MANUAL
therefore we code 8 output states whereas with 12 bits we code 4096 of them.. The diagram
n
showed in figure 1 point out that in the quantized signal there are 2 -1 = 7 threshold levels.
These points are at 0.625-1.875 -3.125 -4.375 -5.625 -6.875 -8.125 V. The threshold points
have to be set accurately to divide the range of the signal to quantize in correct quantized
signals. The voltages 1.25 -2.5 -3.75 -5 -6.25- 7.5 -8.75 V are the center points of each output
code word. The staircase quantization is the best possible approximation for a straight line
starting from the origin and reaching full scale. The range of the input voltage for which the
same output code is used is called "quantum". In figure 1, the quantum is 1.25 V. In general
the quantum is expressed by the relation:
n n
Q = FSR / 2 = Full scale range / 2
It is plain that the quantum is the lowest analog difference that can be discriminated at the
output. In case of a 12 bits quantizer, still with a full scale of 10 V the quantum is:
Q = 10/212 = 10/4096 = .00244 V = 2.44 mV
In figure 1 is also reported a curve called "quantizing error". This represents the error that
could not be eliminated, due to quantization. Increasing the bit number can reduce the error.
The uncertainty due to quantization and therefore the error due to quantization is ::!:: Q/2. An
AID converter requires a given time interval, even small, to perform the quantizing and
coding operations. This time is called "conversion time" and depends on several factors, as
the converter resolution, the conversion technique, the speed of the components used in the
converter.
During the conversion the signal can vary. Therefore the conversion speed
for a given application depends both upon the required accuracy and upon how much rapidly
varies the signal to convert. The conversion time is often called improperly "aperture time" ta
(Fig.2)
V(t)
∆V
ta
If the signal changes of ~ V during the version, we have an amplitude error ~ V which is ~ V
= ta. dV (t)/dt Where dV(t) /dt is the rate of change with time of the input signal. A signal
has not the same rate of variation everywhere, e.g. a sinusoidal signal has the biggest
derivative at the zero passage.
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LABORATORY MANUAL
COUNTER OR SERVO A/D CONVERTER:-
The AID converters use very different techniques to perform the analog/digital
conversion. The conversion speed and the resolution are the two guide criteria in choosing an
AID converter.
One of the more simple A/D converters is the counter one, see fig.3. This circuit uses a
digital counter to control the input of a D/ A converter. The clock pulses are applied to a
counter and the D/ A converter output is increased a step at a time of amplitude
corresponding to that of the less significant bit. A comparator compares the D/ A converter
output with the analog input and stops the clock pulses when the output of the D/ A converter
goes over the input signal. The counter output is therefore the converted digital word. Let us
see in detail how is performed the conversion. The oscillator is always working. The clock is
transmitted to the counter only when the AND input, connected to the comparator is in the
logic state high (" 1 ") or when the signal to convert is larger than the D/ A converter output.
CLK
& CTR Reset
MSB
LSB
DAC
Vi
Let us apply a reset control. The counter goes to "0000" and the converter gives zero voltage
at the output. The comparator results at high level at the output, the first pulse that leads the
counter to "0001" and the converter output to 0.625 is let go. The converter remains in the
starting state. When the new clock pulse passes the counter goes to "0010" and the DAC
output to1.25 V. The process continues until the counter receives the ninth pulse, its state
then becomes "1001" and the converter output goes to 5 .625 V and thus is larger than the
voltage to converter.
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LABORATORY MANUAL
The comparator output changes its state and so the clock pulses are not transmitted to the
counter any more. The word "1001" is then the digital conversion of 5.0 V. The used
converter allows the conversion of positive signals included in the range from 0 to 5 V and
has a maximum resolution of 0.625 V. The counter converter is conceptually simple and its
realization is of little difficulty and cheap. On the other hand it is rather slow in the
conversion. Moreover the conversion time is not constant but depends upon the value to
convert.
Successive approximation A/D converter the previous converter is simple but slow. We can
obtain largest conversion :) speeds to the detriment of simplicity. It is the case of successive;
approximation converters of which the board reports an example in an Integrated version.
The DAC performs the conversion in n steps where n is the converter J settlement in bits. The
working principle of this converter is analogous to that :) of weighing an object on a
laboratory balance, using standard weights as: J reference, according to the binary sequence
1,1/4,1/8, 1/16 1/n () kilograms. To perform accurately the measure, we have to start with the
largest standard weight and go on in decreasing order till the one of smallest weight. We
place the largest weight; if the balance doesn't tip we leave the weight and add the one from
the others of largest weight. If the balance doesn't tip we go on. If instead it does tip, we
remove the largest weight
Added and we replace it with the next one. After having tried n standard weights, the
weighing operation stops. The total of the standard weights remaining on the balance is the
closest approximation to the unknown.
We start by setting the bit 3, thus "1000". The corresponding voltage is worth 5 V and being
lower than the voltage to convert we leave it at "1 ". We set to "1" the bit 2 too. The word
turns into "1100" corresponding to 7.5 V which is larger than the voltage to convert. We put
therefore at zero the bit 2 and we proceed to the bit 1 and set it to "1". The corresponding
word "1010" is worth 6.25 V still larger than 5.0 V; we put than at zero the bit 1 and set to
"1" the bit O. The word turns into "1001" and is worth 5.625 V. This value is still larger than
5.0 V and so the reading jams at "1000" which is the digital conversion of the voltage 5.0 V.
We can see as in this case we have done only four comparisons to perform the conversion. In
the case of an
n bits converter are required n comparisons instead of the 2n foreseen, in the worst case, 'by
the previous converter. We have to make a precise statement: while the counter had convened
5.0 V into the word "1001 ", the successive approximation one converts into "1000". This is
because whereas the counter converter blocks the clock when the digital word goes over the
value to convert and so approaches in excess with the last significant bit, the successive
approximation converter approaches in deficiency.
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LABORATORY MANUAL
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BLOCK DIAGRAM OF A/D CONVERTER:-
FIG:-1
APPARATUS USED:
SL. ITEM
NO.
1 Trainer Kit
2 multimeter
5 Connecting Wires
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LABORATORY MANUAL
PROCEDURE:
1). Connect the power supply to the trainer.

2). Make the connections as shown in fig. 1.
a). Connect the DC supply to the Vi of the converter.
b). Keep the DC pot in counter clockwise position.
c). Place the Reset/Count switch in Reset position.
3). Switch ON the power supply.
4). Keep the DC pot at mid position.
5). To start the conversion, place the switch in Count position. The LEDs lit according to
binary sequence. When the signal from the D/A goes over the input signal, the counter stops
and the LEDs show the binary conversion.
6). Vary the DC pot and observe the corresponding Digital output. The converter will follow
the changes in the analog signal without resetting the converter in upward direction because,
the counter is configured as UP counter only, but to observe the converted output when the
input is being decreased, you have to reset the converter.
7). Observe on the oscilloscope the typical steps signal at the D/A output.
8). Repeat the test with different values of the input signal.
RESULT:-
Vi (V) D3 D2 D1 D0
CONCLUTION:-
1. Check the power supply, GND supply, Power Connectors.

2. Check the data &other signals sources.
3. Check all the Connectors within the kit.
4. Check all the terminals & other connectors with i/p & o/p devices.
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LABORATORY MANUAL
EXPERIMENT NO: 3
EXPERIMENT TITLE: Studies of PCM transmitter and receiver.(To measure the bit rate,
bandwidth requirement and distortion factor of the reconstructed signal in presence of
channel noise).
THEORY: PCM is the only digitally encoded modulation technique commonly used for
digital transmission. The term pulse code modulation as it is not really a type of modulation
but rather a form of digital signals. With PCM, the pulses are of fixed length and fixed
amplitude. PCM is a system where a pulse or lack of a pulse within a 1 or a logic 0
condition. PWM, PPM, and PAM are digital but seldom binary, as does not represent a single
binary digit (bit).Fig shows a simplified block diagram of a single-channel, simplex (only)
PCM system. The band pass filter limits the frequency of the analog input standard voice-
band frequency range of 300 Hz to 3000 Hz.
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LABORATORY MANUAL
FIGURE -2 Simplified block diagram of a single-channel, simple PCM transmission system

It periodically samples the analog input signal and converts those samples to a multilevel
PAM signal. The analog-to-digital converter (ADC) converts the PAM samples to parallel
PCM codes, which are converted to serial binary data in (he parallel-to-serial convener and
Union outputted onto the transmission line as serial digital pulses. The transmission line re-
peaters are placed al prescribed distances to regenerate the digital pulses.
In the receiver, the serial-to-parallel converter converts serial pulses received from the
transmission line to parallel PCM codes. The digital-lo-analog converter (DAC) converts the
parallel PCM codes to multilevel PAM signals. The hold circuit is basically a low-pass filter
that converts the PAM signals back to its original analog form.
Figure 6-2 also shows several clock signals and sample pulses that will be explained in later
sections of this chapter. An integrated circuit that performs the PCM encoding and decoding
functions is called a codec (coder/decoder), which is also described in a later section of this
chapter.
PCM SAMPLING
The function of a sampling circuit in a PCM transmitter is to periodically sample the con-
tinually changing analog input voltage and convert those samples to a series of constant-
amplitude pulses that can more easily be converted to binary PCM code. For the ADC to ac-
curately convert a voltage to a binary code, the voltage must be relatively constant so that the
ADC can complete the conversion before the voltage level changes. If not, the ADC would
be continually attempting to follow the changes and may never stabilize on any PCM code.
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LABORATORY MANUAL
Essentially, there are two basic techniques used to perform the natural sampling and flat-top
sampling. Natural sampling is shown is when tops of the sample pulses retain their natural
shape during the interval, making it difficult for an ADC to convert the sample to a PCM ,
the frequency spectrum of the sampled output is different . The amplitude of the frequency
components produced from sample pulses decreases for the higher harmonics in a (sin x)/x
manner Pi information frequency spectrum requiring the use of frequency equalizer) before
recovery by a low-pass filter.
The most common method used for sampling voice signals in top sampling, which is
accomplished in sample-and-hold circuit. The sample and-hold circuit is to sample the
continually changing. Convert those samples to a series of constant-amplitude PAM volt, the
input voltage is sampled with a narrow pulse and then hold until the next sample is taken.
Figure 6-4 shows flat-top sampling, 4 shows, the sampling process alters the frequency
spectrum and introduced aperture error, which is when the amplitude of the sampled signal
pulse time.
This prevents the recovery circuit in the PCM receive) Inducing the original analog signal
voltage. The magnitude of error of the analog signal voltage changes while the sample is
being taken and the width ' of the sample pulse. Flat-top sampling, however, introduces fewer
apertures natural sampling and operates with a slower analog-to-digital converter.
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LABORATORY MANUAL
FIGURE 3 Flat-top sampling: la] input analog signal;

[bl]sample pulse; [c] sampled output
Figure 6-5a shows the schematic diagram of a sample-and-hold

as a simple analog switch. When turned on, Qj provides a low-impede 11 analog sample
voltage across capacitor C,. The time that Q, is on is acquisition time. Essentially, Cj is the
hold circuit. When Qi is off (plate path to discharge through and, therefore, slores the
sampled \ i >11 of the capacitor is called the A/D conversion time because it is during. i
converts the sample voltage to a PCM code. The acquisition time show sure than a minimum
change occurs in the analog signal while it is 1 C,. If the input to the ADC is changing while
it is performing that.
APPARATUS USED:
SL. ITEM
NO.
1 Trainer Kit
2 multimeter
3 Connecting Wires
4 CRO
5 Function Generator
PROCEDURE:
1. Ensure that the MODE switch should be in FAST mode. (All faults switches are off
position)
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LABORATORY MANUAL
2. Connect CH 0 & CH 1 to DC1 AND DC2.

3. Ensure that the DC1 and DC2 controls in Function Generator Block should be in fully
clockwise direction and ~1 KHz and 2 KHz signal controls set art 10Vpp.
4. Now turn ON the kit and see that the LED glows.
5. With the help of Digital Voltmeter, adjust the DC1 amplitude control until the DC1 output
measures 0V.
6. Observe the output on the A/D Converter Block LED’s (D0 to D6). The LED’s represent
the state of the binary PCM word allocated to the PAM sample being processed.
7. Adjust the D.C input from +5V to –5V in steps of 1V.
8. Observe the output of +5V is as follows:
D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1
Where for the negative values it is less than 1000000.For –5V the output is as follows:
D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0
This is obtained at the approximately full anti clockwise position of the DC Control.
9. Turn the DC1 control fully anticlockwise and repeat the above procedure by varying the
DC2 control. 10. Trigger the dual trace oscilloscope externally by the CH.1 signal available
at t.p.12 and observe the signal at CH.0 and CH.1 at t.p.5 with reference to the signal at t.p.7.
11. Now connect the oscilloscope channel 1 to CH1 sample at t.p.6 and sketch the three
waveforms.
OBSERVATION:-
Truth table of quantizer:
Voltage(v) D6 D5 D4 D3 D2 D1 D0
CONCLUTION:-

23

LABORATORY MANUAL
EXPERIMENT NO: 4
EXPERIMENT TITLE: STUDIES OF PSK MODULATOR AND DEMODULATOR,

CONNECTED BY PHYSICAL CHANNEL.
OBJECTIVE:
Study of Carrier Modulation Techniques by Phase Shift Keying method.
THEORY
Phase-shift keying (PSK) is a digital modulation scheme that conveys data by changing, or
modulating, the phase of a reference signal (the carrier wave).
Any digital modulation scheme uses a finite number of distinct signals to represent digital
data. In the case of PSK, a finite number of phases are used. Each of these phases is assigned
a unique pattern of binary bits. Usually, each phase encodes an equal number of bits. Each
pattern of bits forms the symbol that is represented by the particular phase. The demodulator,
which is designed specifically for the symbol-set used by the modulator, determines the phase
of the received signal and maps it back to the symbol it represents, thus recovering the
original data. This requires the receiver to be able to compare the phase of the received signal
to a reference signal — such a system is termed coherent.
In Phase Shift Keying (PSK) modulation techniques, the modulated output switches between
in-phase and out-of phase component of the carrier frequency for all 'one' to 'zero' transitions.
The carrier frequency chosen for PSK modulation are 1 MHz (o Degree) and 1 MHz (180
Degree)
CARRIER GENERA TOR block on DCL-05 generates the carrier waves 1 MHz (0 Degree)
and 1 MHz (180 Degree), which are available at SIN 2 and SIN 3 post. The PSK modulator is
also built around the 2 to 1 Ana log Multiplexer which switches between the 1 MHz (0
Degree) and 1 MHz (180 Degree) signals for all 'one' to 'zero" transitions occurring in the
transmitted data stream.
The phase detector works in the principle of squaring loops. First step in PSK detection is the
sine to square wave conversion using a Schmitt trigger. This enables the PSK detector to be
built around digital IC's. The Biphase splitter basically doubles the frequency component of
the modulated data and also ensures that the out of phase component of the modulation signal
does not reach the PLL. The PLL recovers the carrier frequency from the output of the phase
splitter, but the frequency of the recovered carrier is twice that of the transmitted carrier. So a
Divide by 2 counters is used to divide the frequency of the PLL output by 2, thus recovering
the reference carrier. The delay flip-flop is used to compare the phase of the incoming data
and the reference carrier thereby recovering the data.
APPARATUS REQUIRED:
1). Experimental Kits Data Conditioning and Carrier Modulation (DCL-05) & Data
Reconditioning and Carrier Demodulation (DCL-06).
2). Power Supply
3). 20 MHZ Dual Trace Oscilloscope
4). Multi-meter
5). Patch Chords
24

LABORATORY MANUAL
PROCEDURE: (AS PER FIG: 1)
1. Refer to the block diagram and carry out the following connections and switch settings.
2. Connect power supply in proper polarity to the kits DCL-O5 and DCL-O6 and switch it on.
3. Connect CLOCK and DATA generated on DCL-O5 to CODING CLOCK IN and DATA
INPUT respectively by means of the patch-chords provided.
4. Note: 8th switch of SW1 from data pattern generator is not used to generate data pattern,
output remains at low level irrespective of this switch position.
5. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier Modulator logic.
6. Connect carrier component SIN 2 to INPUT1 and SIN 3 to INPUT2 of the Carrier
Modulator Logic.
7. Connect PSK modulated signal MODULATOR OUTPUT on DCL-O5 to the PSK IN of
the PSK DEMODULA TOR on DCL-O6.
8. Observe various waveforms as mentioned below.
FIG 1
OBSERVATION:
Observe the following waveforms on oscilloscope and plot it on the paper.

On Kit DCL-O5
1. Input NRZ-L Data at CONTROL INPUT.
2. Carrier frequency SIN 2 and SIN 3.
3. PSK modulated signal at MODULATOR OUTPUT.
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LABORATORY MANUAL
On Kit DCL-O6
1. PSK Modulated signal at PSK IN.
2. PSK Demodulated signal at PSK OUT.
3. Observe output of SINE TO SQUEARE CONVERTOR, SQUARING
LOOP, DIVIDE BY 2 on test points provided.
Waveforms:
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LABORATORY MANUAL
CONCLUTION:-
1). Ensure that equipment or training kit switch is kept off While connect it to main power
supply.
2). For connecting any signal from one equipment to another equipment or from one section
to other section of the same kit, ensure that signal is grounded properly and subsequently
connect the signal-to-signal line.
3). Handle gently all the necessary button or knob in the equipment avoiding all other button
or knobs which are not required to be adjusted for the equipment.
4). For unusual spark of burning smell, immediately switch off the main supply to the kit.
5). Ensure that, a signal is connected to an appropriate junction destined for it.
6). Always cover the equipment for dust protection after the experiment.
27

LABORATORY MANUAL
EXPERIMENT NO: 5
EXPERIMENT TITLE: FREQUENCY SHIFT KEYING MODULATOR AND

DEMODULATOR TECHNIQUES
OBJECTIVE: Study of Carrier Modulation Techniques by Frequency Shift Keying method:
THEORY:
In Frequency Shift Keying modulation techniques, the modulated output shifts
Between two frequencies for all 'one' (mark) to 'zero' (space) transitions. The carrier
frequency chosen for FSK modulation is 500 KHz and 1 MHz Note that the above
frequencies are greater than twice the modulating frequency. Note that the FSK may be
thought of as an FM system in which the carrier frequency is midway between the mark and
space frequencies, and modulation is by a square wave.
CARRIER GENERATOR block on DCL-O5 generates the carrier waves 500KHz and1
MHz, which are available at SIN1 and SIN2 post.
The FSK modulator is also built around the 2 to 1 Analog Multiplexer which switches
between the 500 KHz and 1 MHz signals for all 'one' to 'zero" transitions.
FSK describes the modulation of a carrier (or two carriers) by using a different frequency for
a 1 or 0. The resultant modulated signal may be regarded as the sum of two amplitude
modulated signals of different carrier frequency
s(t) = f1(t) sin (2π fC1 t + Φ) + f2(t) sin (2π fC2 t + Φ).
APPARATUS REQUIRED:
1). Experimental Kits Data Conditioning and Carrier Modulation (DCL-05) & Data
2). Power Supply
3). 20 MHZ Dual Trace Oscilloscope
4). Multi-meter
5). Patch Chords
28

LABORATORY MANUAL
BLOCK DIAGRAM OF FSK MODULATOR:-
PROCEDURE:
1. Refer to the block diagram and carry out the following connections and switch settings.
2. Connect power supply in proper polarity to the kits DCL-O5 and DCL-O6 and switch it on
3. Connect CLOCK and DATA generated on DCL-O5 to CODING CLOCK IN and DATA
INPUT respectively by means of the patch-chords provided.
4. Note: 8th switch of SW1 from data pattern generator is not used to generate data pattern,
output remains at low level irrespective of this switch position.
5. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier Modulator logic.
6. Connect carrier component SIN 1 to INPUT1 and SIN 2 to INPuT2 of the Carrier
Modulator Logic.
7. Connect FSK modulated signal MODULATOR OUTPUT on DCL-O5 to the
FSK IN of the FSK DEMODULATOR on DCL-O6.
OBSERVATION:
On Kit DCL-O5
2. Carrier frequency SIN 1 and SIN 2.
3. FSK modulated signal at MODULATOR OUTPUT.
On Kit DCL-O6
1. FSK Modulated signal at FSK IN.
2. FSK Demodulated signal at FSK OUT.
3. Observe output of PHASE DETECTOR, LPF, VCO on test points provided.
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LABORATORY MANUAL
EXPERIMENTAL DATA:
NOTE: In FSK demodulator PLL circuit used is very sensitive to input voltage level, because
of which you may get blurred output signal if input power varies slightly. To get clear signal
at the output tune pot P3 in FSK Demodulator section. To get better results set the following
bit pattern for INPUT DATA:
10101010
10101110
WAVEFORMS:
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LABORATORY MANUAL
Analysis:
A small phase lag exist between the modulating data and the recovered data because of the
limitation of tracking ability and the time response of PLL
FSK DEMODULATOR:-
Since the amplitude change in FSK waveform does not matter, this modulation technique is
very reliable even in noisy &fading channels. But there is always a price to be paid to gain
that advantage.
The price in this case is widening of the required bandwidth. The bandwidth increase depends
upon the two carrier frequencies used & the digital data rate. Also, for a given data, the
higher the frequencies & the more they differ from each other, the wider the required
bandwidth. The bandwidth required is at least doubled than that in the ASK modulation. This
means that lesser number of communication channels for given band of frequencies.
FSK DEMODULATOR BLOCK DIAGRAM:-
Switch Faults:
Note: Keep the connections as per the procedure. Now switch corresponding fault switch
button in ON condition & observe the different effect on the output. The faults are normally
used one at a time.
1. Put switch 1 of SF1 (DCL-O5) in Switch Fault section to ON position. This will open
capacitor for filtering of SIN 1 signal. Sine wave SIN 1 will be distorted and its amplitude
gets reduced.
2. Put switch 2 of SF1 (DCL-O5) in Switch Fault section to ON position. This VI/ill disable
channel selection signal going to Modulator IC. Modulator output contains only single
channel (INPUT 1) data.
Put switch 2 of SF1 (DCL-O6) in Switch Fault section to ON position. This will remove
resistor connected to PLL in FSK demodulator. Center frequency of PLL changes and output
of FSK demodulator gets distorted.
OBSERVATION:-
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LABORATORY MANUAL
CONCLUTION:-
1. Ensure that equipment or training kit switch is kept off While connect it to main power
supply.
2. For connecting any signal from one equipment to another equipment or from one section to
other section of the same kit, ensure that signal is grounded properly and subsequently
3. Handle gently all the necessary button or knob in the equipment avoiding all other button
or knobs, which are not required to be adjusted for the equipment.
4. For unusual spark of burning smell, immediately switch off the main supply to the kit.
5. Ensure that, a signal is connected to an appropriate junction destined for it.
6. Always cover the equipment for dust protection after the experiment.
32

LABORATORY MANUAL
EXPERIMENT NO: 6
EXPERIMENT TITLE: AMPLITUDE SHIFT KEYING MODULATION

TECHNIQUES
OBJECTIVE:
Study of Carrier Modulation Techniques by Amplitude Shift Keying method.
THEORY:
Carrier modulation is a technique by which digital data is made to modulate a continuous
wave (sine wave) carrier. For all types of carrier modulation, the carrier frequency should
be at least 2 times that of modulating frequency. In Amplitude shift keying, the carrier is
transmitted when the modulating data is 'one' and the carrier is rejected from transmission
when the data is 'zero'. In DCL-O5 the ASK Modulators employs an Analog Multiplexer
as a modulating switch, which can switch between carrier and ground, for every 'one' to
'zero' transitions. The carrier frequency chosen for ASK modulation is 1 MHz.
ASK DEMODULA TOR block on DCL-O6 employs an envelope detector to recover the
data from the modulated carrier. The ASK modulated input is fed to the half wave
rectifier. The rectified input is fed to the filter, where the original data is recovered. The
threshold detector is used to recover the original amplitude levels of the data. So
whenever the sinewave is transmitted, the detector identifies it as a 'one' and whenever
the carrier is absent, the detector identifies it as a 'zero'.
ASK describes the technique the carrier wave is multiplied by the digital signal f (t).
Mathematically, the modulated carrier signal s (t) is:
s (t) = f(t)sin(2π fC t + Φ)
33

LABORATORY MANUAL
APPARATUS REQUIRED:
• Experimental Kits Data Conditioning and Carrier Modulation (DCL-05) & Data
• Power Supply
• 20 MHZ Dual Trace Oscilloscope
• Multimeter
• Patch Chords
NOTE: KEEP THE SWITCH FAULTS IN OFF POSITION.

PROCEDURE:
1. Refer to the block diagram and carry out the following connections and switch
settings.
2. Connect power supply in proper polarity to the kits DCL-OS and DCL~O6 and
switch it on.
3. Connect CLOCK and DATA generated on DCL-OS to CODING CLOCK IN and
DATA INPUT respectively by means of the patch-chords provided.
4. Note: 8th switch of SW1 from data pattern generator is not used to generate data
pattern, output remains at low level irrespective of this switch position.
5. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier Modulator
logic.
6. Connect carrier component SIN2 to INPUT1 and GROUND to INPUT2 of the Carrier
Modulator Logic.
7. Connect ASK modulated signal MODULATOR OUTPUT on DCL-OS to the ASK
IN of the ASK DEMODULATOR on DCL-O6.
8. Observe various waveforms as mentioned below.
OBSERVATION:
On Kit DCL- O5
2. Carrier frequency SIN 2.
3. ASK modulated signal at MODULATOR OUTPUT.
On Kit DCL-O6
1. ASK Modulated signal at ASK IN.
2. ASK Demodulated signal at ASK OUT.
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LABORATORY MANUAL
WAVEFORMS:
Analysis:
It has been observed that a very small time lag between the modulating data and the
recovered data
Switch Faults:
Note: Keep the connections as per the procedure. Now switch corresponding fault
switch button in ON condition & observe the different effect on the output. The faults
are normally used one at a time.
1. Put switch 2 of SF1 (DCL-O5) in Switch Fault section to ON position. This will
disable channel selection signal going to Modulator IC. Modulator output contains
only single channel (INPUT 1) data.
35

LABORATORY MANUAL
CONCLUTION:-

1. Ensure that equipment or training kit switch is kept off While connect it to main
power supply.
2. For connecting any signal from one equipment to equipment or from one section to
other section of the same kit, ensure that signal is grounded properly and subsequently
3. Handle gently all the necessary button or knob in the equipment avoiding all other
button or knobs which are not required to be adjusted for the equipment.
4. For unusual spark of burning smell, immediately switch off the main supply to the kit.
5. Ensure that, a signal is connected to an appropriate junction destined for it.
6. Always cover the equipment for dust protection after the experiment.
36

LABORATORY MANUAL
EXPERIMENT NO. – 7
EXPERIMENT TITLE: Studies on Delta modulator & Demodulator using trainer kits.
OBJECTIVE: This experiment will enable one to understand how a Delta Modulator Circuit
can work to have a good result w.r.t PCM.This experiment will also help to understand the
operation of Digital modulation technique.
THEORY
Delta Modulation is a system of digital modulation developed after pulse code modulation. In
this system, at each sampling time, say the Kth sampling time, the difference between the
sample value at sampling time K and the sample value at the previous sampling time (K-1) is
encoded into just a single bit. i.e. at each sampling time we ask simple question:
Has the signal amplitude increased or decreased since the last sample was taken?
If signal amplitude has increased, then modulators output is at logic level 1.
If the signal amplitude has decreased, the modulator output is at logic level 0.
Thus the output from the modulator is a series of zeros and ones to indicate rise and fall of
the waveform since the previous value.
One way in which Delta modulator and demodulator is assembled is as show in Fig.
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LABORATORY MANUAL
38

LABORATORY MANUAL
THE DELTA MODULATCR WORKS as follows:

The analog signal which is to be encoded into digital data is applied to the +ve input of the
voltage comparator which compares it with the signal applied to its -ve input from the
integrator output (more about this signal in forth coming paragraph).
The Comparator's output is logic '0' or '1' depending on whether the input signal at +ve
terminal is lower or greater then the -ve terminals input signal.
The Comparator's output is then latched into a D-flip-flop which is clocked by the transmitter
clock, thus the output of D-flip-Flop is a latched '1' or '0' synchronous with the transmitter
clock edge.
This binary data stream is transmitted to receiver and is also fed to the Unipolar - to - Bipolar
converter. This block converts logic '0' to voltage level of + 4V and logic '1' to voltage level -
4V.
The Bipolar output is applied to the integrator whose output is as follows:
(a) Rising linear ramp signal when - 4V is applied to it, (corresponding to binary 1)
(b) Falling linear ramp signal when + 4V is applied to it (Corresponding to binary 0).
The integrator output is then connected to the - VE terminal of voltage comparator, thus
completing the modulator circuit.
Let us understand the working of modulator circuit with the analog input waveform applied
as below:
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LABORATORY MANUAL
Suppose at some time-instance t = 0, the integrator output voltage is lower than the analog
input. This causes the voltage comparator voltage to go high i.e. logic '1'. This data is latched
in the D-Flip-Flop at the rising edge of Transmitter clock. The latched '1'output of D-flip is
translated to - 4V by the Unipolar to Bipolar converter block. The integrator then ramps up to
catch analog signal.
At the next clock cycle t = 1, the integrator output becomes more than the analog input, so a
'0' is latched into D-Flip-Flop. The integrator now ramps downward as + 4V voltage signal
from Unipolar to Bipolar converter appears at its input. Thus the ramp signal again tries to
catch the fallen analog signal.
As we can observe, after several clock cycles the integrator output is approximation of the
analog input which tries to catch up the analog input at each sample time. The data stream
from D-flip-flop is the Delta Modulators Output.
The Delta demodulator consists of a D-Flip-Flop a Unipolar to Bipolar converter followed by
an integrator and a Low Pass Filter. The Delta demodulator receives the data from D-Flip-
Flop of Delta Modulator. It latches this data at every rising edge of receiver clock which is
delayed by half clock period with respect to transmitter clock. This has been done so that the
data from transmitter may settle down before being latched into the receiver Flip-Flop.
The Unipolar to Bipolar converter changes the output from D-FIip-Flop to either - 4V or +
4V for logic T and '0' respectively.
40

LABORATORY MANUAL
As it has been seen in case of modulator when the output from unipolar to bipolar converter
is applied to integrator, its output tries to follow the analog signal in ramp fashion and hence
is a good approximation of the signal itself. The integrator's output contains sharp edges
which are 'smoothened out' by the Low - Pass Filter, whose cut-off frequency is just above
the audio band.
DELTA MODULATION offers many advantages as listed below

* Simple System / Circuitry
* Cheap
* Single bit encoding allows us to increase the sampling rate or to transmit more information
at some sampling rate for a give system bandwidth
Unfortunately, the practical use of Delta modulation is limited due to the following severe
drawbacks.
(A) NOISE: Noise is defined as any unwanted unpredictable random waveform

accompanying the information signal. Whenever the signal is received at the received by any
communication medium, it is always accompanied by noise.
(B) DISTORATION : Distortion means that the receiver's output is not the true copy of the
analog input signal at the transmitter.
Distortion in delta modulation occurs due to, following causes: 1) Information Loss due to
rapid input changes.2) Overloading
As it has been seen, when the analog signal is greater then the integrator output,
the integrator ramps up to meet the analog signal. The ramping rate of integrator is constant.
Therefore if the rate of change of analog input is faster than the ramping rate, the modulator
41

LABORATORY MANUAL
is unable to catch up with the information signal. This causes a large disparity between the
information signal and its quantized approximation. This error / phenomenon is known as
slope - overloading and causes the loss of rapidly changing the information.
At first it may look as though the problem of slope overloading can be solved increasing the
ramping rate of the integrator. But as it can be seen from the figure the effect of the large
step-size is to add large sharp edges at the integrator output and hence it adds to noise
problem faced at receiver. This effect itself leads to distorted receiver output. Increasing
sampling rate cannot be the solution to the slope - overloading problem as it determines how
fast the samples are taken and not the ramping rate of the integrator.
FIG:-5
(C) Another problem with delta modulation is that it unable to pass DC information.
This is not a serious limitation of speech communication but for the systems like video
(picture) Transmission DC level does not provide information about brightness level of the
picture.
The above stated limitations of the delta modulation may be traded for acceptable price in
speech application but is totally unsatisfactory for music or video signals.
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LABORATORY MANUAL
APPARATUS USED:
SL. ITEM
NO.
1 Trainer Kit
2 CRO
5 Connecting Wire
PROCEDURE:-
Clock frequency selector switches: A= 0 and B=0 position

Integrator (1) blocks switches position:
Gain control switch position: Left hand side.
Switches position: A=0 and B=0 position.
Gain control switch position: Right hand side.
Switches position: A=0 and B=0 position.
1. Make connections as per diagram 7.
2. Ensure that the clock frequency selector block switches A & B are in A=0 and B=0
position.
3. Now turn on the kit and see that LED glows.
4. In order to ensure for the correct operation of the system, we first connect 0 volts to the
+ve input of the comparator. Now observe the output of the integrator 1 (i.e. tp 17) and the
output of transmitter’s level changer (i.e. tp 15). When the positive and negative output levels
of the level changer will be equal the output will be a triangular waveform as shown in fig 6
(Case A). When the negative level is greater than positive level, the integrator’s output level
will be as shown in fig 6 (Case B). And when the positive output level is greater, then the
integrator’s output will be as shown in fig 6 (Case C). The levels can be adjusted by turning
the potentiometer from one extreme to another.
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LABORATORY MANUAL
FIG:-6
5. Adjust the transmitter’s level changer preset until the output of integrator is a triangular
wave centered at 0 volts. The peak to peak amplitude of the wave should be 0.5 volts
(approx.), this amplitude is known as the integrator Step Size.
6. Now observe the output of the transmitter’s bi-stable circuit (i.e. tp 14). It is now a stream
of alternate ‘1’ and ‘0’. This is the output of a delta modulator and the Delta modulator is
now said to be balanced for correct operation.
7. Now examine the output of integrator at the receiver (i.e. tp 47). It should be a triangular
wave with step size equal to that of integrator in transmitter and ideally centered around 0
volts.
8. Now observe the output of low pass filter. It will be a DC level centered around 0 volts.
This is the output of Delta demodulator and it is balanced for correct operation
.
9. Now disconnect the 0 volts from the +Ve input of the comparator and reconnect it to 250
Hz signal of the function generator block. Now observe the output of voltage comparator (tp
9), integrator (tp 17). Also observe the delta modulated output at the output of bi-stable
circuit. It has been encoded into stream of ‘0’ and ‘1’
.
10. Also observe the output of low pass filter in the receiver (tp 51), which is the output of
demodulator.
11. Now disconnect 250 Hz from the +ve input of comparator and reconnect it to 500 Hz , 1
KHz, and 2 KHz outputs in turn. Now note the frequency of the analog signal increases, so
the low pass filter’s output becomes more distorted and reduced in amplitude. This effect is
known as ‘Slope Overloading’.
44

LABORATORY MANUAL
FIG:-7
OBSERVATION:-
CONCLUTION:-

45

LABORATORY MANUAL
EXPERIMENT NO. –8
EXPERIMENT TITLE: - STUDIES ON ADAPTIVE DELTA MODULATION AND

DEMODULATION USING TRAINER KITS.
OBJECTIVE:- This experiment will enable one to understand how an Adaptive Delta
Modulator and Demodulator Circuit can work to have a good result w.r.t delta modulator.
This experiment will also help to understand the operation of Digital modulation technique.
THEORY:-
As it has been seen, delta modulation system is unable to chase the rapidly
changing information of the analog signal which gives rise to distortion & hence poor quality
reception. This is known as slope overloading phenomenon. The problem can be overcomed
by increasing the integrator gain (i.e. step-size). But using high step-size integrator would
lead to a high quantization noise.
QUANTISATION NOISE:
It is defined as error introduced between the original signal & the quantized
signal due to the fixed step size in which the signal (quantized) is incremented. As the error is
random in nature & hence unpredictable, it can be treated as noise. High quantization noise
may play havoc on small amplitude signals. The solution to this problem is to increase the
integrator gain for fast-changing input & to use normal gain for small amplitude signals.
The basic idea is to increase the integrator the integrator gain (it is doubled on this trainer)
when slope overload occurs. If still it is unable to catch up with the signal, the integrator gain
is doubled again. The integrator on board has four available gains standard, standard X2,
standard X4, and standard X8. The integrator thus adopts itself to the gain where its lowest
value can just overcome the slope overloading effect. See fig. 6A.
the control circuit its output goes low. The counter now advances to 01 doubling the
integrator gain. This increases the ramping rate of the integrator & it is able to catch the
analog signal faster. In the next clock cycle if the same situation continues the counter
advances to '10' thus forcing the integrator gain to quadruple its standard value. This situation
continues till the counter advances to ' 11' where it remains locked until the control logic does
not detect a change in the bit level at its input
As soon as the control circuit detects a change in the bit level, its output goes high, thus
resetting the counter & thus normalizing the integrator gain.
In Adaptive Delta Demodulator the control circuit receives the same bit stream as the
transmitted one except for the fact that it is received after a half clock cycle delay. The
functioning of the Receiver's control circuit & counter is same as that of the transmitter's
block. Therefore, the demodulator’s output which itself is a good
Approximation of the analog input signal accepts for the inherent spikes. The output from
integrator is passed to a Low Pass Filter to 'smooth out 'the waveform. Thus, Adaptive Delta
Modulation system is thus able to reduce slope-over load error at an expense of small
increase in quantization error. It turns out that in matter of speech transmission the reduced
slope error provides a net advantage in spite of slight increase in quantization error & that the
adaptive delta.
46

LABORATORY MANUAL
Modulator can operate at the bit rate of 32 KB / S with performance comparable to that
obtained using PCM at 64 KB /S.
FIG: - A
Principle of Adaptive Delta Modulation
Functionally, the Adaptive Delta Modulator / Demodulator are shown.
As it can be observed, the Adaptive Delta Modulator is similar to the Delta Modulator except
for few blocks namely the counter & the control CKT.
The input to the control circuit is the latched data from the D Flip-Flop. The counter is reset
whenever 'high' appears at the output of the control circuit. Both the counter & the control
circuit are clocked by the same TX. CLOCK.
The input to the integrator from the counter is a two bit control word which controls the gain
of the integrator. When the output of counter is '00' the gain is lowest (standard) where as it is
highest (standard X8) for counters output '11*.
Control Word Integrator Gain

00 Standard
01 Standard X2
10 Standard X4
11 Standard X8
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LABORATORY MANUAL
FIG:- B
48

LABORATORY MANUAL
FIG:-C
THE CONTROL CIRCUIT WORKS AS FOLLOWS:

The control circuit compares the preset data bit from D flip-flop
with the previous two data bits. Its output to the counter is high when the three bits are
identical, the control circuits output goes low, thus letting the counter advance with every
clock cycle. This advancement continues till the output from the control circuit does not go
'high'. Each time the counter is incremented from 00 integrator gain is doubled till the counter
reached '11' where it remains in that state until it is reset by the counter. Similarly, the
Adaptive Delta Demodulator is alike Delta Demodulator except for two blocks namely, the
control circuit & the counter. They function in the same way as in modulator part, except for
the fact that they are clocked by the receiver clock.
Consider the Adaptive Delta Modulator in operation. In normal case, when slope overloading
is not occurring, the integrator output always hunt above & below the analog input even after
it has caught up with it. The output from the D-Flip-Flop is a constantly changing ' 1' to '0' at
each TX.CLOCK edge. Even when the analog input is changing at a slightly higher rate, the
integrator ramp output is able to catch it in two clock cycles. Thus the output of the D-Flip-
Flop is never a three or more consecutive '0' or T s.
The changing input to the control circuit ensures that its output to the counter is high & hence
the counter is 'rested' at every clock cycle. Thus the control word from counter is always '00'
forcing the integrator gain at its lowest value, thereby reducing quantization noise. Here the
Adaptive Delta modulator is behaving just as a Delta Modulator. Suppose, now a fast
changing analog signal appears at the input of the modulator such that the slope overloading
occur. The integrator output no longer follows the analog signal but it spends its time trying
to catch up the analog signal (either it ramps down or up continuously). As a result of
continuous ramping in one direction, the D-Flip-Flops output is either '0' or * 1' for three or
more consecutive time. As soon as the third continuous 1 / 0 is sensed by
49

LABORATORY MANUAL
APPARATUS USED:
SL. ITEM
NO.
1 Trainer Kit
2 CRO
5 Connecting Wire
PROCEDURES:
1. Connect the mains supply.
2. Connect the board as per figure D.
3. Ensure that the clock frequency selector switches A & B are in A=0 & B=0 position.
4. Ensure that the switches in TX. Integrator gain control block are in following positions. a)
Gain control switch at the L.H.S. position. (Towards switches A & B) b) Switches A & B in
position A=0 & B=0.
5. Ensure that the switches in receiver's integrator gain control block are in following
positions: a) Gain control switches at the R.H.S. position. (Towards switches A & B) b)
Switches A & B in Position A=0 & B=0.
6. Turn all the potentiometers of function, generator block namely 250Hz to 2 KHz to their
fully clockwise positions.
7. Turn ON the supply.
8. As the gain control switch is towards A & B switches the gain setting is still manual,
connect the voltage comparator's +ve input to 0V & check whether the modulator &
demodulator are balanced for correct operation as in delta modulation experimentation.
Change the clock frequency selector switches to the A=1, B=1, positions (256 KHz Clock
Frequency) before continuing.
9. Disconnect the voltage comparators '+' input from 0V and reconnect it to the 2 KHz output
from the function generator block.
10. Monitor the 2 KHz analog input at TP9 and the output of integrator 1 at TP17. Note that
slope overloading is still occurring, as indicated by the fact that the integrator's output is not
an approximation of the analog input signal.
11. At the transmitter, move the slider of the gain control switch in the integrator 1 block to
the right-hand position (towards the sockets labeled A, B). At the receiver, move the slider of
the gain control switch in the integrator 2 blocks to the left-hand position (again towards the
sockets labeled A, B). The gain of each integrator is now controlled by the outputs of the
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LABORATORY MANUAL
counter connected to it. Functionally, the transmitter and receiver are now configured as
shown in the figure 9 & 10 i.e. as adaptive delta modulator and demodulator respectively.
12. Once again examine the 2 KHz analog input at TP9 and the output of integrator 1 at
TP17, noting that the" slope overloading problem has been eliminated, and that the
integrator's output once again follows the analog input signal. Again, it may be necessary to
adjust slightly the transmitter's level adjust preset, in order to obtain a stable trace of the
integrator's output signal.
13. Compare the output of integrator 1 (TP17) with that of integrator 2 (TP47); noting that, as
expected, both are identical in appearance.
14. Examine the output of the low pass filter (TP51) and the output of integrator 2 (TP47).
The filter has removed the high-frequency components from the integrator's output signal, to
leave goods, clean 2 KHz sine wave.
15. Compare the original 2 KHz analog input signal (at TP9) with the output signal from the
receiver's low pass filter at TP47). Note that the demodulator's output signal is equal in
amplitude to the modulator's input signal, but is delayed somewhat.
16. Disconnect the voltage comparator’s '+' input from the 2 KHz function generator output,
and reconnected it in turn to the 1 KHz, 500Hz and 250Hz outputs, noting in each case that
the demodulator’s output signal is identical to the modulator's input signal, but delayed in
time.
17. The adaptive delta modulator/demodulator system has therefore eliminated any slope
overloading problems. To examine in detail how it does this, reconnect the voltage
comparator's '+' input to the function generator's 2 KHz output, then reduce the system clock
(i.e. sampling) frequency to 32 KHz, by putting the clock frequency selector switches in the
A=0, B=0 positions. Although a 32 KHz sampling frequency is too low to ensure that an
undistorted output is obtained from the demodulator's low pass filter, it does increase the step
size to a level, which makes it easier to understand how the system is operating.
18. Monitor the 2 KHz analog input signal at TP9 and at the output of integrator 1 (TP17). It
should now become a little clearer as to how the adaptive delta modulator is operating. It will
be noted that the slope of the integrator's output signal is no longer constant, but increases in
a series of discrete steps, in order to 'catch up' with the fast-changing analog input signal. If
the integrator output does not 'catch up' with the analog input within two clock periods of its
direction changing, the slope of the integrator's output signal. (i.e. the integrator gain) is
doubled. If it has still not caught up with the analog input signal by the end of the third clock
period, the integrator gain will once again be doubled. If the integrator output still lags behind
at the end of the fourth clock period, the integrator's gain is doubled once again, to its
maximum value. It then remains at this value until the integrator output 'catches up' with the
analog input signal. Once the integrators output 'overtakes' the analog input signal, its
direction changes, and its rate of change reverts to the minimum value.
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LABORATORY MANUAL
19. Examine also the test points in the adaptive control circuit 1 block (TP20-24), to ensure
you have a complete understanding of how the adaptive delta modulator is operating.
20. While monitoring the outputs of the modulator's binary counter (TP21 and 22), slowly
turn the 2 KHz preset anticlockwise, in order to reduce the amplitude of the 2 KHz analog
input signal. Notice that once the analog input signal becomes small enough, both the
counter's outputs becomes permanently low, causing the integrator to have minimum gain.
This happens because the input signal is now so small that the integrator can always follow it,
even with minimum gain. The result is that small-amplitude input signals can be transmitted
with minimum integrator gain, thereby keeping quantization noise to a minimum at the
demodulator’s output.
FIG:-D
7) Check the +5V supply, GND supply, Power Connectors.

8) Check the data sources.
9) Check the data testers.
10) Check all the terminals.
52

LABORATORY MANUAL
EXPERIMENT NO. –9
EXPERIMENT TITLE: STUDIES ON DELTA SIGNAL MODULATION USING

TRAINER KITS.
OBJECTIVE: This experiment will enable one to understand how an Delta Sigma
Modulator Circuit can work to have a good result(to pass DC level signal which is a must in
video system w.r.t delta modulator).This experiment will also help to understand the
operation of Digital modulation technique.
THEORY
The Delta Modulation & Adaptive Delta Modulation suffers from two serious
limitations, namely,
(1) They are not able to pass DC. Level information which is a must in video systems.
(2) The signal - to - noise ratio decreases as the signal frequency increases.
Both these serious limitations can be overcomed by Delta Sigma modulation.
The Delta Modulator on-board can pass DC level information if the integrators are zeroed
before hand (by level adjust presets) & the gains of integrator at two ends (TX & RX) are
exactly equal. This is possible on ST2105 board but not in real life operation where TX &
RX. are separated by hundreds of kms. & they are expected to work over a long period
without additional setting up.
The inherent short coming of the Delta Modulator to pass DC level information is due to the
fact that it passes the information about the change in the voltage level & not the actual
voltage level itself. It encodes the change from -2V to -IV same as it would encode a change
from +2V to +3V. J
In Delta Sigma Modulation the integrator is added hi front of the Delta sigma modulator.
This simple arrangement makes a big change in the circuit behaviors. It now responds to
actual voltage levels rather than the change in the voltage level.
The effect of the addition of integrator before the delta modulator can be done away by
adding a differentiator at the end of the receiver. The System looks as shown in
53

LABORATORY MANUAL
The system shown in the Figures can be simplified further. Since the voltage comparator is
highly non-linear device cannot transfer the two integrations at its input to one integration at
its output.
The voltage comparator functionally can be thought of as a unity gain differential amplifier
followed by a zero-crossing detector.
If the voltage comparator is replaced by this circuit, the no. of integrators can be reduced to
one (at the output of unit-gain differential amplifier).Similarly, since the low pass filter is a
linear circuit element the effect of integrator at the input of L.P.f...is nullified by the
differentiator present at its output. Therefore these two blocks are redundant in the receiver.
The resulting circuit looks as in Fig. 2A & 2B.
54

LABORATORY MANUAL
To see how the circuit functions, suppose that initially the TX.DATA is at logic * 1' & that
input remains constant at+2V.
Since logic 1 is present at the input of Unipolar-to-Bipolar converter, its output is-4V, which
appears at-VE terminal of unity gain differential amplifier. Its output soon switches to+6V.
This +6V appears at the input of integrator which ramps down at a fast rate. As soon as it
55

LABORATORY MANUAL
crosses zero level, the zero-crossing detectors output goes zero which is latched in the
coming clock cycle. Thus the D-Flip-Flops output goes low & a zero is transmitted.
The zero's appearance at input of unipolar to bipolar converter makes it switch its output to
+4V. With +4V input to the unity gain differential amplifier, its output goes to -2V level.
Since -2V signal is present at input of integrator; it ramps up slowly, as the rate of ramping
depends on the input applied to it. The ramp will not be able to cross-up zero at this slow rate,
so again a zero is latched at the next clock cycle. Thus the inference which can be drawn is
that smaller the signal at integrator input, slower it will ramp up or down thus latching the
same data bits for more clock periods.
Thus the mark to space ratio conveys the information about the mean level of the signal & the
signal & the modulator's output depends on the actual signal amplitude itself & not only on
its change.
The received data is latched into D-Flip-Flop by the Receiver clock which has been before
being latched. The level changer provides the +VE & -VE voltages needed to reconstruct the
input analog signal. It also inverts the signal & compensate for the inversion at transmitter
automatically. The work of the low pass filter is to remove the spikes introduced by switching
action of unipolar to bipolar converter.
ADVANTAGES OFFERED BY DELTA SIGMA MODULATION:
(1) The first & the foremost advantage of Delta Sigma Modulation is its ability to
transmit DC Level information.
(2) Receiver Simplicity, since there is no integrator in the demodulator circuit. With no
integrator in the receiver we do not have the problem of its quantization noise or ramping rate
limitation which leads to slope overload at high frequency, signals.
(3)With absence of integrator in receiver, the errors due to noise disturbances during
transmission are no cumulative.
(4)The signal - to - Noise ratio is independent of frequency of analog signal unlike in delta
modulation where it decreases as the frequency of information signal increases.
The received data is latched into D-Flip-Flop by the Receiver clock which has been before
being latched. The level changer provides the +VE & -VE voltages needed to reconstruct the
input analog signal. It also inverts the signal & compensate for the inversion at transmitter
automatically. The work of the low pass filter is to remove the spikes introduced by switching
action of unipolar to bipolar converter.
APPARATUS USED:
SL. ITEM
NO.
1 Trainer Kit
2 CRO
5 Connecting Wires
56

LABORATORY MANUAL
PROCEDURE:-
1. Connect the mains supply.
2. Make connections as per figure 3.
3. Confirm that the clock frequency selector blocks switches A & B are in position A=1 &
B=1.
4. Confirm the positions of various switches of integrator block's are in following position. a)
Gain control switch in L.H.S. position (near A & B switches). b) Switches A & B in A=1 &
B=1 position.
5. Turn ON the power supply.
6. The delta sigma system is currently being clocked at 256 KHz, as indicated by the current
positions of the clock frequency selector switches (A=1, B=1). Reduce the clock frequency to
128 KHz (switch positions A= 1, B=0), then 64 KHz (A=0, B=1), and finally to 32 KHz
(A=0, B=0), while monitoring the output of the demodulator at TP51. Note : That as the
clock frequency is reduced, so the analog output signal becomes less 'smooth', indicating that
clocking frequency affects the quality of the demodulator's output signal. Leave the system
clock frequency at 32 KHz, since it is easiest to analyze the operation of the delta sigma
system when the clock frequency is at minimum.
57

LABORATORY MANUAL
FIG:-3
7. In order to understand exactly how the delta-sigma modulator is working examine the
following signals: analog input (TP6), differential amplifier output (TP8), integrator output
(TP17), Voltage comparator output (TP11) and level changer output (TP15) Note : In the
case of signals at test points 8, 17, 11 and 15, trigger the scope on the analog input signal
(TP6), and if necessary trim the transmitter's level adjust preset (in the bi-stable & level
changer circuit 1 block) in order to obtain a stable, repeatable waveform.
8. At the demodulator, examine the bi-stable's data output (TP33), the level changer's output
(TP34), and the output of the low pass filter (TP51), to understand how the transmitted data
stream is demodulated.
9. Return the system clock frequency to 256 KHz (clock frequency selector switches in A=1,
B=1 positions), so that the demodulator's output once again becomes a good, clean sine wave.
10. While examining the modulator’s analog input TP6 and the receiver's low pass filter
output; increase the amplitude of the analog input signal to its maximum value, by turning the
function generator’s ~250Hz preset fully clockwise. Note: the peaks of the demodulator's
output signal become peak-to-peak amplitude if exceeds that of the transmitter's level changer
output, causing the modulator to 'saturate'. The result is a signal at the modulator's output
which contains long periods when a continuous stream of' ‘1’s or '0's is transmitted. These
long streams of the same digit are responsible for the flattening of peaks at the demodulator
output. This amplitude overloading is delta-sigma modulations equivalent of delta
modulation's 'slope over loading', and it occurs whenever the amplitude of the analog input
signal exceeds that of the transmitter's level changer output. Examine the signals at the delta-
sigma modulator and demodulator, in order to understand exactly how amplitude over
loading occurs.
11. Return the amplitude of the analog input signal to 5 volts P P by adjusting the ~250Hz
preset in the function generator block. While monitoring the output of the receiver's low pass
filter output (TP51), reduce the gain of the integrator 1 by putting the integrator's A, B
switches in the A=0, B=0 position. Note : That the demodulator's output becomes distorted;
this implies that there is a minimum integrator gain is necessary in the modulator circuit, in
order to guarantee correct operation of the delta modulator system. Reduce the amplitude of
the 250Hz analog input signal (by turning the ~250Hz preset anticlockwise), and notice that
the distortion can be removed by using an analog input signal of lower amplitude. Return
integrator 1's A, B switches to the A=1, B=1 positions before continuing.
12. Remove the differential amplifier's '+' input from the function generator's ~250Hz output,
and reconnect it in turn to the ~500Hz, ~1 KHz and ~2 KHz outputs. In each case, adjust the
amplitude adjustment preset for a sine wave of 5 volts P P (to avoid amplitude overloading),
and monitor the signal at the demodulator's output (TP51). Note: that the output is in each
case a good sine wave, and that there is no distortion as the frequency of the analog input
signal is increased.
58

LABORATORY MANUAL
13. Finally, connect the differential amplifier's '+' input to the function generator’s DC output
monitor the analog input (TP6) and the demodulated output (TP51), while turning the DC
preset from its fully anticlockwise (-4.7V) position to its fully clockwise (+4.7V) position.
Note that the demodulator's output changes accordingly, indicating that the delta- sigma
system can handle DC levels.
OBSERVATION:-

2. Check the data & other signals sources.
59

LABORATORY MANUAL
EXPERIMENT NO. –10
EXPERIMENT TITLE: - STUDY ON LINE CODER: POLAR/ UNIPOLAR/

BIPOLAR NRZ, RZ AND MANCHESTER.
THEORY:
The wave pattern of current or voltage used to represent 1s or 0s of a digital
signal on a transmission link is called line coding. Line coding consists of representing the
digital signal to be transmitted by amplitude and time discrete signal, which is optimally
tuned for the specific properties of the physical channel. The common types of line coding
are Unipolar, Polar, Bipolar and Manchester. Line codes are most widely used in computer
communication networks over short distances.
MODEL GRAPH
60

LABORATORY MANUAL
APPARATUS USED:
SL. ITEM
NO.
1 Trainer Kit ST-2106
2 CRO
5 Connecting Wires
PROCEDURE:-
1. Connect the OUTPUT of clock source to the CLOCK INPUT of parallel to serial
converter.
2. Feed the DATA OUTPUT of data source to the DATA IN of data format block.
3. Reset the data and set a binary D0 to D7.
4. Observe the input data, clock signal using CRO. Tabulate the observed readings.
5. Observe the output of various format of block, Plot the graph.
OBSERVATION TABLE:-
SL. NO SIGN AL AMPLITUDE(V) BIT DURATION(ms)
1 Data input
(Binary seq:)
2 Clock Signal
3 NRZ(L)
4 NRZ(M)
5 RZ
6 Biphase (Manchester)
7 Biphase (Mark)
8 RB
9 AMI
61

LABORATORY MANUAL

2. Check the data & other signals sources.
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DIGITAL COMMUNICATION LAB (CODE:EC691)

Narula Institute of Technology Department of ECE

GROUP - C (At least three experiments)

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EXPERIMENT TITLE: DESIGN, IMPLEMENTATION AND STUDIES OF THE

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SL. SHIFT RESISTER FEED BACK SHIFT STATE SHIFT O/P

The output sequence is ….. 111100010011010

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PIN DIAGRAM OF IC 7495 ,7486:-

Narula Institute of Technology Department of ECE

1). Mount the IC 4795 and 7486 on the bread board.

PRECAUTIONARY MEASURE TO BE TAKEN:

1) Check the +5V supply, GND supply, Power Connectors.

Narula Institute of Technology Department of ECE

Narula Institute of Technology Department of ECE

An output voltage value depending on the converter full scale range

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D/ A CONVERTER WITH LADDER NETWORK:-

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With analog reasoning we obtain.

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Narula Institute of Technology Department of ECE

The figure 1 shows what just said.

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Narula Institute of Technology Department of ECE

COUNTER OR SERVO A/D CONVERTER:-

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Narula Institute of Technology Department of ECE

Narula Institute of Technology Department of ECE

BLOCK DIAGRAM OF A/D CONVERTER:-

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1). Connect the power supply to the trainer.

PRECAUTIONARY MEASURE TO BE TAKEN:

1. Check the power supply, GND supply, Power Connectors.

Narula Institute of Technology Department of ECE

Narula Institute of Technology Department of ECE

FIGURE -2 Simplified block diagram of a single-channel, simple PCM transmission system

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Narula Institute of Technology Department of ECE

FIGURE 3 Flat-top sampling: la] input analog signal;

Figure 6-5a shows the schematic diagram of a sample-and-hold

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2. Connect CH 0 & CH 1 to DC1 AND DC2.

PRECAUTIONARY MEASURE TO BE TAKEN:

1. Check the power supply, GND supply, Power Connectors.

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EXPERIMENT TITLE: STUDIES OF PSK MODULATOR AND DEMODULATOR,

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PROCEDURE: (AS PER FIG: 1)

Observe the following waveforms on oscilloscope and plot it on the paper.

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Narula Institute of Technology Department of ECE

PRECAUTIONARY MEASURE TO BE TAKEN:

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EXPERIMENT TITLE: FREQUENCY SHIFT KEYING MODULATOR AND

OBJECTIVE: Study of Carrier Modulation Techniques by Frequency Shift Keying method:

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BLOCK DIAGRAM OF FSK MODULATOR:-

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Narula Institute of Technology Department of ECE

FSK DEMODULATOR BLOCK DIAGRAM:-

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