Chapter Two...

Lecture 4 CPU Registers

Processor Organization
 To understand the organization of the processor, let us
consider the requirements placed on the processor, the things
that it must do:
 Fetch instruction: The processor reads an instruction from
memory (register,cache, main memory).
 Interpret instruction: The instruction is decoded to determine
what action is required.
 Fetch data: The execution of an instruction may require
reading data from memory or an I/O module.
 Process data: The execution of an instruction may require
performing some arithmetic or logical operation on data.
 Write data: The results of an execution may require writing
data to memory or an I/O module.
Continued….
 To do these things, it should be clear that the processor
needs to store some data temporarily.
 It must remember the location of the last instruction so that
it can know where to get the next instruction.
 It needs to store instructions and data temporarily while an
instruction is being executed.
 In other words, the processor needs a small internal
memory.
 The major components of the processor are an arithmetic
and logic unit (ALU) and a control unit (CU).
 In addition, the processor consists of minimal internal
memory, consisting of a set of storage locations, called
registers.
CPU Registers
• The registers in the CPU can be classified into:
• User-Visible Registers
- Used for temporary storage of data while it is being processed
inside the CPU
• Control and Status Registers
- Used by the control unit to control the operation of the CPU

• The division between the two types is not set in stone.

• Some CPUs allow user access to registers that other CPUs
make non-user-visible.
User-Visible Registers
• Registers that may be referenced through the machine
language of the CPU:
• General Purpose Registers
- Can be used for many functions by the programmer.
- Quite often these are not 100% “general purpose”. For example,
some CPUs have separate “general purpose” registers for integer
and floating point operations.
- R0, … Rk

• Data Registers
- “General purpose” registers that can only be used while
manipulating data. (Specialized).
- May not be used in the calculation of an effective address.
… User-Visible Registers
• Address Registers
- May be used “General purpose” as well as addressing.
(Specialized).
- Ex: Segment Pointers, Stack Pointer, etc

• Condition Codes Register (flags)

- Partially user-visible
- The flags allow testing for conditional execution
- They are usually collected into one or more registers
- The flags may be read, but may not be altered directly
General Purpose or Specialized??
• If we use truly general purpose registers, then we will
have a large number of registers that can be used with
each instruction.
• More bits are needed in the operand specifiers to
specify the individual registers.
• If we use specialized registers, the opcode will have to
determine which set is being used.
How many registers??
• Too few results in too many memory references.
• Too many results in large number of bits and may not affect
memory references.

• ~32 registers is very reasonable.

• Newer processors contain > 100 registers.

• This is done to allow “register frames”.
How many bits per register??
• Address registers must contain at least as many bits as the
address bus.
• Data registers must contain at least as many bits as the data
bus.

• Possible to combine registers to form “extended” registers for

wider operations.
• Example:
- the register pairs in the 8085 microprocessor and the
“extended” registers in the x86 processors.
Registers & Sub-Routines
• In some machines, a sub-routine call results in the automatic
saving of all user-visible registers to be restored automatically
on return.
• Saving registers means “memory access” = time.
• May save registers that are not being used.

• In other machines, it is the responsibility of the programmer to

save and restore the registers being used.
• Too many “pops”.
• Not enough “pops”.
Control & Status Registers
• Most CPUs use a number of registers to control the operation.
• These registers can not be seen or altered through
“normal” programming techniques.
• Some CPUs allow “supervisor” or “operating system”
modes, where these registers can be altered directly.
… Control & Status Registers
• There are four registers that are common to most CPUs:
• Program Counter (PC)
- Always points to the next instruction.
- It is incremented after each instruction fetch.
- A branch/call instruction causes the new address to be
loaded into the PC.

• Instruction Register (IR)

- Each fetched instruction goes into the IR.
- Then its opcode and operands are decoded to decide
which operations are to be executed.
- The instruction decoder connects to the IR.
Control & Status Registers
• Memory Address Register (AR)
- Connects directly to the CPU’s address bus.
Addresses for memory references are placed in AR
before the memory reference is executed.
 Memory Data Register (DR)
- Connects directly to the CPU’s data bus.
- Data to be sent to memory during a memory write
operation is first transferred into DR before the
operation is executed.
- Data read during a memory read operation comes into
DR, then it is transferred to the internal general
purpose register specified in the instruction.
ALU Registers
• It is quite common for the ALU to contain its own registers.
• These are used for temporary storage of data while it is
being operated on in the ALU.
• Data is transferred to the ALU registers before an ALU
operation is executed.
• This simplifies the connections needed between the ALU’s
logic and the general purpose registers.
• AC
Example Register Organizations
• Intel 8085 8-bit microprocessor

8
AC
16
8 8
B C Data registers that can be
D E combined in pairs to form
H L Address registers

16
PC
User-visible control register
SP

Flags
 … Example Register Organizations
• Intel 8086 Microprocessor (16-bit)
• Every register is special purpose.
AX Accumulator
- Some are usable as general General BX Base
purpose Registers CX Count
DX Data
• 4 16-bit data registers
- Usable as 8-bit and 16-bit SP Stack Pointer
Pointers
• 4 16-bit pointer & index registers & BP Base Pointer
SI Source Index
Index
• 4 16-bit segment registers DI Destination Index

CS
• These registers acquire implicit Segment DS
meanings when used with some Pointers SS
instructions. ES
- Example, AX becomes
accumulator when arithmetic IP Instruction Pointer
PSW
instructions are being executed. Flags
… Example Register Organizations
• Motorolla 68000 Microprocessor (16-bit)
• Seventeen 32-bit registers
- 8 Data and 9 Address
- Data registers are used for data manipulation allowing 8, 16 and 32 bit
operations.
- Address registers are used for 32-bit addressing.
– No segmentation.
- Two registers are used for stack pointers (A7 and A7’).
– One for user stack and the other for system stack.
D0 A0
D1 A1
D2 A2
D3 A3
D4 A4
D5 A5
D6 A6
D7 A7 User SP
A7’ System SP
Program Counter
Status Reg.
… Example Register Organizations
• Intel 80386 Microprocessor (32-bit)
• The 8086 design is embedded into the new 32-bit register
design.

EAX AX
EBX BX
ECX CX
EDX DX

ESP SP
EBP BP
ESI SI
EDI DI

Instr. Pointer
Flags