A CMOS Current Mirror with Enhanced Input
Dynamic Range
Ying-Chuan Liu1, Hung-Yu Wang1, Yuan-Long Jeang2 and Yu-Wei Huang1
1
Department of Electronic Engineering, National Kaohsiung University of
Applied Sciences, Taiwan, R.O.C.
2
Department of Information Engineering Kun Shan University, Taiwan, R.O.C.
E-mail: hywang@cc.kuas.edu.tw
Abstract
˔ʳ ́̂̉˸˿ʳ ˶̂́˹˼˺̈̅˴̇˼̂́ʳ ̂˹ʳ ˖ˠˢ˦ʳ ˶˴̆˶̂˷˸ʳ ˶̈̅̅˸́̇ʳ
̀˼̅̅̂̅ʳ̊˼̇˻ʳ˸́˻˴́˶˸˷ʳ˼́̃̈̇ʳ˷̌́˴̀˼˶ʳ̅˴́˺˸ʳ̊˴̆ʳ̃̅˸̆˸́̇˸˷ˁʳ
The proposed mirror circuit combines the advantages
of wide input swing, wide output swing and large
output resistance capability which makes it attractive
for low-voltage application. Based on 0.18um MOS
model parameters, HSPICE simulation results show
that the input current range of 1uA to 1mA with
723MHz bandwidth for the proposed circuit.
1. Introduction
Nowadays, the demand for portable electronics has
made low power circuit design extremely desirable.
Reducing power supply voltage is a straightforward
method to achieve low power consumption. The low
power and low voltage CMOS techniques were applied
extensively in analog and mixed mode circuits for the
compatibility with the present IC technologies.
The current mirror (CM) is one of the most
common building blocks both in analog and mixed
mode VLSI circuits. Especially for active elements like
op-amps, current conveyors, current feedback
amplifiers etc, the current mirror is the integral part of
such components [1]. Though most current mirrors are
usually desired to have high output-impedance and
large output voltage signal swings, there are certain
applications, where designers is interested in having
large input voltage swings and large output voltage
swings. The use of current mirrors with low input
voltage is especially important for implementation of
VLSI test circuits which employ current sensing
techniques [2]. Besides, some terminals of the current
conveyor and four-terminal floating nullor have
current following properties which are operated in
dynamic state. The larger input current swing thereby
voltage swing is necessary for their implementation.
In this article, we present a level shifted low
voltage ˖ˠˢ˦ʳ ˶˴̆˶̂˷˸ʳ ˶̈̅̅˸́̇ʳ ̀˼̅̅̂̅ʳ ̊˼̇˻ʳ ˸́˻˴́˶˸˷ʳ
˼́̃̈̇ʳ˷̌́˴̀˼˶ʳ̅˴́˺˸ˁʳThe proposed circuit makes use of
The 3rd Intetnational Conference on Innovative Computing Information
and Control (ICICIC'08)
978-0-7695-3161-8/08 $25.00 © 2008 IEEE
both the high input swing and high output swing
techniques. HSPICE simulation results confirm the
input current range of 1uA to 1mA with 723MHz
bandwidth. The popular low voltage cascode current
mirror structure was also simulated for comparison.
2. Proposed Circuit Structure
The popular low voltage cascode current mirror
was presented in [3], as shown in Fig. 1. It is assumed
that the mirror transistors M1 and M2 have identical
aspect ratio, i.e. AM = W1/L1 = W2/L2 where W1, W2,
L1, and L2 are the transistor channel widths and lengths
for transistors M1 and M2, respectively. Similarly, the
cascode transistors M3 and M4 are assumed to have the
same aspect ratio, AC = W3/L3 = W4/L4. The body
effect is ignored and it is assumed that all NMOS
transistors have the identical threshold voltage Vtn and
transconductance parameter k. To ensure saturation of
M1 and M3, the biasing voltage VB in Fig. 1 should be
VGS 3  (VGS 1  Vtn ) d V B d VGS 1  Vtn (1)
To ensure the saturation operations of M1 and M3, the
input current range can be expressed by
k k AC / AM 2
AM (VB 2Vtn )2 d Iin d AM (VB Vtn )2 ( )
2 2 1 AC / AM
(2)
In Fig. 1, as Iin increases, VGS3 and Vin will increase.
Because the biasing voltage VB is fixed, the voltage
level at the drain terminal of M1 decreases. Thereby M1
may enter into the triode region which determines the
upper limit of Iin.
The level shifted current mirror with the advantage
of low input and output voltage requirements [5, 6] is
redrawn in Fig. 2. Transistor M5 shifts the voltage
level at the drain terminal of M1. The input compliance
voltage (Vin1) is a characteristic parameter which
decides the range of input voltage swing in such
circuits. The magnitude of bias current (Ibias1) decides
the operational region of M5. The input current (Iin1)
 and the externally applied voltage (Vo1) at drain
terminal of M2 decides the operational region for M2.
The Ibias1 and Iin1 decide the operating region of M1.
The most suitable operational mode is operation of M5
in sub-threshold region while M1 operates in sub-
threshold region for low input currents and in
saturation region for high input currents.
Fig. 1 Low voltage cascode current mirror
Fig. 2 Level shifted current mirror
The proposed level shifted low voltage cascode
current mirror structure is shown in Fig. 3. It combines
the techniques of low voltage cascode current mirror
with level shifted current mirror to achieve larger input
voltage dynamic range for low voltage operation. The
operation of M5 and M3 in Fig. 3 is similar to the
operation of M5 and M1 in Fig. 2. Here we adopt the
same assumption as the above mentioned low voltage
cascode current mirror and assume the threshold
voltage of M5 is Vtp. In Fig.3, to turn on the transistor
M5 and M3, the conditions VSG5 > |Vtp| and VGS3 > Vtn
must be satisfied. Since |Vtp| > Vtn, there is a difficulty
The 3rd Intetnational Conference on Innovative Computing Information
and Control (ICICIC'08)
978-0-7695-3161-8/08 $25.00 © 2008 IEEE
to keep the condition VDS3 > 0 valid in the circuit over
a wide range of Iin2. Therefore, there may be many
possible combinations in which transistor M5, M3 and
M1 can operate. However, after the investigation of
various cases, it can be found that the most suitable
operational mode is operation of M5 in sub-threshold
region while M3 and M1 operate in sub-threshold
region for low input currents and in saturation region
for high input currents.
Under the assumption that VSD5 > 3VT, the sub-
threshold drain current of M5 can be expressed by
W5 VSG 5  | Vtp |
I bias 2 | I DO 5 exp( ) (3)
L5 nVT
where W5 and L5 respectively represent the channel
width and length for M5, and VT( | 26mV for room
temperature) is the thermal voltage. The constants n
and IDO5 are process parameters. Typical value of IDO5
§ 20 nA and n lies between 1.2 and 2.0 [7, 8]. For the
sub-threshold operation of M5 (VSG5 § |Vtp| [6]) and
saturation operation of M1 and M3, we find
2 2
kACVSG kA V
I in 2 d 5
d C tn (4)
2 2
A § A ·
Vtn d Vin2 d VSG5 C Vtn d Vtn ¨1 C ¸ (5)
AM ¨ AM ¸¹
©
When M5, M1 and M3 are in sub-threshold region; the
gate to source voltages of M5, M1 and M3 are almost
near to their threshold voltages. We can find
I DO1W1
I in 2 d (6)
L1
I in 2 L1
Vin 2 nVT ln( )  Vtn d Vtn (7)
I DO1 W1
For the sub-threshold operation of M5, when Iin2
increases thereby Vin2 increases, transistor M5 shifts the
voltage level at the gate terminal of M3, Therefore, this
CM has improved upper limit of the input current as
compared with the above low voltage cascode CM.
The current through M5 should be small enough to
keep M5 in sub-threshold region. Correspondingly
W5/L5 ratio should also be large. Besides, the current
through M3 and M1 should be large to keep it in
saturation region. When input current (i.e. Iin2) is low,
M3 and M1 will operate in sub-threshold region. If only
M5 operates in sub-threshold region and M1-M4 are
restricted to operate in saturation region, this CM will
possesses better frequency response and the lower
 limit of the input current is slightly higher. And the response of the proposed CM. It shows that the
minimum output voltage necessary for the proposed bandwidth is about 723MHz.
CM is equal to:

2I in 2I in
Vo 2,min VGS 2  VGS 4  2Vtn  (8)
kAM kAC
Since M5 sets the dc operating point, its operation in
sub-threshold region does not degrade the frequency
response. If M1-M4 operate in sub-threshold region, the
structure can not have high bandwidth.

Fig. 4 Input characteristics of both CMs

Fig. 3 Level shifted low voltage cascode current

3. Simulation results
To verify the potentialities of the proposed Fig. 5 Current transfer characteristics of both CMs
configuration, circuit simulations of the proposed level
shifted low voltage cascode CM (Fig. 3) and low
voltage cascode CM (Fig. 1) have been carried out
based on the level 49 MOS model parameters provided
Table 1 W/L for various transistors of the CMs
by the TSMC 0.18um CMOS technology with a DC
supply voltage of r1V. The VB in Fig. 1 and Ibias2 in
Fig. 3 are assumed to be -0.2V and 0.3uA, respectively.
CM shown W/L
Selection criterion for VB is to ensure the saturation MOSFETs Type
in figures (um/um)
operations for M1 and M3. Ibias2 is selected to ensure M5
operate in sub-threshold region so VSG5 is slight lower
than Vtn. Table 1 shows the aspect ratios of different M1,M2,
NMOS 1, 3 20/0.5
transistors of the CMs. The input characteristics of M3, M4
both CMs are shown in Fig. 4. The current transfer M5 PMOS 3 10/0.3
characteristics of both CMs are shown in Fig. 5. It can
be observed that the proposed CM has improved
inputted dynamic range. The output characteristics for
various input currents of the proposed CM are shown
in Figs. 6 and 7. Fig. 8 shows the magnitude frequency

The 3rd Intetnational Conference on Innovative Computing Information

and Control (ICICIC'08)
978-0-7695-3161-8/08 $25.00 © 2008 IEEE

Fig. 6 Output characteristics at high currents
Fig. 7 Output characteristics at low currents
Fig. 8 Frequency response of the proposed CM
4. Conclusion
A novel level shifted low voltage cascode current
mirror with large output resistance and enhanced input
current dynamic range was presented. A MOS
transistor operated in sub-threshold region is used as a
level shifter. The low bias current is also an attractive
feature for low power applications.
The 3rd Intetnational Conference on Innovative Computing Information
and Control (ICICIC'08)
978-0-7695-3161-8/08 $25.00 © 2008 IEEE
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