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JFET CHARAC TERISTICS

Experiment-449 S

JFET CHARACTERISTICS
Jeethendra Kumar P K
KamalJeeth Instrumentation & Service Unit, Tata Nagar, Bengaluru-560 092, Karnataka, INDIA
Email: labexperiments@kamaljeeth.net

Abstract
Input characteristics (transconductance) curve and output characteristics (drain)
curves of an n-channel junction field effect transistor (JFET) are determined using a
BFW-10 JFET. From these characteristic curves, maximum drain current, IDSS; pinch-
off voltage, VGS(off); and drain-source resistance, RDS(on) are determined and
compared with the corresponding standard values. The drain current equation is
also verified.

Introduction

A junction field effect transistor (JFET) is a uni-polar semiconductor device in which


only one type of charge carriers are involved in conduction. A JFET or FET differs from
a bipolar transistor in several ways. The most important being that in a bipolar
transistor the small input (base) current controls the large output (collector) current,
making it a current controlled device. In the case of a FET, it is the input voltage that
controls the output current making it a voltage-controlled device. The output drain
current is controlled by the electric field across the conducting channel of the
semiconductor, from which the name field effect transistor has been derived.

There are two types of FETs. The Junction FET in which the control electrode or gate is
isolated from the conducting channel by a reverse biased junction and in the insulated
gate field effect transistor (or MOSFET ) a layer of silicon dioxide is used to insulate the
control electrode making it a very high input resistance device.

An n-channel JFET consists of n-type silicon bar in which two p-islands are deposited
that are interconnected and called as the gate (G) terminal. The lower portion of the bar
is called source (S) and upper portion of the bar is called drain (D). Figure-1 shows the
schematic structure, symbols and the base diagram of a JFET. Similarly a p-channel
JFET has p-bar and n-type islands. In the schematic representation, for a p-channel
JFET the direction of the arrow at the gate is reversed.

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JFET CHARAC TERISTICS

Figure-1: Structure, symbols and the base diagram of an N-channel JFET


The gate controls the flow of current through the bar by modifying its resistance. When
no potential is applied to the gate, the bar has maximum resistance, called the source-
drain resistance, RDS (on). For this biasing condition, the source-drain resistance is
minimum, and hence the maximum current flows from source to drain. This maximum
current is called IDSS. Under these conditions the two p-islands form very thin depletion
layers around them and provide large space for the electrons to flow from the source to
drain.

As negative gate voltage is applied with respect to the source, the depletion regions
grows which makes it difficult for electrons to flow from source to drain, hence the
drain current is reduced. As the negative gate voltage is increased further, the drain
current will decrease further and become zero at a voltage at which the depletion
regions come very close to each other around the two islands making difficult for
electrons to pass through. This gate voltage at which the drain current becomes zero is
called “pinch-off voltage” or VDS(Off).

For low drain-source voltage (VDS), the two depletion regions are thin and the current
increases with the applied voltage linearly, initially with increase in VDS. As VDS
increases, the two depletion layers come closer (but never touch each other) and the
drain current thereafter remains constant with further increase in the VDS value.

Hence the current flowing from source to drain is called drain current and it is
controlled by gate voltage [1, 2]. The drain current is given by:

୚ృ౏ ଶ ୚ృ౏ି୚ీ౏ ଶ
Iୈ = Iୈୗୗ ൤ቀ1 − ቁ − ቀ1 − ቁ ൨ …1
୚ౌ ୚ౌ

where VDS is drain-source voltage,


VGS is gate –source voltage,
VP is pinch-off voltage, and
IDSS is maximum drain current.

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JFET CHARAC TERISTICS

Equation-1, giving the ratio of current and voltage, represents a non-linear curve;
hence it is called transconductance curve or input characteristic curve. The input is
voltage (VGS) and output is current (ID), the maximum value of which gives the
maximum transconductance as

ିଶ୍ీ౏౏
gmo = ୚ౌ
…2

where gmo is the maximum value of transconductance ( for VGS=0),


IDSS is the maximum drain-source current (for VGS=0), and
VP is the pinch-off voltage.

Knowing the maximum value of transconductance, gmo, transconductance for any gate-
source voltage can be calculated using the Equation

୚ృ౏
gm = gmo ቂ1 − ቃ …3
୚ౌ

Equation-3 represents a parabolic curve.

The other parameter associated with JFET is the drain source resistance and its variation
with the source gate voltage is given by

୚ృ౏
RDS = RDS(on) ቂ1 − ୚ౌ
ቃ …4

where

୚ౌ
RDS(on =- …5
ଶ୍ీ౏౏

Apparatus used

The experimental setup for studying JFET characteristics consists of a dual power
supply -0-5V and 0-10V, digital DC voltmeter 0-20V, and digital DC milli-ammeter 0-
20mA. Figure-3 shows the experimental set-up used.

Figure-2: Circuit connections for studying JFET characteristics

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JFET CHARAC TERISTICS

Figure-3: Experimental set-up of FET-201 of KamalJeeth make for studying JFET


characteristics

Experimental procedure

The experiment consists of four parts, namely

Part-A: Determination of maximum drain current, IDSS


Part-B: Determination of the pinch-off voltage, VP (VGS (OFF))
Part-C: Transconductance curve (Input curve)
Part-D: Output characteristics curve for different values of gate source voltage

Part-A: Determination of maximum drain current, IDSS

1. The circuit connections are made as per the circuit diagram shown in Figure-2 and
the BFW-10 JFET is fixed into to the socket, as shown in Figure-3.

2. The gate-source voltage is set to 0V, by adjusting the voltage control knob of VGG
power supply

VGS =0V

3. The drain-source voltage VDS is now set to its maximum value by adjusting the two
(coarse and fine) knobs of the VDD power supply and maximum drain current is
noted as

IDSS = 10.45mA

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JFET CHARAC TERISTICS

Part-B: Determination of the pinch-off voltage, VP (VGS (OFF))

4. The negative gate-source voltage is now slowly increased by observing the decrease
in the drain current until it becomes zero.

ID =0

5. The gate voltage is now measured by connecting the voltmeter across the VGS
terminal, as shown in Figure-4.

VP= VGS(OFF) = -3.11V

Figure-4: Determination of the pinch-off voltage

Part-C: Transconductance curve (Input curve)

6. To draw the transconductance curve, first VGS is set to 0V and VDS is set to 5V and
the value of current ID is noted.
ID = 10.45mA

7. The experiment is repeated by setting VGS =-0.5V and VDS is set as 5.0V and the drain
current is noted.

ID = 7.9mA

8. The experiment is repeated for VGS =-1.0V, keeping VDS constant at 5V throughout.
The readings obtained are tabulated in Table-1. The graph giving the variation of
drain current with gate voltage is shown in Figure-5 from which the value of VP is
noted as

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JFET CHARAC TERISTICS

VP =-3.0V

The maximum transconductance, gmo, can be calculated using Equation-2 as

ିଶ୍ీ౏౏ ିଶ௫ଵ଴.ସହ௫ଵ଴ షయ
gmo = ୚ౌ
=- ିଷ.଴
= 6.96x10-3 mho

Table-1: Variation of drain current with gate voltage


Transconductance Curve VDS = 5.00V
Gate-Source Drain current ID
Voltage VGS(V) (mA)
0 10.45
-0.5 7.90
-1.0 5.73
-1.5 3.73
-2.0 2.23
-2.5 0.83
-3.0 0.01

Figure-5: Transconductance curve of BFW-10 JFET for VDS=5V

Part-D: Output characteristics curve for different values of gate source


voltage

9. In this part of the experiment, keeping VGS constant, the variation in ID is observed
with respect to VDS.

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JFET CHARAC TERISTICS

10. First keeping VGS = 0, the VDS versus ID variation is studied. VDS is varied in steps of
0.1V from 0V up to 2V and from 2V onwards it is varied in steps 0.2V up to 3V, and
from 3V to 5V in steps of 1V. Table-2 gives the observed voltage and current
variations.

Table-2: Drain current variation with Drain-source voltage at different Gate voltage
Drain Current ID (mA)
VDS (V) VGS = 0V VGS = -1.5V VGS =-2.5V
0 0 0 0
0.1 0.69 0.39 0.11
0.2 1.34 0.71 0.23
0.3 1.92 1.02 0.30
0.4 2.60 1.33 0.37
0.5 3.16 1.64 0.42
0.6 3.67 1.89 0.46
0.7 4.24 2.13 0.48
0.8 4.77 2.35 0.51
0.9 5.21 2.53 0.52
1.0 5.62 2.70 0.54
1.2 6.43 2.96 0.56
1.4 7.21 3.17 0.58
1.6 7.81 3.31 0.60
1.8 8.28 3.43 0.61
2.0 8.71 3.51 0.62
2.2 9.12 3.58 0.63
2.4 9.39 3.62 0.64
2.6 9.62 3.67 0.65
2.8 9.79 3.70 0.66
3.0 9.99 3.72 0.67
4.0 10.37 3.83 0.70
5.0 10.46 3.88 0.73

11. From the above figure it is noted that after reaching the pinch off voltage, the
current subsequently remains constant. The small change in the current thereafter is
due to the thermal heating of the JFET that can be observed by touching it with a
finger.

12. A graph is drawn taking VDS along X-axis and ID along Y-axis as shown Figure-6.
This is the output characteristics curve of the JFET.

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JFET CHARAC TERISTICS

13. The JFET is removed from the socket and its source-drain resistance is measured
using a digital multimeter.

RDS(on) = 160Ω
This can also be calculated from Equation-5 as

୚ ଷ
RDS(on =- ଶ୍ ౌ = ଶ୶ଵ଴.ସହ = 143.5Ω
ీ౏౏

Equation-1 can also be verified, for example for VGS =-1.5V and VDS = 1V, one
obtains

ID = 2.32mA, which is close to the value 2.7mA, as given in Table-2.

Figure-4: Output Characteristics of BFW-10 JFET

Results

The characteristic parameters of BFW-10 JFET obtained are listed in Table-3 as

Table-3: Experimental results


Parameter Experimental Standard
IDSS (mA) 10.45 <20
Vp (V) -3.1V <-8V
RDS(ON) (Ω) 149 160*
gmo (mS) 7 <12
*Measured value

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JFET CHARAC TERISTICS

Discussion

1. The output characteristics curves, or the drain curves, of the BFW-10 JFET resemble
that of transistor output characteristic curves, with the difference that the base
current IB is replaced by VGS. The value of the saturation voltage is higher in a JFET
compared to a transistor which is around 0.3V for a silicon transistor.

2. The transconductance curve meets the Y-axis at a point giving the maximum value
of the drain current IDSS and meets the X-axis at a point giving the maximum value
of the voltage Vp.

References

1. A P Malvino, Electronic Principles, TMD Ed 3rd Ed, 1987, Page-321

2. W Goswng, W G Townsend, J Watson, Field Effect Electronics, Butterworth


London, Page-18

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