Interfacing
Analog signals are very common inputs to embedded systems .Most transducers and sensors
such as temperature ,pressure ,velocity ,humidity are analog. Therefore we need to convert
these analog signals in to digital so that 8051 can read it.
ABOUT IC
PinOut
• CS – Chip Select , active low
• RD – Read Digital data from ADC, H-L edge triggered
• WR -- Start conversion, L-H pulse edge triggered
• INTR -- end of conversion, Goes low to indicate conversion done
• Data bits -- D0-D7
• CLK IN & CLK R
– CLK IN is an input pin connected to an external clock source when an external clock is used
for timing. However, ADC804 has an internal clock
generator.
To use the internal clock generator of the ADC804, the CLK IN and CLK R pins are connected
to a capacitor and a resistor. In that case, the
clock frequency is determined by the equation.
f = 1/1.1RC
R=10K and C=150pF f=606Hz
the conversion time is 110us.
Vref/2 Vin
Input Voltage range Step size (mV)
(Volts) (Volts)
• Default 0-5V. Can be changed by setting Open (2.5) 0 to 5 5/256 = 19.53
different value for Vref/2 pin. 2.56 0 to 5.12 5.12/256 =20
Vin=Vin(+) – Vin (-) 1.28 0 to 2.56 2.56/256 = 10
0.5 0 to 1 1/256=3.90
• Range = 0 to 2x Vref/2.
for Vin = 2x Vref/2. we
get 256 as a digital output on
D0-D7. (Refer Table)
Data Out
Dout = Vin / Step Size
for input vtg. of 2.56 volts (Vref=1.28 volts) and stepsize of 10mv Dout =2560/10 =256 or
FF that is full scale output.
Conversion Time
Greater than 110us for ADC804
Resolution
8 bits for ADC804
Algorithm
• Make CS=0 and send a low-to-high to pin WR to start the conversion.
• Keep monitoring INTR
– If INTR =0, the conversion is finished and we can go to the next step.
– If INTR=1, keep polling until it goes low.
• After INTR=0, we make CS=0 and send a high-to-low pulse to RD to get the data out of the
ADC804 chip.
ADC_IO:
mov P1, #0xff ; To configure as input
AGAIN
clr p3.7 ;Chip select
setb P3.6 ;RD=1
clr P3.5 ;WR=0
setb P3.5 ;WR=1- low to high transition
WAIT:
jb P3.4, WAIT ;wait for INTR
clr p3.7 ;generate cs to ADC
clr P3.6 ;RD=0 -High to low transition
mov A, P1 ;read digital o/p
sjmp AGAIN
Channel CBA
IN0 000
IN1 001
IN2 010
IN3 011
IN4 100
IN5 101
IN6 110
IN7 111
Algorithm
Notice that the ADC808/809 that there is no self-clocking and the clock must be provided from
an external source to the CLK pin. (you can use programmable clock oscillator to enable or
disable clock by programmable bit. )
PinOut
– D0-D7 à Connected to the Processor’s IO port
– Vref+, Vref-, Vee
Usage:
– Just write a byte to the IO port and the DAC converts it to an
analog value
Some 8051 clones have ADCs and DACs in built