NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76132S3ST. S
Packaging
JEDEC TO-220AB JEDEC TO-263AB
SOURCE
DRAIN
GATE DRAIN
DRAIN (FLANGE)
GATE
(FLANGE)
SOURCE
6-130 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HUF76132P3, HUF76132S3S
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V
Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figure 9, 10) - 0.0085 0.011 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient RθJA TO-220, TO-262 and TO-263 - - 62 oC/W
Fall Time tf - 42 - ns
6-131
HUF76132P3, HUF76132S3S
Fall Time tf - 42 - ns
Threshold Gate Charge Qg(TH) VGS = 0V to 1V (Figures 14, 19, 20) - 1.8 2.2 nC
CAPACITANCE SPECIFICATIONS
1.2 80
POWER DISSIPATION MULTIPLIER
60
0.8
0.6
40
VGS = 4.5V
0.4
20
0.2
0
0 25 50 75 100 125 150 0
25 50 75 100 125 150
TA , AMBIENT TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
6-132
HUF76132P3, HUF76132S3S
2
DUTY CYCLE - DESCENDING ORDER
0.5
1 0.2
0.1
THERMAL IMPEDANCE
0.05
ZθJC, NORMALIZED
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)
2000
TC = 25oC
FOR TEMPERATURES
1000
ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)
CURRENT AS FOLLOWS:
VGS = 5V
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)
1000 500
TJ = MAX RATED If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
TC = 25oC
If R ≠ 0
IAS, AVALANCHE CURRENT (A)
100 100µs
100
STARTING TJ = 25oC
1ms
10
10ms
STARTING TJ = 150oC
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON) BVDSS MAX = 30V
1 10
1 10 100 0.01 0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
6-133
HUF76132P3, HUF76132S3S
120 120
PULSE DURATION = 80µs VGS = 10V VGS = 5V
DUTY CYCLE = 0.5% MAX -40oC
100 150oC 100 VGS = 4.5V VGS = 4V
80 80
25oC
VGS = 3.5V
60 60
40 40
VGS = 3V
1.4
ON RESISTANCE (mΩ)
ID = 51A
ON RESISTANCE
14
1.2
ID = 25A
12
1.0
10
0.8
8
6 0.6
2 4 6 8 10 -60 0 60 120 180
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE
1.2 1.2
VGS = VDS, ID = 250µA ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE
1.0 1.1
0.8 1.0
0.6 0.9
-60 0 60 120 180 -60 0 60 120 180
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
JUNCTION TEMPERATURE VOLTAGE vs JUNCTION TEMPERATURE
6-134
HUF76132P3, HUF76132S3S
2500 10
VGS = 0V, f = 1MHz VDD = 15V
CISS
1500 6
COSS
1000 4
WAVEFORMS IN
DESCENDING ORDER:
500 2 ID = 75A
CRSS ID = 51A
ID = 25A
0 0
0 5 10 15 20 25 30 0 10 20 30 40 50
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
400 400
VGS = 4.5V, VDD = 15V, ID = 41A, RL= 0.312Ω VGS = 10V, VDD = 15V, ID = 75A, RL= 0.20Ω
300 300
SWITCHING TIME (ns)
tr
td(OFF)
200 200
tf
tf
100 100 tr
td(OFF)
td(ON)
td(ON)
0 0
0 10 20 30 40 50 0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω) RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
VDS
BVDSS
L tP
VDS
tP
0V IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
6-135
HUF76132P3, HUF76132S3S
VDS
RL VDD Qg(TOT)
VDS
VGS = 10
VGS Qg(5)
+
VDD
VGS VGS = 5V
-
DUT VGS = 1V
Ig(REF) 0
Qg(TH)
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
+
VGS
VDD 10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
6-136
HUF76132P3, HUF76132S3S
LDRAIN
DBODY 7 5 DBODYMOD DPLCAP 5 DRAIN
DBREAK 5 11 DBREAKMOD 2
10
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSLC1
51 DBREAK
+
EBREAK 11 7 17 18 33.34 RSLC2
EDS 14 8 5 8 1 5
ESLC 11
EGS 13 8 6 8 1 51
-
ESG 6 10 6 8 1 50 +
EVTHRES 6 21 19 8 1 -
RDRAIN 17 DBODY
EVTEMP 20 6 18 22 1 6
ESG EBREAK 18
8
+ EVTHRES 16
-
+ 19 - 21
IT 8 17 1 MWEAK
LGATE EVTEMP 8
GATE RGATE +
LDRAIN 2 5 1e-9 18 - 6
1 22 MMED
LGATE 1 9 5.42e-9 9 20
LSOURCE 3 7 4.16e-9 RLGATE MSTRO
LSOURCE
MMED 16 6 8 8 MMEDMOD CIN SOURCE
8 7
MSTRO 16 6 8 8 MSTROMOD 3
MWEAK 16 21 8 8 MWEAKMOD RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1 S1A S2A
RDRAIN 50 16 RDRAINMOD 3.5e-4 12 RBREAK
13 14 15
RGATE 9 20 2.61 17 18
8 13
RLDRAIN 2 5 10
RLGATE 1 9 54.2 S1B S2B RVTEMP
RLSOURCE 3 7 41.6 13 CB 19
RSLC1 5 51 RSLCMOD 1e-6 CA
+ + 14 IT -
RSLC2 5 50 1e3
6 5 VBAT
RSOURCE 8 7 RSOURCEMOD 6.5-3 EGS EDS
8 8 +
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1 - - 8
22
S1A 6 12 13 8 S1AMOD RVTHRES
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*450),3))}
.MODEL DBODYMOD D (IS = 1.79e-12 IKF = 20 RS = 5.32e-3 TRS1 = 7e-4 TRS2 = 1.21e-6 CJO = 2.65e-9 TT = 3.24e-8 M = 4.2e-1 XTI=6)
.MODEL DBREAKMOD D (RS = 8.25e-2 TRS1 = 9.12e-4 TRS2 = 8.14e-7)
.MODEL DPLCAPMOD D (CJO = 1.3e-9 IS = 1e-30 N = 10 M = 6.1e-1)
.MODEL MMEDMOD NMOS (VTO = 1.86 KP = 4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.61)
.MODEL MSTROMOD NMOS (VTO = 2.2 KP = 120 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.63 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.1 RS=1e-1)
.MODEL RBREAKMOD RES (TC1 = 9.97e-4 TC2 = 1.24e-7)
.MODEL RDRAINMOD RES (TC1 = 7.2e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1.07e-3 TC2 = 1.25e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-11 TC2 = 1e-11)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -9.2e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.08e-3 TC2 = 9.73e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.00 VOFF= -1.00)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.00 VOFF= -6.00)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 1.65)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.65 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
6-137
HUF76132P3, HUF76132S3S
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/450))** 3))
}
}
6-138
HUF76132P3, HUF76132S3S
HUF76132
RTHERM2 CTHERM2
RTHERM1 th 6 1.51e-2
RTHERM2 6 5 1.51e-2
RTHERM3 5 4 3.03e-2
RTHERM4 4 3 6.05e-2 5
RTHERM5 3 2 1.81e-1
RTHERM6 2 tl 2.45e-1
RTHERM3 CTHERM3
tl CASE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
6-139