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TLE2142-Q1

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Excalibur™ LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIER


1FEATURES
D PACKAGE
• Qualified for Automotive Applications
2
(TOP VIEW)
• Low Noise
1OUT 1 8 VCC+
– 10 Hz: 15 nV/√Hz
1IN- 2 7 2OUT
– 1 kHz: 10.5 nV/√Hz 1IN+ 3 6 2IN-
• 10000-pF Load Capability VCC- 4 5 2IN+
• 20-mA Short-Circuit Output Current (Min)
• 27-V/µs Slew Rate (Min)
• High Gain-Bandwidth Product: 5.9 MHz
• Single or Split Supply: 4 V to 44 V
• Fast Settling Time
– 340 ns to 0.1%
– 400 ns to 0.01%
• Large Output Swing:
VCC– + 0.1 V to VCC+ – 1 V

DESCRIPTION/ORDERING INFORMATION
The TLE2142 device is a high-performance, internally compensated operational amplifier built using the Texas
Instruments complementary bipolar Excalibur™ process. It is a pin-compatible upgrade to standard industry
products.
The design incorporates an input stage that simultaneously achieves low audio-band noise of 10.5 nV/√Hz with a
10-Hz 1/f corner and symmetrical 40-V/µs slew rate typically with loads up to 800 pF. The resulting low distortion
and high power bandwidth are important in high-fidelity audio applications. A fast settling time of 340 ns to 0.1%
of a 10-V step with a 2-kΩ/100-pF load is useful in fast actuator/positioning drivers. Under similar test conditions,
settling time to 0.01% is 400 ns.
The device is stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHz at
this high loading level. As such, the TLE2142 is useful for low-droop sample-and-holds and direct buffering of
long cables, including 4-mA to 20-mA current loops.
The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches as
is evidenced by a 500-µV maximum offset voltage and 1.7-µV/°C typical drift. Minimum common-mode rejection
ratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.
Device performance is relatively independent of supply voltage over the ±2-V to ±22-V range. Inputs can operate
between VCC– – 0.3 V to VCC+ – 1.8 V without inducing phase reversal, although excessive input current may flow
out of each input exceeding the lower common-mode input range. The all-npn output stage provides a nearly
rail-to-rail output swing of VCC– + 0.1 V to VCC+ – 1 V under light current-loading conditions. The device can
sustain shorts to either supply, because output current is internally limited, but care must be taken to ensure that
maximum package power dissipation is not exceeded.
The TLE2142 can also be used as a comparator. Differential inputs of VCC± can be maintained without damage
to the device. Open-loop propagation delay with TTL supply levels is typically 200 ns. This gives a good
indication as to output stage saturation recovery when the device is driven beyond the limits of recommended
output swing.
The TLE2142 device is available in industry-standard 8-pin small-outline (D) packages. The device is
characterized for operation from –40°C to 125°C.
1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Excalibur is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLE2142-Q1
SLOS628 – JULY 2009....................................................................................................................................................................................................... www.ti.com

SYMBOL (EACH AMPLIFIER)

IN+ +
OUT
IN- -

ORDERING INFORMATION (1)


TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 125°C SOIC – D Reel of 2500 TLE2142QDRQ1 2142Q

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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TLE2142-Q1
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EQUIVALENT SCHEMATIC

OUT
R24

Q37

Q36
R21

R22
R23
Q34

Q35
R19

R20
Q32
Q30

Q31

Q33
D8
R18

Q29
Q28
R17
Q26

Q27

D7
D6
Q25
R16
R15

D5
Q23

Q24
Q22

R13
D4
R14

C3

TLE2142
C4

Q21
D3

DEVICE COMPONENT COUNT

65

43

14

1
8
Q20

R12
Q19
VCC +

VCC -
Q18

COMPONENT
R11

Transistors

Capacitors
C2

Resistors

Epi-FET
Diodes
Q17
R9

R10
Q16
Q15
R7

R8
Q13

Q14
D2

Q11

Q12
Q10

R6

Q9
R4

C1
Q5 Q8

R5
Q7
Q6
R3

Q2
Q4
D1
Q3
R1

R2

Q1
IN +
IN -

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ABSOLUTE MAXIMUM RATINGS (1)


over operating free-air temperature range (unless otherwise noted)
VCC+ Supply voltage (2) 22 V
VCC– Supply voltage –22 V
VID Differential input voltage (3) ±44 V
VI Input voltage range (any input) VCC+ to (VCC– – 0.3) V
II Input current (each input) ±1 mA
IO Output current ±80 mA
Total current into VCC+ 80 mA
Total current out of VCC– 80 mA
Duration of short-circuit current at (or below) 25°C (4) Unlimited
θJA Package thermal impedance (5) (6) 97.1°C/W
TA Operating free-air temperature range –40°C to 125°C
Tstg Storage temperature range –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
ESD Electrostatic discharge rating, Human-body model 500 V

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
(3) Differential voltages are at IN+ with respect to IN–. Excessive current flows, if input, are brought below VCC– – 0.3 V.
(4) The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
(5) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS


MIN MAX UNIT
VCC± Supply voltage ±2 ±22 V
VCC = 5 V 0 2.7
VIC Common-mode input voltage V
VCC± = ±15 V –15 12.7
TA Operating free-air temperature –40 125 °C

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ELECTRICAL CHARACTERISTICS
VCC = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TA (1) MIN TYP MAX UNIT
25°C 220 1900
VIO Input offset voltage VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V µV
Full range 2600
Temperature coefficient of
αVIO VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V Full range 1.7 µV/°C
input offset voltage
25°C 8 100
IIO Input offset current VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V nA
Full range 200
25°C –0.8 –2
IIB Input bias current VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V µA
Full range –2.3
–0.3 to
25°C 0 to 3
Common-mode input 3.2
VICR RS = 50 Ω V
voltage range –0.3 to
Full range 0 to 2.7
2.9
IOH = –150 µA 3.9 4.1
IOH = –1.5 mA 25°C 3.8 4
IOH = –15 mA 3.4 3.7
VOH High-level output voltage V
IOH = –100 µA 3.75
IOH = –1 mA Full range 3.65
IOH = –10 mA 3.45
IOL = 150 µA 75 125
mV
IOL = 1.5 mA 25°C 150 225
IOL = 15 mA 1.2 1.4 V
VOL Low-level output voltage
IOL = 100 µA 200
mV
IOL = 1 mA Full range 250
IOL = 10 mA 1.25 V
Large-signal differential VIC = ±2.5 V, RL = 2 kΩ, 25°C 50 220
AVD V/mV
voltage amplification VO = 1 V to -1.5 V Full range 5
ri Input resistance 25°C 70 MΩ
ci Input capacitance 25°C 2.5 pF
zo Open-loop output impedance f = 1 MHz 25°C 30 Ω
25°C 85 118
CMRR Common-mode rejection ratio VIC = VICR(min), RS = 50 Ω dB
Full range 80
Supply-voltage rejection ratio 25°C 90 106
kSVR VCC± = ±2.5 V to ±15 V, RS = 50 Ω dB
(ΔVCC±/ΔVIO) Full range 85
25°C 6.6 8.8
ICC Supply current VO = 2.5 V, No load, VIC = 2.5 V mA
Full range 9.2

(1) Full range is –40°C to 125°C.

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OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR+ Positive slew rate AVD = –1, RL = 2 kΩ (1), CL = 500 pF 45 V/µs
SR– Negative slew rate AVD = –1, RL = 2 kΩ (1), CL = 500 pF 42 V/µs
To 0.1% 0.16
ts Settling time AVD = –1, 2.5-V step µs
To 0.01% 0.22
f = 10 Hz 15
Vn Equivalent input noise voltage RS = 20 Ω nV/√Hz
f = 1 kHz 10.5
Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 0.48
Vn(PP) µV
noise voltage f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.92
In Equivalent input noise current pA/√Hz
f = 1 kHz 0.5
VO = 1 V to 3 V, RL = 2 kΩ (1), AVD = 2,
THD+N Total harmonic distortion plus noise 0.0052 %
f = 10 kHz
B1 Unity-gain bandwidth RL = 2 kΩ (1), CL = 100 pF 5.9 MHz
Gain-bandwidth product RL = 2 kΩ (1), CL = 100 pF, f = 100 kHz 5.8 MHz
BOM Maximum output-swing bandwidth VO(PP) = 2 V, RL = 2 kΩ (1), AVD = 1, CL = 100 pF 660 kHz
φm Phase margin at unity gain (1)
RL = 2 kΩ , CL = 100 pF 57 °

(1) RL terminated at 2.5 V.

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ELECTRICAL CHARACTERISTICS
VCC = ±15 V, at specified free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TA (1) MIN TYP MAX UNIT
25°C 290 1200
VIO Input offset voltage VIC = 0, RS = 50 Ω µV
Full range 2000
Temperature coefficient of
αVIO VIC = 0, RS = 50 Ω Full range 1.7 µV/°C
input offset voltage
25°C 7 100
IIO Input offset current VIC = 0, RS = 50 Ω nA
Full range 250
25°C –0.7 –1.5
IIB Input bias current VIC = 0, RS = 50 Ω µA
Full range –1.8
–15 to –15.3 to
25°C
Common-mode input 13 13.2
VICR RS = 50 Ω V
voltage range –15 to –15.3 to
Full range
12.7 12.9
IO = –150 µA 13.8 14.1
IO = –1.5 mA 25°C 13.7 14
Maximum positive peak IO = –15 mA 13.3 13.7
VOM+ V
output voltage swing IO = –100 µA 13.7
IO = –1 mA Full range 13.6
IO = –10 mA 13.3
IO = 150 µA –14.7 –14.9
IO = 1.5 mA 25°C –14.5 –14.8
Maximum negative peak IO = 15 mA –13.4 –13.8
VOM– V
output voltage swing IO = 100 µA –14.6
IO = 1 mA Full range –14.5
IO = 10 mA –13.4
Large-signal differential 25°C 100 450
AVD VO = ±10 V, RL = 2 kΩ V/mV
voltage amplification Full range 20
ri Input resistance 25°C 65 MΩ
ci Input capacitance 25°C 2.5 pF
zo Open-loop output impedance f = 1 MHz 25°C 30 Ω
25°C 85 108
CMRR Common-mode rejection ratio VIC = VICR(min), RS = 50 Ω dB
Full range 80
Supply-voltage rejection ratio 25°C 90 106
kSVR VCC± = ±2.5 V to ±15 V, RS = 50 Ω dB
(ΔVCC±/ΔVIO) Full range 85
VID = 1 V –25 –50
IOS Short-circuit output current VO = 0 25°C mA
VID = –1 V 20 31
25°C 6.9 9
ICC Supply current VO = 0, No load, VIC = 2.5 V mA
Full range 9.4

(1) Full range is –40°C to 125°C.

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OPERATING CHARACTERISTICS
VCC = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR+ Positive slew rate AVD = –1, RL = 2 kΩ, CL = 100 pF 27 45 V/µs
SR– Negative slew rate AVD = –1, RL = 2 kΩ, CL = 100 pF 27 42 V/µs
To 0.1% 0.34
ts Settling time AVD = –1, 10-V step µs
To 0.01% 0.4
f = 10 Hz 15
Vn Equivalent input noise voltage RS = 20 Ω nV/√Hz
f = 1 kHz 10.5
Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 0.48
Vn(PP) µV
noise voltage f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.89
In Equivalent input noise current pA/√Hz
f = 1 kHz 0.47
THD+N Total harmonic distortion plus noise VO(PP) = 20 V, RL = 2 kΩ, AVD = 10, f = 10 kHz 0.01 %
B1 Unity-gain bandwidth RL = 2 kΩ, CL = 100 pF 6 MHz
Gain-bandwidth product RL = 2 kΩ, CL = 100 pF, f = 100 kHz 5.9 MHz
BOM Maximum output-swing bandwidth VO(PP) = 20 V, AVD = 1, RL = 2 kΩ, CL = 100 pF 668 kHz
φm Phase margin at unity gain RL = 2 kΩ, CL = 100 pF 58 °

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TYPICAL CHARACTERISTICS

Table of Graphs
VIO Input offset voltage Distribution Figure 1
IIO Input offset current vs Free-air temperature Figure 2
vs Common-mode input voltage Figure 3
IIB Input bias current
vs Free-air temperature Figure 4
vs Supply voltage Figure 5
vs Free-air temperature Figure 6
VOM+ Maximum positive peak output voltage
vs Output current Figure 7
vs Settling time Figure 9
vs Supply voltage Figure 5
vs Free-air temperature Figure 6
VOM– Maximum negative peak output voltage
vs Output current Figure 8
vs Settling time Figure 9
VO(PP) Maximum peak-to-peak output voltage vs Frequency Figure 10
VOH High-level output voltage vs Output current Figure 11
VOL Low-level output voltage vs Output current Figure 12
Phase shift vs Frequency Figure 13
vs Frequency Figure 13
AVD Large-signal differential voltage amplification
vs Free-air temperature Figure 14
zo Closed-loop output impedance vs Frequency Figure 15
IOS Short-circuit output current vs Free-air temperature Figure 16
vs Frequency Figure 17
CMRR Common-mode rejection ratio
vs Free-air temperature Figure 18
vs Frequency Figure 19
kSVR Supply-voltage rejection ratio
vs Free-air temperature Figure 20
vs Supply voltage Figure 21
ICC Supply current
vs Free-air temperature Figure 22
Vn Equivalent input noise voltage vs Frequency Figure 23
Vn Input noise voltage Over a 10-second period Figure 24
In Noise current vs Frequency Figure 25
THD+N Total harmonic distortion plus noise vs Frequency Figure 26
vs Free-air temperature Figure 27
SR Slew rate
vs Load capacitance Figure 28
Noninverting large signal vs Time Figure 29
Pulse response Inverting large signal vs Time Figure 30
Small signal vs Time Figure 31
B1 Unity-gain bandwidth vs Load capacitance Figure 32
Gain margin vs Load capacitance Figure 33
φm Phase margin vs Load capacitance Figure 34

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TLE2142 INPUT OFFSET CURRENT


DISTRIBUTION OF vs
INPUT OFFSET VOLTAGE FREE-AIR TEMPERATURE
24 20
236 Units Tested From 1 Wafer Lot VO = 0
VCC ± = ± 15 V 18 VIC = 0
20 TA = 25°C
P Package 16

IO − Input Offset Current − nA


Percentage of Units − %

14
16
12

12 10
VCC ± = ± 2.5 V
8
8
6
VCC ± = ± 15 V

IIIO
4
4
2

0 0
−800 −600 −400 −200 0 200 400 600 800 −75 −50 −25 0 25 50 75 100 125 150
VIO − Input Offset Voltage − µV TA − Free-Air Temperature − °C
Figure 1. Figure 2.
INPUT BIAS CURRENT INPUT BIAS CURRENT
vs vs
COMMON-MODE INPUT VOLTAGE FREE-AIR TEMPERATURE
0 −1000
VCC ± = ± 2.5 V VO = 0
VIC = 0
−0.2
−900
IB − Input Bias Current − nA
uA
IB − Input Bias Current − µA

−0.4
VCC ± = ± 2.5 V
−800
−0.6
TA = 125°C

−0.8 TA = 25°C −700


VCC ± = ± 15 V
−1
IIIB
IIIB

TA = − 55°C −600
−1.2

−1.4 −500
−3 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 −75 −50 −25 0 25 50 75 100 125 150
VIC − Common-Mode Input Voltage − V TA − Free-Air Temperature − °C
Figure 3. Figure 4.

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MAXIMUM PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE


vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
24 15
RL = 2 kΩ
VCC ± = ± 15 V
TA = 25°C
18
V OM − Maximum Peak Output Voltage − V

V OM − Maximum Peak Output Voltage − V


14.6
RL = ∞
12
14.2
VOM + VOM +
6
13.8 RL = 2 kΩ
0
−13.8
−6
VOM −
−14.2 RL = 2 kΩ
−12

−14.6 VOM −
−18
RL = ∞

− 24 −15
0 3 6 9 12 15 18 21 24 −75 −50 −25 0 25 50 75 100 125 150
VCC ± − Supply Voltage − V TA − Free-Air Temperature − °C
Figure 5. Figure 6.
MAXIMUM POSITIVE PEAK MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
V OM + − Maximum Positive Peak Output Voltage − V

14.6
V OM − − Maximum Negative Peak Output Voltage − V

−13.4
VCC ± = ± 15 V VCC ± = ± 15 V
−13.6
14.4
−13.8
TA = 125°C
−14
14.2
TA = 125°C
−14.2
TA = − 55°C
14
−14.4 TA = 25°C

TA = − 55°C TA = 25°C −14.6


13.8
−14.8

13.6 − 15
−0.1 −0.4 −1 −4 −10 − 40 −100 0.1 0.4 1 4 10 40 100
IO − Output Current − mA IO − Output Current − mA
Figure 7. Figure 8.

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MAXIMUM PEAK OUTPUT VOLTAGE MAXIMUM PEAK-TO-PEAK


vs OUTPUT VOLTAGE
SETTLING TIME vs
12.5 FREQUENCY
AVD = −1

V O(PP) − Maximum Peak-to-Peak Output Voltage − V


30
10 VCC ± = ± 15 V VCC ± = ± 15 V
OM − Maximum Peak Output Voltage − V

TA = 25°C RL = 2 kΩ
7.5 0.1%
25
0.01%
5
TA = 25°C
2.5 20
Rising
0 TA = 125°C
Falling 15
−2.5
0.01%
−5
10
0.1% TA = − 55°C
−7.5
VVOM

−10 5

−12.5
0 100 200 300 400 500 0
ts − Settling Time − ns 100 k 400 k 1M 4M 10 M
f − Frequency − Hz
Figure 9. Figure 10.
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
4.6 1400
VCC = 5 V VCC = 5 V
OL − Low-Level Output Voltage − mV

1200
V OH − High-Level Output Voltage − V

4.4
TA = 125°C TA = 125°C
1000
4.2 TA = 25°C

800
4 TA = − 55°C
600
TA = 25°C
3.8
400
VOL

3.6
200
V

TA = − 55°C
3.4 0
−0.1 −1 −10 −100 0.1 1 10 100
IO − Output Current − mA IO − Output Current − mA
Figure 11. Figure 12.

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LARGE-SIGNAL DIFFERENTIAL VOLTAGE LARGE-SIGNAL DIFFERENTIAL


AMPLIFICATION AND PHASE SHIFT VOLTAGE AMPLIFICATION
vs vs
FREQUENCY FREE-AIR TEMPERATURE
120 0° 140
110 20° VCC ± = ± 15 V
VO = ± 10 V
100 40°
VD − Large-Signal Differential

90 60° RL = 10 kΩ
Voltage Amplification − dB

VD − Large-Signal Differential
80 Phase Shift 80°

Voltage Amplification − dB
70 100° 120

Phase Shift
60 120°
AVD
50 140°
40 160° RL = 2 kΩ
30 180°
100
AAVD

20 VCC ± = ± 15 V 200°
RL = 2 kΩ

AAVD
10 220°
CL = 100 pF
0 TA = 25°C 240°
− 10 260°
1 10 100 1k 10 k 100 k 1M 10 M
80
f − Frequency − Hz
−75 −50 −25 0 25 50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 13. Figure 14.
CLOSED-LOOP OUTPUT IMPEDANCE SHORT-CIRCUIT OUTPUT CURRENT
vs vs
FREQUENCY FREE-AIR TEMPERATURE
100 60
30 Ω VCC ± = ± 15 V
VO = 0
z o − Closed-Loop Output Impedance − Ω

IOS − Short-Circuit Output Current − mA

10
50 VID = 1

40
AVD = 100
0.1
AVD = 10
AVD = 1
30
0.01
VID = − 1

0.001 20
1k 10 k 100 k 1M 10 M −75 −50 −25 0 25 50 75 100 125 150
f − Frequency − Hz TA − Free-Air Temperature − °C
Figure 15. Figure 16.

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COMMON-MODE REJECTION RATIO COMMON-MODE REJECTION RATIO


vs vs
FREQUENCY FREE-AIR TEMPERATURE
140 120
VCC ± = ± 15 V VIC = VICRmin
CMRR − Common-Mode Rejection Ratio − dB

CMRR − Common-Mode Rejection Ratio − dB


TA = 25°C VCC = 5 V
120
116
100

112
80

60
108

40 VCC ± = ± 15 V

104
20

0 100
100 1k 10 k 100 k 1M −75 −50 −25 0 25 50 75 100 125 150
f − Frequency − Hz TA − Free-Air Temperature − °C
Figure 17. Figure 18.
SUPPLY-VOLTAGE REJECTION RATIO SUPPLY-VOLTAGE REJECTION RATIO
vs vs
FREQUENCY FREE-AIR TEMPERATURE
160 110
VCC ± = ± 2.5 V to ± 15 V
SVR − Supply-Voltage Rejection Ratio − dB
SVR − Supply-Voltage Rejection Ratio − dB

140
kSVR + 108
120
kSVR −
100
106

80

60 104

40
102
kkSVR
kkSVR

20 VCC ± = ± 2.5 V to ± 15 V
TA = 25°C
0 100
10 100 1k 10 k 100 k 1M 10 M −75 −50 −25 0 25 50 75 100 125 150
f − Frequency − Hz TA − Free-Air Temperature − °C
Figure 19. Figure 20.

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SUPPLY CURRENT SUPPLY CURRENT


vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
4 3.8
VO = 0
TA = 125°C No Load
3.6
3.5 VCC ± = ± 15 V

CC − Supply Current − mA
CC − Supply Current − mA

TA = 25°C
3.4
VCC ± = ± 2.5 V
3

TA = − 55°C 3.2

IIDD
IIDD

2.5
3
VO = 0
No Load
2 2.8
0 4 8 12 16 20 24 −75 −50 −25 0 25 50 75 100 125 150
|VCC ±| − Supply Voltage − V TA − Free-Air Temperature − °C
Figure 21. Figure 22.
EQUIVALENT INPUT NOISE VOLTAGE INPUT NOISE VOLTAGE
vs OVER A 10-SECOND PERIOD
FREQUENCY
750
250
VCC ± = ± 15 V
VCC ± = ± 15 V
Vn − Equivalent Input Noise Voltage − nV/ Hz

f = 0.1 to 10 Hz
RS = 20 Ω
500 TA = 25°C
200
Input Noise Voltage − nV

TA = − 55°C
250

150
0
TA = 125°C
100
−250

TA = 25°C
50 −500

−750
0 0 2 4 6 8 10
1 10 100 1k 10 k
t − Time − s
f − Frequency − Hz
Figure 23. Figure 24.

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Product Folder Link(s): TLE2142-Q1
TLE2142-Q1
SLOS628 – JULY 2009....................................................................................................................................................................................................... www.ti.com

NOISE CURRENT TOTAL HARMONIC DISTORTION


vs PLUS NOISE
FREQUENCY vs
8 FREQUENCY
1%

THD + N − Total Harmonic Distortion + Noise − %


VO(PP) = 20 V
VCC ± = ± 15 V AV = 100
TA = 25°C RL = 600 Ω
In − Noise Current − pA/ Hz

0.1%
TA = − 55°C AV = 100
4 AV = 10 RL = 2 kΩ
RL = 600 Ω

TA = 25°C
0.01%
2
AV = 10
TA = 125°C RL = 2 kΩ

0
1 10 100 1k 10 k 0.001%
f − Frequency − Hz 10 100 1k 10 k 100 k
f − Frequency − Hz
Figure 25. Figure 26.
SLEW RATE SLEW RATE
vs vs
FREE-AIR TEMPERATURE LOAD CAPACITANCE
60 50

50
SR + 40
SR − Slew Rate − V/ µ s
SR − Slew Rate − V/ µ s

40 SR+
30
SR −
30

20
20
SR −
VCC ± = ± 15 V 10 VCC ± = ± 15 V
10 AVD = − 1 AVD = − 1
RL = 2 kΩ TA = 25°C
CL = 500 pF
0 0
−75 −50 −25 0 25 50 75 100 125 150 0.01 0.1 1 10
TA − Free-Air Temperature − °C CL − Load Capacitance − nF
Figure 27. Figure 28.

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TLE2142-Q1
www.ti.com....................................................................................................................................................................................................... SLOS628 – JULY 2009

NONINVERTING INVERTING
LARGE-SIGNAL LARGE-SIGNAL
PULSE RESPONSE PULSE RESPONSE
15 15
TA = 125°C TA = 25°C
10 10

TA = 25°C TA = − 55°C
O − Output Voltage − V

O − Output Voltage − V
5 5 TA = 125°C TA = − 55°C
TA = − 55°C

0 0

TA = − 55°C TA = 125°C
−5 −5 TA = 25°C
VO

VO
TA = 25°C

V
V

VCC ± = ± 15 V VCC ± = ± 15 V
−10 AVD = 1 −10 AVD = −1
RL = 2 kΩ RL = 2 kΩ
CL = 300 pF TA = 125°C CL = 300 pF
−15 −15
0 1 2 3 4 5 0 1 2 3 4 5
t − Time − µs t − Time − µs
Figure 29. Figure 30.
SMALL-SIGNAL UNITY-GAIN BANDWIDTH
PULSE RESPONSE vs
100 LOAD CAPACITANCE
7
TA = − 55°C VCC ± = ± 15 V
RL = 2 kΩ
6
1 − Unity-Gain Bandwidth − MHz
O − Output Voltage − mV

50
TA = 25°C

5
TA = 125°C
0
4
VO

VCC ± = ± 15 V 3
V

−50 AVD = −1
RL = 2 kΩ
B1
B

CL = 300 pF 2
TA = 25°C
−100
0 400 800 1200 1600 1
10 100 1000 10000
t − Time − ns
CL − Load Capacitance − pF
Figure 31. Figure 32.

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SLOS628 – JULY 2009....................................................................................................................................................................................................... www.ti.com

GAIN MARGIN PHASE MARGIN


vs vs
LOAD CAPACITANCE LOAD CAPACITANCE
14 70°
VCC ± = ± 15 V TA = − 55°C
AVD = 1
12 RL = 2 kΩ to ∞ 60°
TA = 25°C
VO = − 10 V to 10 V
10 TA = − 55°C 50°

φ m − Phase Margin
Gain Margin − dB

TA = 125°C
8 40°

6 30°
TA = 125°C
4 20°

2 10°
VCC ± = ± 15 V
TA = 25°C
RL = 2 kΩ
0 0°
10 100 1000 10000 10 100 1000 10000
CL − Load Capacitance − pF CL − Load Capacitance − pF
Figure 33. Figure 34.

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PACKAGE OPTION ADDENDUM

www.ti.com 19-May-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TLE2142QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 2142Q
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 19-May-2014

OTHER QUALIFIED VERSIONS OF TLE2142-Q1 :

• Catalog: TLE2142
• Military: TLE2142M

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product


• Military - QML certified for Military and Defense Applications

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Dec-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLE2142QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Dec-2010

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLE2142QDRQ1 SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
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