79 3 - 4 Fault simulation essentials

.x G
x
2
-- T ?T r 3
>1 c5 Cl
r >
G, -
t c6
rclalH > ns
equivalence and dominance
An example illustrating incuinplctcness ol ihe
'
Figure 3.23

3.4.1.2 A fault collapsing procedure

of
inputs and outputs
I he equivalence and dominance relations betweeni SAFs at
that can typically
primitive gates may be used to formulate a simple procedure
. each possible single
eliminate many faults from the complete lault list that contain
list , it is often
SAF in a circuit. Since such a procedure decreases t e size ol a fault

cT“ rL ««
arc incomplete in the sense that it is possible lor two laulls / , anc j .
'

at an input or the output of a particular gate in a particulai ciic.uit , to be ecl

dominant even though no such relation between these laulls has been idenlihe^
For example, no universally true relation can be derived between any two single SA s
associated with the inputs and the output ol an XOR gate . Yet , the readet can vetily
that in the circuit shown in Figure 3.23, an SAI lault at input Q, ol the XOR gate GT ,
dominates Ihe SAO fault at the output c of the gale .
In addition , SAFs that arc not associated with the inputs and output of a single gate
can also be equivalent . The relations mentioned so far do not address such scenarios
and the following procedure is not guaranteed to find all such relations.
In general , the complexity of identifying all fault equivalence and dominance
relations is high . Hence, in practice, the equivalence and dominance relations identified
between single SAFs associated with inputs and outputs of gales are used in an iterative
fashion to achieve significant fault collapsing.

Procedure 3.6 [ FauItCollapsing( )]

I Starting at each primary output P O , compute the value of output level rjuul ( ) ,
c for
each line cy .
,
The output level of a line c
. . . , , ‘-
a oinhinalional circuit is the
ol circuit elements Ural are traversed along any path from the line
maximum number
lo any primary
output . The values tjtnufc / ) can be computed lor each line c
OutputLevelize( ) which can be obtained by modifying ' by using Procedure
Procedure lnputLevelize ( ).

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80 Combinational logic and fault simulation

decreasing values of qum in an

ordered list
2 Son the circuit lines in ihe order of non -
01101,1 - fault set F ( n ) containing all
single SAFs that
3 For each circuit line c . create a local
*

' SAO. < 7 S A 11 .

=
may he located at the line , i .c F i n ) U i , remove
Q is the output of a gate C
that is
4 While there exists at least one line in 7 / > l l l i

the first line c j from the ordered list Q ^o i i i *

( a ) Let c / j , c/ p n be the inputs of gate G with output C the j.

set of single SAFs
( b ) Let F$ak.
.
F( cy ) U A' ( cv , ) U F ( C j 2 ) U • • U F ( cio ) be
=
located at the inputs and the output of gate G .
( c ) Use Table 3.4 to identify the relations between the
faults in the set /'gate - This
will result in the identification of equivalence and dominance
relations between
pairs of faults.
( d ) Create equivalent fault sets E \ , Ei Ey .
Due to the symmetric and transitive nature of the fault equivalence relation , the
faults in Fgale< can be partitioned into equivalent fault sets, each containing one
or more faults such that each pair of faults in an equivalent fault set is equivalent ,
and all faults that are equivalent to a fault J also belong to the equivalent fault
scl to which / belongs .
Note that the equivalent fault sets form a partition of Fgalc , > - e - > Egale = E i U
£? U • • U Ey , and no fault belongs to more than one equivalent fault set .
.
( e ) If any fault J ) in Fcatl dominates any other fault fi in Faalc , then delete f \ from
the local fault set to which it belongs.
( f ) For each equivalent fault set E / that contains more than one fault , retain one
fault and delete the others from the local fault set to which they belong.
If any one of the faults in E\ is located at a line that is one of the inputs of gate G
and is also the output of another primitive gate, then that fault may be retained .
Otherwise, the fault on an arbitrarily selected input of the gate may be retained .
5 The collapsed fault list is obtained by taking the union of the local fault sets at each
circuit line .

Example 3.5 Consider the circuit shown in Figure 3.24. First , ijoul ( c, ) is computed
for each circuit line , c, . The values obtained arc shown in Figure 3.24( a) . In the
increasing order of output level , the lines are added to an ordered list to obtain
, -
Qr m — ( Z2 z|. CIO , C9 , C'g , t'3 , C7 , Cfi . C|, X \ , C5 , A 2 , C4 , Cs , 4 , XT, ) .
'
*
The local fault sets are then created for each line , where the local fault set is
comprised of SAO and SA 1 faults at that line . Each of these sets is pictoriully depicted
in Figure 3.24( b ), where an unshaded and a shaded box , respectively, depict an SAO
and an SAI fault at the corresponding line .
The first line in the ordered list Q
, -
rim' 2 » is removed from the list . Since Z 2 is the
output of gate Gf , in this step all faults associated with the
inputs and output of gate

.F
•,'

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