Physical Structure

1
of CMOS ICs - 3
Lecture# 08
VLSI Design
 2 Basic Gate Designs
 NAND 2-Input Gate
 Design a CMOS schematic of 2-input NAND gate

VDD

a.b

a b
GND
 3 Basic Gate Designs
 OR 2-Input Gate
 Design a CMOS schematic of 2-input OR gate

VDD

a+b

a b
GND
 4 Class Exercise 1
 3-Input NAND Gate
 First design a CMOS schematic of 3-input NAND gate and then
design a CMOS layout of 3-input NAND gate.

VDD

a.b.c

a b c
GND
 5 Class Example 1
 3-Input OR Gate
 First design a CMOS schematic of 3-input OR gate and then design
a CMOS layout of 3-input OR gate.

VDD

a+b+c

a b c
GND
 6 Class Example 2
 Design CMOS schematic and Layout of the equation
 𝑓 𝑎 𝑏⋅𝑐

VDD
VDD

c b

a
f a+b.c

b
a
c c b a
GND
Gnd
 7 Class Exercise 2
 Design CMOS schematic and Layout of the equation
 𝑔 𝑎⋅ 𝑏 𝑐

VDD
VDD
c a

b
g a . (b + c)

c b a
b c GND

Gnd
8 Stick Diagrams

 Colored lines are used to represent patterns of layers, e.g.

 Polysilicon (gate): Red
 Doped n+/p+ (active): Green
 N-well: Yellow
 Metal1: Blue
 Metal2: Brown
 Contacts or via: Black X’s
 Fabrication Process of
CMOS Integrated
Circuits
9
10 Fabrication of CMOS ICs

 We have developed an understanding of physical structure of CMOS

 How patterns and layers are used to form a network
 Now, we will discuss how these layers are created
 The process starts with growing a single crystal silicon
 As shown in the figure below
11 Fabrication of CMOS ICs
 Creating Wafer

 The crystal is sliced to get thin wafers

 100 mm to 300 mm in diameter
 0.4 mm to 0.7 mm in thickness
 The sliced wafers passes a number of
steps
 To create a patterned wafer
 The patterned wafer contains multiple
die sites
 Die site is the location where circuit is
created
Wafer
 Each die site is a candidate for being a
chip Die

 The circuit is replicated on each die

12 Yield
 Not every die site turns out to be functional
 May be due to defects arise in manufacturing line or
 Due to defects in the silicon
 The percentage of the functional sites to total sites
 Is called Yield 𝑌 100 %

 Where 𝑁 is number of functional sites and 𝑁 is total number of sites

 High yields are desirable
 The total number of sites on a wafer

 𝑁 ⋅

r is effective radius
𝐴 is area of a single die
𝑑 is effective diameter
𝑑 is diameter of the wafer
𝑑 is wasted edge (due to rectangular sites)
13 Yield cont.

 Empirical analysis show

𝐴 Area of a single die
 𝑌 𝑒 D defect density
(average defect
 Increasing die area would result is lower yield per cm )

 𝐷 is limit of perfection, in modern tech around 1 cm .

 When several die fail in an large area 𝐴 of the Wafer (area 𝐴)

 𝑌 1 𝑔 𝑒 𝑔 fractional area
(where defects exist)
 𝑔

Yield analysis and improvement is a very specialized aspect of VLSI

Personnel from dynamic backgrounds work to increase yield
14 Economics
 It may be important to keep the economics in mind
 While designing, manufacturing and marketing VLSI chips
 Profit on a single chip 𝐶 Cost of manufacturing a
 Profit 𝐶 𝐶 chip (material, salaries,
equipment, infrastructure
 Here Profit 0, in order to survive and thrive and utility bills)
 A VLSI fabrication plant cost (to be recovered over the years)
 over a billion US dollars, may be up to 5 billion dollars or more
 Excluding running costs
 So, 𝐶 must include all these direct and in-direct costs
 𝐶 ≫𝐶
 With time 𝐶 tends to decrease
 𝐶 𝐶 (which is cheap)

It is possible that an idea may fail to attract customers

𝑃𝑟𝑜𝑓𝑖𝑡 0
15 Material Growth & Deposition
 We will now discuss creation of the layers
 As IC is stacking layers of various materials
 Both electrical properties and geometrical patterns are important
 Silicon Dioxide (SiO )
 Called “Quartz glass” or simply “glass”, primarily used for gate oxide
 Excellent electrical insulator
 Adheres (bond, attach & glued) well to most materials
 Can be grown on a silicon wafer or deposited on top of a wafer

 Creation of thermal (native) oxide SiO

 16 Material Growth & Deposition
 Thermal (native) Oxide SiO2
 Silicon dioxide can be grown on the wafer
 By passing oxygen over the surface (heat as a catalyst)
 The oxygen reacts with silicon in the wafer to form oxide layer
𝑂 Flow
𝑥 0.46 𝑥 𝑥
Heat as catalyst
Si O SiO
Surface

 This procedure is slow and produces high quality oxides Silicon Wafer
 Thermal oxide is native oxide, as it grows on the wafer
 A faster method is to use water (as steam) instead of O 𝑥

 Called wet oxidization

 Si 2H O steam → SiO 2H
Silicon Wafer
 In practice mixture of 𝑂 and steam are used

Most oxide layers in VLSI are well above the wafer. So, thermal oxide
growth is not possible.
17 Material Growth & Deposition
 Chemical Vapor Deposition (CVD) Oxide SiO2

 We can also create silicon dioxide layer using gaseous reaction

 And then deposit the created silicon dioxide onto the surface
 To provide and oxide coating (SiH4 = Silane)
 SiH gas 2O gas → SiO solid 2H O gas

 This method allows SiO molecules above the wafer

 This technique is called Chemical Vapor Deposition (CVD)
 Resulting oxide may be referred to as CVD oxides
 Deposition is possible at low temperature as well
SiO molecules
 Hence the name low-temperature-oxide (LTO)

CVD
oxide

Substrate