Logic Design using

1
MOSFETS – Part 2
Lecture# 03
VLSI Design
2 Complex Logic Gate in CMOS

 Single Circuit which contains several primitives operation

F (a, b, c) = 𝑎 ⋅ 𝑏 𝑐
 OR, AND, NOT gate are used
 Let us discuss number of gates used for this design

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

3 Complex Logic Gate in CMOS
 Structured Logic Design

 CMOS logic gates are intrinsically inverting

 So NAND, NOR and NOT are called universal gates
 CMOS logic offers two types of expressions
 And Or Invert (AOI)
 𝑔 𝑎, 𝑏, 𝑐, 𝑑 𝑎⋅𝑏 𝑐⋅𝑑
 𝑔 𝑎, 𝑏, 𝑐, 𝑑 𝑎 𝐴𝑁𝐷 𝑏 𝑎𝑛𝑑 𝑐 𝐴𝑁𝐷 𝑑
 𝑔 𝑎, 𝑏, 𝑐, 𝑑 𝑁𝑂𝑇 𝑎 𝐴𝑁𝐷 𝑏 𝑂𝑅 𝑐 𝐴𝑁𝐷 𝑑

 Or And Invert (OAI)

 ℎ 𝑤, 𝑥, 𝑦, 𝑧 𝑥 𝑦 . 𝑧 𝑤
 ℎ 𝑤, 𝑥, 𝑦, 𝑧 𝑥 𝑂𝑅 𝑦 𝑤𝑖𝑡ℎ 𝑤 𝑂𝑅 𝑧
 ℎ 𝑤, 𝑥, 𝑦, 𝑧 𝑁𝑂𝑇 𝑥 𝑂𝑅 𝑦 𝐴𝑁𝐷 𝑤 𝑂𝑅 𝑧

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

 4 Complex Logic Gate in CMOS
 Rule to Remember

 Parallel connected MOSFETs

 nMOS inverted OR 𝑎 𝑏
 pMOS inverted AND 𝑎 𝑏 𝑎⋅𝑏

 Serial connected MOSFETs

 nMOS inverted AND 𝑎⋅𝑏
 pMOS inverted OR 𝑎. 𝑏 𝑎 𝑏

 nMOS and pMOS have interchanging property

 𝑔 𝑎⋅ 𝑏 𝑐 nMOS Logic
 𝐺 𝑎 𝑏. 𝑐 pMOS Logic

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

5 Complex Logic Gate in CMOS
 Class Exercise 2
 Consider the complex function for AOI logic design
𝑋 𝑎 𝑏⋅ 𝑐 𝑑
 Schematic for pMOS logic
 Schematic for nMOS Logic
 Final schematic for X

𝑎
𝑏 𝑋
𝑐
𝑑
Or And Or-Invert

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

6 Complex Logic Gate in CMOS
 Bubble Pushing

 The pull-up network (PUN) contains

 pMOS (assert low switches)
 The pull-down network (PDN) contains
 nMOS (assert high switches)
 We convert the logic functions for CMOS implementation
 among assert-low (PUN) <–> assert-high (PDN) modeling
 Using De-Morgran’s law etc.
𝐴 𝐵 𝐴̅ · 𝐵
 𝐴. 𝐵 𝐴̅ 𝐵

 The graphical method to convert among PUN and PDN

 is called Bubble pushing
 Graphical representation of DeMorgan’s law

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

7 Complex Logic Gate in CMOS
 Bubble Pushing : Rules to Remember

 Construct Logic Diagram using basic AOI or OAI structure

 Use gate-nFET logic to construct the nFET logic between
output and ground
 To obtain pFET logic, start with original diagram and push
bubble back towards input using DeMorgan’s Rule.

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

8 Complex Logic Gate in CMOS
 Bubble Pushing : Home Task

 An AOAI logic gate is described in schematic given below

 Construct the nFET array using the logic diagram
 Apply bubble pushing to obtain the pFET logic. Use the
diagram to construct the pFET array using the pFET rules

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

9 Assignment # 1 – Part 2

 Make CMOS schematic of the following equations. Use Gate

schematics and bubble pushing logic for implementation
 𝑥 𝑎 𝑏 𝑐 𝑑
 𝑦 𝑎⋅𝑏 𝑐⋅𝑑
 𝑧 𝑎 𝑏 ⋅ 𝑐 𝑑

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi