ECE6133
Physical Design Automation of VLSI Systems
Objectives:
• Subthreshold Region I ds ≈ 0 , V gs ≤ V
V ds 2
• I ds = β ( V gs – V t )V ds – --------- O ≤ V ds ≤ V gs – V t
2
V ds 2
• I ds = β ( V gs – V t )V ds – --------- O ≤ V ds ≤ V gs – V t
2
Pattern definition by
photolithography
Etch
8 to 10 iterations
Photolithographic Process UV Radiation
Silicon dioxide
Photoresist (Negative )
Silicon
Hardened
Photoresist
Silicon dioxide
(c)
(d) etched where
Photoresist exposed
stripped
(e)
Design Rules
System
Specifications Chip
automation
Largenumber of devices
Optimization requirements for high performance
~
Time-to-market competition
Cost
M1 M2 M3
M4 M5 M6
Matrix Solver (20K)
• GDSII shots: manufacturing-ready
– Used Cadence Virtuoso, passed DRC
Matrix Solver (20K)
• GDSII shots: manufacturing-ready
– Specify all intra-cell details
MAC Unit (267K)
• Placement took 44 sec, routing took 289 sec
– Area = 320x320um, used 7 metal layers
MAC Unit (267K)
M1 M2 M3
M4 M5 M6
MAC Unit (267K)
M7
MAC Unit (267K)
Placement Routing
MAC Unit (267K)
32-bit Processor (2.7M)
• Placement took 739 sec, routing took 4740 sec
– Area = 1000x1000um, used 10 metal layers
32-bit Processor (2.7M)
M1 M2 M3
M4 M5 M6
32-bit Processor (2.7M)
M7 M8 M9
M10
Placement Comparison
• Runtime: 1 sec vs 44 sec vs 739 sec
1. System Specication
2. Functional Design
3. Logic Design
4. Circuit Design
5. Physical Design
~
6. Design Verication
7. Fabrication
8. Packaging, Testing, and Debugging
Functional Design
x = (AB*CD)+(A+D)+(A(B+C))
Logic Design
Y=(A(B+C)+AC+D+A(BC+D))
Circuit Design
Physical Design
Fabrication
Packaging
Physical Design
Physical Design
cutline 2
cutline 1
(a) Partitioning
Floorplanning
(b) &
Placement
(c) Routing
(d) Compaction
Fabrication
Design Styles
Complexity of
VLSI curcuits
Data path
PLA I/O
ROM/RAM
Random logic
A/D converter
D C C B
A C C
D C D B
C C C B
Cell library
Cell A Cell B
P G
2
C
E
(a)
P P P P
1 2 3 4
A B D B C E D E F D E G
0 0 0 0 0 0 0 0 1 0 0 0
0 1 1 0 1 1 0 1 1 0 1 0
1 0 1 1 0 1 1 0 1 1 0 0
1 1 0 1 1 1 1 1 0 1 1 1
(b)
VDD GND
A B B B
1 2 3
B B B B
4 5 6
B B B
C 7 8 9
B B B
10 11 12
F
(c)
style
full-custom standard cell gate array FPGA
cell size variable xed height xed xed
~ cell type variable variable xed programmable
cell placement variable in row xed xed
interconnections variable variable variable programmable
uneven height cells are also used.
style
full-custom standard cell gate array FPGA
Area compact compact moderate large
~ to moderate
Performance high high moderate low
to moderate
Fabrication layers All All routing layers none
Summary
1. Physical design is one of the steps in the VLSI design cycle.
2. Physical design is further divided into partitioning, placement, routing
and compaction.
3. There are ve major design styles, e.g., full custom, standard cell,
gate array, sea of gates and FPGAs.
~ 4. There are three alternatives for packaging of chips, e.g., PCB,
MCM and WSI.
5. Automation reduces cost, increases chip density, reduces time-
to-market, and improves performance.
6. CAD tools currently lag behind fabrication technology, which
is hindering the progress of IC technology.