MODULE 5

I/O SYSTEM
(note was given in class itself. Reference: William Stalling)
STANDARD I/O INTERFANCES
Reference : Call Hamacher, “Computer Organization”
I/O interface is a circuitry used for interconnecting an I/O device and the system bus.
The side of the interface that will be attached to the I/O device is called port and is classified
as serial port or parallel port. Parallel port transfers data in multi-bit form (8/16) to or from the
device. Parallel port uses a multi-pin connector and a cable with as many wires as the number
of bits transferred simultaneously. It is suitable for devices that are physically close to the
computer. Serial port transfers and receives data one bit at a time. It uses a single pin
connector and is useful for devices that are at a longer distance from the system.
The system bus is defined by the signals on the processor chip itself. Due to electrical reasons,
only a few devices can be connected directly to it and for remaining devices, motherboard
provides expansion buses. Some of the bus standards are Peripheral Component Interconnect
(PCI), Small Computer System Interface (SCSI) and Universal Synchronous Bus (USB).
a) Serial Port
Serial interface is used to connect the processor to I/O devices that transmit data one
bit at a time. Data are transferred in a bit-serial fashion on the device side and in a bit-parallel
fashion on the processor side. The transformation between the parallel and serial formats is
achieved with shift registers that have parallel access capability. A block diagram of a typical
serial interface is shown in Figure below.

Block diagram of Serial Interface

The input shift register accepts bit-serial input from the I/O device. When all 8 bits of data have
been received, the contents of this shift register are loaded in parallel into the DATAIN register.
Similarly, output data in the DATAOUT register are transferred to the output shift register, from
which the bits are shifted out one by one and sent to the I/O device. Presence of DATAIN &
DATAOUT registers in addition to the shift registers ensure double buffering so that the
interface can handle continuous stream of data.
Since it requires fewer wires, serial transmission is convenient for connecting devices that are
physically far away from the computer. Speed of transmission, known as bit rate, depends on
the nature of the device connected. Widely used serial interface standards are Universal
Asynchronous Receiver Transmitter (UART) and RS232-C.
b) Parallel Port
Parallel port was developed by IBM for connecting a printer to the computer. The basic
version can transmit 50 to 100 KB of data per second. Figure below shows the block diagram
of a general purpose parallel interface. D7-D0 are the connections to system bus and P7-P0 are
the connections to the I/O device. This can be used for both input and output purposes. It is
possible to configure any individual connection (out of total 8) as input or output by
programming the Data Direction Register (DDR). If DDR value is 1 for a given bit, corresponding
data line acts as output; otherwise it acts as input line.

One byte of data read from the I/O device at a time and is available in the DATAIN register. Its
output lines are connected to system bus by means of state buffers, which are turned on when
the processor issues a read command. Similarly, tri-state buffers are also provided between
DATAOUT register and I/O device. While writing data into the device, each byte is first held in
DATAOUT register and then passed via the buffers.
c) Peripheral Component Interconnect (PCI)
PCI was developed as a low-cost, processor-independent bus. It is housed in the
motherboard of a computer and used to connect I/O interfaces for a variety of devices. A
device connected to the PCI bus appears to the processor as if it is connected directly to the
processor bus. An important feature of PCI is the plug-and-play capability for connecting I/O
devices. To connect a new device, the user only needs to give the physical connection. All the
configuration requirements will be taken care of by the software.
  PCI bus is designed primarily to support a burst of data than just one word.
 It supports 3 independent address spaces: Memory, I/O, Configuration
 The I/O address space is intended to use with processor such as Pentium that have
separate I/O address space.
 The Configuration space is intended to give the PCI its plug and play capability.
 The PCI Bridge provides a separate physical connection for the main memory.
 A 4‑bit command identifies which of the three spaces is being used in each data transfer
operation.
 At any given time one device is the bus master. It has the right to initiate data transfer by
issuing read and write commands.
When an I/O device is connected to a computer, several actions are needed to configure both
the devices and software communities with it. The PCI simplifies this process by incorporating
in each I/O device interfaces a small configuration ROM memory that stores information about
the device. The configuration ROMs of all devices are accessible in the configuration address
space. By reading these ROM, PCI software can determine whether the device is a keyboard or
printer, an Ethernet controller or disk controller.
The PCI bus has gained great popularity. Both a 32-bit and a 64-bit configuration are available,
using either a 33-MHz or 66-MHz clock. A high-performance variant known as PCI-X is also
available. It is a 64-bit bus that runs at 133 MHz. Still higher performance versions of PCI-X run
at speeds up to 533 MHz.
d) Small Computer System Interface (SCSI)
SCSI refers to a standard bus defined by the American National Standards Institute
(ANSI). The SCSI bus is well-suited for use with disk drives. In the original specifications of the
SCSI standard, devices are connected to a computer via a 50-wire cable, which can be up to 25
meters in length and can transfer data at rates of up to 5 Megabytes. The standard has
undergone many revisions, and its data transfer capability has increased rapidly. SCSI-2 and
SCSI-3 have been defined, and each has several options. Data are transferred either 8 bits or
16 bits in parallel, using clock speeds of up to 80 MHz.
A controller connected to a SCSI bus is one of two types – an initiator or a target. An initiator
can select a particular target and to send commands specifying the operations to be
performed. Clearly, the controller on the processor side, such as the SCSI controller, must be
able to operate as an initiator. The disk controller operates as a target. It carries out the
commands it receives from the initiator. The initiator establishes a logical connection with the
intended target. Once this connection has been established, it can be suspended and restored
as needed to transfer commands and bursts of data. While a particular connection is
suspended, other device can use the bus to transfer information. This ability to overlap data
transfer requests is one of the key features of the SCSI bus that leads to its high performance.
Let us examine a complete Read operation as an example. Assume that the processor wishes
to read a block of data from a disk drive and that these data are stored in two disk sectors that
are not contiguous. The processor sends a command to the SCSI controller, which causes the
following sequence of events to take place:
1. SCSI controller sends a command to the disk controller, specifying the required Read
operation.
2. Data transfer cannot start immediately as the read head of the disk should be moved to
the required sector. Hence the disk controller suspends the connection to the SCSI
controller. The SCSI bus is now free to be used by other devices.
3. The disk controller sends a command to the disk drive to move the read head to the first
sector of the data. It reads the data and stores them in a data buffer. Now it re-
establishes the connection with SCSI controller, sends the contents of the data buffer
and suspends the connection again.
4. The process is repeated to read & transfer the contents of the second disk sector.
5. The SCSI controller transfers the requested data to the main memory and sends an
interrupt to the processor indicating that the data are now available.
e) Universal Serial Bus (USB)
USB is the most widely used interconnection standard today. The commercial success
of the USB is due to its simplicity and low cost. The original USB specification supports two
speeds of operation, called low-speed (1.5 Megabits/s) and full-speed (12 Megabits/s). Later,
USB 2 (High-Speed USB) was introduced which enables data transfers at speeds up to 480
Megabits/s. As I/O devices continued to evolve with even higher speed requirements, USB 3
(Super-speed) was developed supporting data transfer rates up to 5 Gigabits/s. The USB has
been designed to meet several key objectives:
 Provide a simple, low-cost, and easy to use interconnection system.
 Accommodate a wide range of I/O devices and bit rates, including Internet connections,
and audio and video applications.
 Enhance user convenience through a “plug-and-play” mode of operation.
USB architecture
USB uses point-to-point connections and a serial transmission format. When multiple
devices are connected, they are arranged in a tree structure as shown in Figure below. Each
node of the tree has a device called a hub, which acts as an intermediate transfer point
between the host computer and the I/O devices. At the root of the tree, a root hub connects
the entire tree to the host computer. The leaves of the tree are the I/O devices. The tree
structure makes it possible to connect many devices using simple point-to-point serial links.
USB operates strictly based on polling. A device may send a message only in response to a poll
message from the host processor. This restriction allows hubs to be simple, low-cost devices.
Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit address. The
host software communicates with individual devices by sending information to the root hub,
which it forwards to the appropriate device in the USB tree.
Electrical Characteristics
USB connections consist of four wires, of which two carry power, +5 V and Ground, and
two carry data. Thus, I/O devices that do not have large power requirements can be powered
directly from the USB. This obviates the need for a separate power supply for simple devices
such as a memory key or a mouse. Two methods are used to send data over a USB cable. When
sending data at low speed, a high voltage relative to Ground is transmitted on one of the two
data wires to represent a 0 and on the other to represent a 1. The Ground wire carries the
return current in both cases. Such a scheme in which a signal is injected on a wire relative to
ground is referred to as single-ended transmission. However, it is highly susceptible to noise
and Interference.
The High-Speed USB uses an alternative arrangement known as differential signaling. The data
signal is injected between two data wires twisted together. The ground wire is not involved.
The receiver senses the voltage difference between the two signal wires directly, without
reference to ground. This arrangement is very effective in reducing the noise seen by the
receiver. The ground wire acts as a shield for the data on the twisted pair against interference
from nearby wires. Differential signaling allows much lower voltages and much higher speeds
to be used compared to single-ended signaling.
 MEMORY SYSTEM
MEMORY HIERARCHY

CPU PRIMARY SECONDARY

CACHE
MEMORY MEMORY

REGISTERS MEMORY

Third level
 Secondary memory (external memory)  permanent storage
 Inexpensive and large size  called mass storage devices (HDD, CD etc)
 It provides an illusion of more capacity than actually exists in the main memory. Hence
called virtual memory.
Second level
 Primary memory (main memory)  faster than secondary memory
 Also called physical memory.
 Implemented using DRAM
 Still slow compared to processor speed.
First level
 Cache memory  very fast semiconductor memory
 Implemented using SRAM
 Expensive and hence used in small size.
 Physically implemented within the processor itself.
Cost of memory component is proportional to its speed of operation. Hence high-speed
components are used only in small size. i.e. there is a tradeoff between speed & capacity. All
memory components together provide reasonably fast system memory in large size at
reasonable cost.
Secondary memory stores the programs permanently. Only the required portion at any
moment of time is brought to main memory. Frequently used components of that portion will
be kept in Cache memory for fast access.
Whenever processor needs some information form memory, it first checks in cache. If found,
it is considered as cache hit. If not, it is a cache miss. Then, main memory is checked. If still not
found, the information is brought from virtual memory.
CHARACTERISTICS OF MEMORY SYSTEMS
Reference : William Stalling, “Computer organization and architecture”
The complex subject of computer memory is made more manageable if the memory
systems are classified as per their key characteristics. Most important of these are listed below.

The term location refers to whether memory is internal and external to the computer. Internal
memory is often equated with main memory. But there are other forms of internal memory.
The processor requires its own local memory, in the form of registers. Cache is another form
of internal memory. External memory consists of peripheral storage devices, such as disk and
tape, that are accessible to the processor via I/O controllers.
An obvious characteristic of memory is its capacity. For internal memory, this is typically
expressed in terms of bytes or words. Common word lengths are 8, 16, and 32 bits. External
memory capacity is typically expressed in terms of bytes.
A related concept is the unit of transfer. For internal memory, the unit of transfer is equal to
the number of electrical lines into and out of the memory module. This may be equal to the
word length, but is often larger such as 64, 128, or 256 bits. To clarify this point, consider three
related concepts for internal memory:
a) Word: The “natural” unit of organization of memory. The size of the word is typically
equal to the number of bits used to represent an integer and to the instruction length.
b) Addressable units: In some systems, the addressable unit is the word. However, many
systems allow addressing at the byte level.
c) Unit of transfer: For main memory, this is the number of bits read out of or written into
memory at a time. The unit of transfer need not equal a word or an addressable unit.
For external memory, data are often transferred in much larger units than a word, and
these are referred to as blocks.
Another distinction among memory types is the method of accessing units of data. Following
are the accessing methods:
a) Sequential access: Memory is organized into units of data, called records. Access must
be made in a specific linear sequence. Stored addressing information is used to separate
records and assist in the retrieval process. A shared read–write mechanism is used, and
this must be moved from its current location to the desired location, passing and
rejecting each intermediate record. Thus, the time to access an arbitrary record is highly
variable. Tape units are sequential access.
b) Direct access: As with sequential access, direct access involves a shared read–write
mechanism. However, individual blocks or records have a unique address based on
physical location. Access is accomplished by direct access to reach a general vicinity plus
sequential searching, counting, or waiting to reach the final location. Again, access time
is variable. Disk units are direct access.
c) Random access: Each addressable location in memory has a unique, physically wired-in
addressing mechanism. The time to access a given location is independent of the
sequence of prior accesses and is constant. Thus, any location can be selected at
random and directly addressed and accessed. Main memory and some cache systems
are random access.
d) Associative: This is a random-access type of memory that enables one to make a
comparison of desired bit locations within a word for a specified match, and to do this
for all words simultaneously. Thus, a word is retrieved based on a portion of its contents
rather than its address. As with ordinary random-access memory, each location has its
own addressing mechanism, and retrieval time is constant independent of location or
prior access patterns. Cache memories may employ associative access.
From the user point of view, two most important characteristics of memory are capacity and
performance. Three performance parameters are used:
a) Access time (latency): For random-access memory, this is the time it takes to perform
a read or write operation, that is, the time from the instant that an address is presented
to the memory to the instant that data have been stored or made available for use. For
non-random-access memory, access time is the time it takes to position the read–write
mechanism at the desired location.
b) Memory cycle time: This concept is primarily applied to random-access memory and
consists of the access time plus any additional time required before a second access can
commence. This additional time may be required for transients to die out on signal lines
 or to regenerate data if they are read destructively. Note that memory cycle time is
concerned with the system bus, not the processor.
c) Transfer rate: This is the rate at which data can be transferred into or out of a memory
unit. For random-access memory, it is equal to 1/(cycle time). For non-random-access
memory, the following relationship holds:

where
TN = Average time to read or write N bits
TA = Average access time
n = Number of bits
R = Transfer rate, in bits per second (bps)
A variety of physical types of memory have been employed. The most common today are
semiconductor memory, magnetic surface memory, used for disk and tape, and optical and
magneto-optical.
Several physical characteristics of data storage are important. In a volatile memory,
information decays naturally or is lost when electrical power is switched off. In a nonvolatile
memory, information once recorded remains without deterioration until deliberately changed;
no electrical power is needed to retain information. Magnetic-surface memories are
nonvolatile.
Semiconductor memory may be either volatile or nonvolatile. Nonerasable memory cannot
be altered, except by destroying the storage unit. Semiconductor memory of this type is known
as read-only memory (ROM). Of necessity, a practical nonerasable memory must also be
nonvolatile.
For random-access memory, the organization is a key design issue. It means the physical
arrangement of bits to form words.

INTERNAL ORGANIZATION OF A MEMORY CHIP

Reference : Carl Hamacher, “Computer Organization”
Memory cells are organized in the form of an array, in which each cell can store one bit of
information. Each row of cells constitutes a memory word and all cells of a word are connected
to a common line referred to as word line. It is driven by the address decoder on the memory
chip. The cells in each column are connected to a sense / write circuit via a bit line. During a
read operation, this circuit sense the information stored in the cells selected by a word line
and transmit to the output lines. During a write operation, it receives input information and
store in the cells of the selected word.
Figure below shows the internal organization of a memory chip consisting of 16 words of 8 bits
each i.e. 16 X 8 memory chip with a total capacity of 128 bits. To address 16 words, the system
needs 4-bit address bus (A3-A0). It also needs 8-bit data bus (D7-D0) since each word is of 8 bits.
Two control lines are additionally provided : and CS. The former specifies the required
operation (read / write) and the latter selects a specific chip in a multi-chip memory system.
To read a word from the chip, the bit lines are left floating. The control line is made high
to indicate the read operation. Now the address of the word to be read is applied to the
address bus. For example, to read word 1, make A3-A0 = 0001. The address decoder activates
corresponding word line W1. Thus, all the cells in row 1 are selected. Content of each cell drives
the connected bit line to that value. The data bus D7-D0 together gives the 8-bit data word.
Similarly, while writing into a word in the chip, all bit lines are first driven to the desired bit
values obtained from the data bus. The control line is made low and address of the word
is applied to the address bus. Thus, all the bit cells of the desired word are selected. Now, the
bit lines store the bit values into the memory cells of the word.

b7 b6 . . . . . . b0
W0

. . . . . . . .
W1
A0
Address decoder

. . . . .

A1
. . . . .

. . . . .
A2
A3
. . . . . . .
W15

Sense/write Sense/write Sense/write

. . . . . .
circuit circuit circuit CS

D7 D6 D0