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# Finite State Machines

CS 3410
Computer System Organization & Programming

## [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]

Stateful Components
Combinational logic
• Output computed directly from inputs
• System has no internal state
• Nothing depends on the past!

## Inputs Combinational Outputs

N circuit M
Need:
• to record data
• to build stateful circuits
• a state-holding device

## Enter: Sequential Logic & Finite State Machines

2
Finite State Machines
An electronic machine which has
◦external inputs
◦externally visible outputs
◦internal state

## Output and next state depend on

◦inputs
◦current state

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Automata Model
Finite State Machine
Current
Output
Registers State Comb.
Logic
Input Next State

## ◦ inputs from external world

◦ outputs to external world
◦ internal state
◦ combinational logic
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FSM Example
start
state input/output

## state state 0/0

1/0 0/0
Legend A B
1/1

Input: 1 or 0
Output: 1 or 0 What input pattern is
States: A or B
the FSM “looking for”?

[Mealy Machine] 5
Mealy Machine
General Case: Mealy Machine

Current
Registers
State Comb.
Output
Logic
Input Next State

## Outputs and next state depend on both

current state and input
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Moore Machine
Outputs depend only on current state

Current Comb.
Registers
State Logic Output
Comb.
Input Logic Next State

0 1
start
state input
1
A B 0 C
state state 0 0 1
out out
0
Legend
1 7
xkcd

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Why FSMs?
They help us reason about complex behavior.
waits Clicker Question:
What kind of machine is
wags
barks
gets petted tail this?
(A) Mealy
sees squirrel (B) Moore
ett ed
g e t s p (C) Neither
sits

doesn’t give a
crap about you

ve r !
e n t e
ev
any
https://learnyousomeerlang.com/finite-state-machines 9
Other FSMs
Tennis

http://blog.mikemccandless.com/201
4/08/scoring-tennis-using-finite-
state.html

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https://www.c-sharpcorner.com/article/understanding-state-design-pattern-by-implementing-finite-state/
Activity: Build a Circuit for a Serial Adder
Add two infinite input bit streams
◦streams sent with least-significant-bit (lsb) first
…10110
…00101
…01111

Clicker Question:
How many states are needed
to represent this FSM?
(a) 0 (d) 3
(b) 1 (e) 4
(c) 2 11
Strategy for Building an FSM
(1) Draw a state diagram
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state
and outputs
(5) Draw the circuit

12
Step 1: State Diagram
start
state input/output

state state
S0
Legend

…10110
…00101
…01111

States:
Inputs: a and b (drawn as 2-bit input ab)
Output: z 13
Strategy for Building an FSM
(1) Draw a state diagram
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state
and outputs
(5) Draw the circuit

15
Step 2: Output & Next State Tables
Curr Next
a b State z State
s s’

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Strategy for Building an FSM
(1) Draw a state diagram
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state
and outputs
(5) Draw the circuit

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Step 3: Create Bit Encoding
Curr
Next
a b State z
State s’
Encode states as bits
s
S0 =
S1 =
2 states à 1-bit enough
(1-hot also an option)

## Copy from previous

Make a binary
encoding instead of
names
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Strategy for Building an FSM
(1) Draw a state diagram
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state
and outputs
(5) Draw the circuit

21
Step 4: Create Logic Equations
Determine logic equations for next state and
outputs

s’ =

z =
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Strategy for Building an FSM
(1) Draw a state diagram
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state
and outputs
(5) Draw the circuit: Simplify first!

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Step 5: Draw the Circuit
Next Current Output
State State z
s' s
D Q
a
b

s'

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FSMs in a Processor?
• multi-cycle (non-pipelined) processor

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FSMs in a Processor?
• multi-cycle (non-pipelined) processor
• handling cache misses, branch mispredictions,
interrupts
• tracking the state of data in your cache (cache
coherency)

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Consider a finite state machine that takes two inputs, A and B, and
generates a single output, Z. Inputs are unsigned binary numbers,
entered into the FSM one digit at a time, beginning with the most
significant digit. The output, Z, should be the larger of the two numbers.
Example: A = 1000 and B = 0101, then Z = 1000 (the value of A).

Draw the state transition diagram (states & arrows) that expresses this
FSM. Use the notation AB for inputs (10 means A = 1 and B = 0).

## (1) Draw a state diagram

(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state and outputs
(5) Draw the circuit
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Clicker Question:
How many states are needed
to represent this FSM?
(a) 0 (d) 3
(b) 1 (e) 4
(c) 2

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