Design and Simulation Of

LNA
(Cadence Spectre RF)

by
Kushaal Gajavelly, ECE, 16116034

Kuridi Uday Kiran, ECE, 16116033

 Introduction

LNA is a special type of electronic that widely used in wireless communication system. Generally, the main
goal of LNA design is to achieve simultaneous a low noise and high-power gain for the given power
dissipation and frequency condition. There are several fundamental low noise amplifier topologies for
single ended narrow band low power low voltage design, such as resistive termination common source,
common gate, shunt series feedback common source, inductive degeneration common source, cascade
inductor source degeneration. The design is based on a cascade configuration including feedback to the
common source amplifier for simultaneous noise and input impedance matching. This project describes
the operation and the simulation of gain and a minimum noise figure using 180nm CMOS technology.

Purpose

We will use S-Parameters (SP), Periodic Steady State Analysis (PSS), Periodic AC (PAC) and Pnoise
analysis available in SpectreRF to simulate above parameter of LNA. Usually there is more than one
method available to simulate the desired parameter; we will use the procedure recommended by
cadence and takes less simulation time.

1. S-Parameter Analysis

• Small Signal Gain (S21, GA, GT, GP)

• Small Signal Stability (Kf and ∆ or Bif )
• Small Signal Noise (SP and Pnoise)
• Input and Output Matching (S11, S22, Z11, Z22)

2. Large Signal Noise Simulation (PSS and Pnoise)

3. Gain Compression, 1dB Compression Point (Swept PSS)

4. Large Signal Voltage Gain and Harmonic Distortion (PSS)

5. IP3 Simulation (Swept PSS) 6. Conversion Gain and Power Supply Rejection Ratio (PSS and PXF)
 LNA Design

Inductive degeneration topology offers the lowest noise figure and no resistors are required here. It is
called inductive degeneration because the L3 inductor is connected in such a way that the current through
it opposes the current through the gate of the transistor M1 (negative feedback).

The transistor M2 is connected in common gate connection and the transistor M1 is connected in common
source connection. Together they form a cascode, this cascode connection is necessary to provide the
required isolation between the input and the output, reduce the effect of miller effect caused by gate-
drain capacitance Cgd of the M1 transistor. The inductors L1 and L3 are chosen in such a way as to provide
matching to the output resistance of the antenna. Their combination forms the input resistance (Rs)
where is matched to the output of the antenna for favorable results.

Schematic Of LNA

The transistor M3, R1 and R2 forms the biasing circuit. They are used to set the prerequisite DC voltage
so that the transistor can operate in the correct region (Region 2 in this case). Transistor M1 forms a
current mirror with the transistor M3, whose width is just a fraction of the width of M1 to minimize the
current through it and hence save power. The current through the transistor M3 is set by the supply
voltage as well the resistor R1 which is chosen to be around 500Ω. The resistor R2 has to be large enough
so that the equivalent noise current is small enough to be ignored. Here it is chosen to be around 5KΩ
(optimized). The capacitor C3 forms the final piece of the DC biasing circuit. It acts a DC blocking capacitor
and should be large enough to provide a negligible reactance at the frequency of 1.57542 Ghz. Here it is
chosen as 1.2Pf

The inductor L2, Capacitor C2 and the resistor R3 form the output matching circuit.Together they form a
parallel tank circuit as opposed to a series tank circuit at the input of the transistor M1. Supply voltage
used here is just 0.5V.
Design of LNA at 180nm

STEP 1: Calculation of gate-oxide Capacitance (Cox)

Cox=ɛox/tox
ɛox=ɛo* ɛr
Where ɛox=Permitivity of gate oxide
tox=Thickness of gate oxide
ɛo=Free space permittivity = 8.854*10-12 F/m
ɛr=3.9
Hence, we get ɛox=3.45*10-11 F/m
so, Cox=3.45*10-11/4.1*10-9 = 8.42*10-3 F/m2

STEP2: Calculation of optimum width of the transistor M1

Wopt = 1/(3*Cox*w*L*Rs)

Where Cox= Capacitance of the gate oxide

W = Angular Frequency
L = Length Of Device
Rs = Source Resistance
Hence, we obtain
Wopt = 1/(3*(8.854*10^-12)*(2*pi*1.57542*10^9)*(180*10^-9)*50)
= 444um

STEP3: Calculation of Gate Source Capacitance (Cgs)

Cgs = (2*Wopt*Cox*L)/3
Substituting the values of Wox = 444um, Cox = 8.42*10^-3, L = 180nm
We get Cgs = 449fF

STEP4: Calculation of Source Inductor L3

Input impedance looking into the LNA,

Z=jωLs+ + (gm*Ls)/Cgs + 1/(jwCgs)

The individual inductance and capacitance part would be resonated out

and the remaining part should be effectively equal to 50,so we get
(gm*Ls)/Cgs=50
Substituting the values of gm and cgs in the above,we get Ls=400pH

STEP 6: Calculation Of Gate Inductor L1

We are employing a series resonant circuit at the input, to set the

resonant frequency. The resonant frequency of a series resonant circuit
is as follows:
F= 1/(2*pi*((Lg+Ls)Cgs)^0.5)

Substituting the obtained values of Lgs and Cgs, we get Lg=22nH

STEP 7: Calculation Of Output Inductor

The equation that governs the output matching is as follows:

Z = gm*rds*Zs + Zs + rds
Where gm is the transconductance,
rds is the drain to source resistance,
Zs is the source impedance.
The formula for the resonant frequency of a parallel resonant circuit
is as follows:
F=1/ (2*pi*(1/(L*C)-R^2/L^2)0.5)

We need to work on the formula of Z twice as we have two cascaded

amplifiers, by substituting the values of gm,rds ,Zs , R and C values
of the parallel resonant circuit we obtain the value of L as
approximately 17.7 nH. R is chosen as 50k and C is chosen as 220p.

LNA Circuit Diagram (Source Inductor Degenerated LNA)

LNA Test Bench
 Simulation Results

1. S parameter analysis

• S parameters

LNA S parameters plot

Is the matching good?

The above S parameters obtained are good in terms of Gain (S21), which should be as high as possible,
reverse isolation (S12), which should be as low as possible, Input matching (S11) and Output matching
(S22), should be close to zero which can be seen in above graph.
 • GT, GA and GP (Different types of Gain)

GT, GA and GP Plots

The power gain GP is closer to the transducer gain GT than the available gain GA, which means that the
input matching network is properly designed, i.e. s11 is close to zero.
 • Noise Figure

NF and NFmin Plots

Noise figure is the ratio of the SNR at the input terminal of the system to the SNR at the output
terminals of the system. The noise figure is always greater than one because of the output SNR
is always lower than input SNR. For an ideal amplifier, we know that there are no additional noise
introduced by the different stages of the receivers. So, we can say that the noise figure of an ideal
amplifier is unity.
Here, from the above graph, The Noise figure is almost unity at the desired Frequency (1.6GHz).
So, there is minimum noise introduced in the amplifier stage.
 • Stability Factor Kf (Stern or Rollet) and B1f (intermediate term ∆)

Kf and B1f plots

The Rollet Stability Test (K-delta Test)

The K-delta Stability Test says that the amplifier is stable if K>1 (Rollet Stability Factor) and Delta < 1

From the above graph, at frequency 1.57Ghz, the above stability rule satisfies and hence the amplifier is
stable.

2. Large Signal Noise Simulation

Use the hb and hbnoise analyses for large-signal and nonlinear noise analyses, where the circuits are
linearized around the periodic steady-state operating point (the Noise and SP analyses are used for small-
signal and linear noise analyses, where the circuits are linearized around the DC operating point.)

As the input power level increases, the circuit becomes nonlinear, harmonics are generated, and the noise
spectrum is folded. Therefore, you should use the hb and hbnoise analyses. When the input power level
remains low, the NF calculated from the hbnoise, hbsp, Noise, and SP analyses should all match.

• Noise Figure (NF)

Noise Figure Plot

 • Input and Output Noise

Input and Output Noise Plot

The simulated Noise Figure should be similar to the SP analysis.

The Noise summary shows you the contributions of different noise sources in the total noise. This
is very powerful feature to focus the effort to improve the noise performance of the device that
contributes the maximum noise.
 3. Gain Compression (Swept hb and Xdb)

hb analysis calculates the operating power gain, which is the ratio of power delivered to the load
divided by the power available from the source. This gain definition is the same as that for GP, so
the gain from hb should match GP when the input power level is low and nonlinearity is weak.

Swept hb analysis can be used to calculate the compression point (input or output referred)
 • Compression curve and Compression point

Compression Curve Plot

A dedicated Xdb compression option is integrated for the hb analysis form. It calculates
compression points and compression curves directly, without the need for post processing or
manual setup of power sweeps. It supports voltage and power-based compression point
calculation. It is extremely useful when a large number of compression simulations are needed
such as in the corner simulations or MC (Monte Carlo) analysis
 • Using Xdb analysis

Compression Point using Xdb analysis

4. IP3 Measurement: hb Analysis with Two Tone

A two-tone test is normally used to measure an IP3 curve where the two input tones are ω1 and ω2. Since
the first-order components grow linearly and third-order components grow cubically, they eventually
intercept as the input power level increases. The IP3 is defined as the crossing point of the power for the
1st order tones, ω1 and ω2, and the power for the 3rd order tones, 2ω1 – ω2 and 2ω2 - ω1, on the load
side.
There are several simulation methods to measure IP3. In this lab, we will use hb analysis with two tones.
The hb analysis method treats both tones as large signals and uses an hb analysis with two tones.