PD-93991D

AUTOMOTIVE MOSFET
IRF1405
Typical Applications
O Electric Power Steering (EPS) HEXFET® Power MOSFET
O Anti-lock Braking System (ABS)
O Wiper Control D
O Climate Control VDSS = 55V
O Power Door
Benefits RDS(on) = 5.3mΩ
O Advanced Process Technology G
O Ultra Low On-Resistance
O Dynamic dv/dt Rating ID = 169A†
S
O 175°C Operating Temperature
O Fast Switching
O Repetitive Avalanche Allowed up to Tjmax
Description
Specifically designed for Automotive applications, this
Stripe Planar design of HEXFET® Power MOSFETs
utilizes the latest processing techniques to achieve
extremely low on-resistance per silicon area. Additional
features of this HEXFET power MOSFET are a 175°C
junction operating temperature, fast switching speed
and improved repetitive avalanche rating. These benefits TO-220AB
combine to make this design an extremely efficient and
reliable device for use in Automotive applications and a
wide variety of other applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 169†
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 118† A
IDM Pulsed Drain Current  680
PD @TC = 25°C Power Dissipation 330 W
Linear Derating Factor 2.2 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 560 mJ
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy‡ mJ
dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting Torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.45 °C/W
RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––
RθJA Junction-to-Ambient ––– 62
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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 4.6 5.3 mΩ VGS = 10V, ID = 101A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 69 ––– ––– S VDS = 25V, ID = 110A
––– ––– 20 VDS = 55V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 170 260 ID = 101A
Qgs Gate-to-Source Charge ––– 44 66 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– 62 93 VGS = 10V„
td(on) Turn-On Delay Time ––– 13 ––– VDD = 38V
tr Rise Time ––– 190 ––– ID = 101A
ns
td(off) Turn-Off Delay Time ––– 130 ––– RG = 1.1Ω
tf Fall Time ––– 110 ––– VGS = 10V „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package G

LS Internal Source Inductance ––– 7.5 –––

and center of die contact S

Ciss Input Capacitance ––– 5480 ––– VGS = 0V

Coss Output Capacitance ––– 1210 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 280 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 5210 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 900 ––– VGS = 0V, VDS = 44V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance … ––– 1500 ––– VGS = 0V, VDS = 0V to 44V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 169†

(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 680

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 101A, VGS = 0V „
trr Reverse Recovery Time ––– 88 130 ns TJ = 25°C, IF = 101A
Qrr Reverse RecoveryCharge ––– 250 380 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by … Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11).
as Coss while VDS is rising from 0 to 80% VDSS .
‚ Starting TJ = 25°C, L = 0.11mH
† Calculated continuous current based on maximum allowable
RG = 25Ω, IAS = 101A. (See Figure 12).
junction temperature. Package limitation current is 75A.
ƒ ISD ≤ 101A, di/dt ≤ 210A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C ‡ Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
„ Pulse width ≤ 400µs; duty cycle ≤ 2%. avalanche performance.
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1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
I D , Drain-to-Source Current (A)

I D , Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V
100

100

10

4.5V 4.5V

20µs PULSE WIDTH 20µs PULSE WIDTH

TJ = 25 °C TJ = 175 °C
1 10
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0
TJ = 25 ° C ID = 169A
RDS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)

TJ = 175 ° C 2.5

100 2.0
(Normalized)

1.5

10 1.0

0.5

V DS = 25V
20µs PULSE WIDTH VGS = 10V
1 0.0
4 6 8 10 12 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature( °C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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20
100000 ID = 101A
VGS = 0V, f = 1 MHZ
VDS = 44V
Ciss = Cgs + Cgd, Cds SHORTED

VGS , Gate-to-Source Voltage (V)

VDS = 27V
Crss = Cgd
16
Coss = Cds + Cgd
C, Capacitance(pF)

10000
Ciss 12

Coss 8
1000

Crss 4

FOR TEST CIRCUIT

100 SEE FIGURE 13
0
1 10 100 0 60 120 180 240 300

VDS, Drain-to-Source Voltage (V) QG , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000
10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD , Reverse Drain Current (A)

TJ = 175 ° C
ID, Drain-to-Source Current (A)

1000
100

100 100µsec
TJ = 25 ° C
10 1msec
10

Tc = 25°C
Tj = 175°C 10msec
V GS = 0 V Single Pulse
1 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0 1 10 100 1000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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200 RD
LIMITED BY PACKAGE VDS

VGS
160 D.U.T.
RG
I D , Drain Current (A)

+
-VDD
120
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
80

Fig 10a. Switching Time Test Circuit

40
VDS
90%
0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

1
Thermal Response (Z thJC )

D = 0.50

0.1 0.20

0.10
0.05
0.02 SINGLE PULSE
0.01 (THERMAL RESPONSE) PDM
0.01
t1
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.001
0.00001 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF1405

15V 1200
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 41A
1000 71A
VDS L DRIVER BOTTOM 101A

800
RG D.U.T +
V
- DD
IAS A
20V
600
tp 0.01Ω

400
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp 200

0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature( °C)

I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG

10 V
QGS QGD 4.0

VG 3.5
VGS(th) , Variace ( V )

Charge 3.0 ID = 250µA

Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
2.5

50KΩ

12V .2µF 2.0

.3µF

+
V
D.U.T. - DS
1.5
VGS -75 -50 -25 0 25 50 75 100 125 150 175

3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
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1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs
Avalanche Current (A)

100 0.01 avalanche pulsewidth, tav

assuming ∆ Tj = 25°C due to
avalanche losses
0.05

0.10
10

1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

600 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
500 ID = 101A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

temperature far in excess of Tjmax. This is validated for

every part type.
400 2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
300
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
200 avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
100 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3·BV·Zth]
Vs. Temperature EAS (AR) = PD (ave)·tav
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IRF1405
Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T* • Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• ISD controlled by Duty Factor "D" VDD
-
• D.U.T. - Device Under Test
VGS

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.
Period D=
P.W. Period

[VGS=10V ] ***

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
[VDD]
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% [ ISD]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

Fig 17. For N-channel HEXFET® power MOSFETs

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TO-220AB Package Outline (Dimensions are shown in millimeters (inches))

TO-220AB Part Marking Information

E XAMPL E : T HIS IS AN IR F 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997 INT E R NAT IONAL PAR T NU MB E R
IN T HE AS S E MB L Y L INE "C" R E CT IF IE R
L OGO
Note: "P" in assembly line
position indicates "Lead-Free" DAT E CODE
YE AR 7 = 1997
AS S E MB L Y
L OT CODE WE E K 19
L INE C

TO-220AB packages are not recommended for Surface Mount Application.

Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/04
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/