EXPERIMENT NO.

OBJECTIVE:

To design and implement the circuit of MOD-8 asynchronous and MOD-6 synchronous counters
using J-K flip-flops.

EQUIPMENT/APPARATUS USED:
S. No. Name of the equipment Range/Rating Make
1. Digital IC Trainer .... IC 74151
2. ... ... ...

A) Mod-8 Asynchronous counter

BRIEF THEORY:
Digital counters are sequential building blocks made by cascading flip-flops (FF) together. These
versatile units count the number of pulses arriving at its clock input. It counts in terms of binary
numbers.
Asynchronous/ripple counters are constructed in such a way that the count pulses in effect ripple
through FF chain. The output of first FF is the clock input to the second. Any state change in 2 nd FF
occurs, after 1st FF changes its state. This continues down the chain. A 3 bit (modulo-8) counter is
shown in Fig. 1 and its transition table in table 1.

LOGIC DIAGRAM:

Q2 1 Q1 1 Q0 1

Q PR CL J Q PR CL J Q PR CL J Clock
pulse
CLK CLK CLK
FF2 FF1 FF0
Q K Q K Q K
1

Figure 1 (a): A 3 bit (MOD-8) ripple counter

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 1 2 3 4 5 6 7 8
CLOCK

0 1 0 1 0 1 0 1 0
Q0

0 0 1 1 0 0 1 1 0
Q1

0 0 0 0 1 1 1 1 0
Q2
000 001 010 011 100 101 110 111 000

Figure 1 (b): Timing Diagram of 3 bit ripple counter

Table 1:

No. of clock pulses input to FF 0 Q2 Q1 Q0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 0 0 0

PROCEDURE:
1. Make connections as shown in Figure 1 (a). The JK FFs are converted to T FFs by connecting JK
inputs of all FFs to 1. Connect a pulser switch to the clock input to flip-flop FF0. Q0 goes to clock
input of FF 1 and Q1 goes to clock input of FF2 and so on.

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2. Put CL and PR high by means of logic input switches.
3. Apply the clock of pulses through the pulser switch to the clock input of FF0.
4. Verify the count sequences of Table 1.

OBSERVATIONS:
Verify and note down the count sequence for each clock input given in Table 1.

(B) MOD-6 synchronous counter:

BRIEF THEORY:
In synchronous counter, all FFs are controlled by common clock input. Here all FF changes states
simultaneously. However J and K inputs of each flip-flop are obtained from the combination of
outputs Q2, Q1 and Q0 according to the state transition of the counter. Fig. 2 show the circuit diagram
of Mod-8 counter.

LOGIC DIAGRAM:

Q 2 Q Q
Q 1
1
1
0

J Q Q J Q J Q
0

Q 0 CLK CLK CLK

FF2 Q 2 FF 1 Q 1
FF 0 Q
K Q K Q K Q 0

Clock
Input

Figure 2: MOD-8 Synchronous counter

DESIGN:
In designing a Mod-n synchronous counter, following steps are involved:
Step 1) Number of flip-flop, N, required to implement Mod-n is calculated as
N = log
where = smallest integer greater than or equal to x. e.g., for mod-6 synchronous counter,
the number of FFs = 3.
Step 2) Identify the no of states that counter will count and draw the state transition diagram. Typical
state diagram is shown in Fig 3 for count sequence 0,1,2,3,4,5 and repeat. In similar way,

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 each group has to design state transition diagram of Mod-6 counter for count sequence
assigned in Table 2.

000 001

101 010

100 011
Figure 3 Typical State transition diagram for Mod-6 counter

Table 2: Assignment of count sequence

Group No Count Sequence Group No Count Sequence
Group 1 0,3,4,5,6,7 and repeat Group 9 0,1,2,4,6,7 and repeat
Group 2 0,1,4,5,6,7 and repeat Group 10 0,1,2,3,5,7 and repeat
Group 3 0,1,2,5,6,7 and repeat Group 11 0,1,2,3,4,6 and repeat
Group 4 0,1,2,3,6,7 and repeat Group 12 0,2,3,5,6,7 and repeat
Group 6 0,1,2,3,4,7 and repeat Group 13 0,1,3,4,6,7 and repeat
Group 7 0,2,4,5,6,7 and repeat Group 14 0,1,2,4,5,7 and repeat
Group 8 0,1,3,5,6,7 and repeat Group 15 0,1,2,3,5,6 and repeat

Step 3) Construct the Excitation table for the count sequence as detailed in step 2. As an example,
Table 3 shows the excitation table for the count sequence shown in Fig. 3.

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 Table 3. Excitation Table of MOD-6 synchronous counter

Present State Next State Flip-flop inputs

( (

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 0 0 0 X 1 0 X X 1

Note:
a) Make use of JK excitation table (Table 4) to construct Table 3.
b) The invalid states are considered as don’t care. For example, the states 110, 111 are not
valid states for Mod-6 counter for the state diagram shown in Fig. 3, hence considered as
don’t care.
Table 4: Excitation Table of JK FF

Qn Qn+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Qn : Present state, Qn+1 : Next state, X : don’t care

Step 4) Find the logic expression of J2, K2, J1, K1, J0, and K0 in terms of Q2 Q1Q0 using K-map. As
an illustration, Fig 5 shows the steps to obtain the expression for Ji and Ki for the excitation
Table shown in Table 3.

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 Q1Q0 Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 X X 1 0 0 1 X X 1 0 X 1 1 X

1 X X X X 1 1 X X X 1 X 1 X X

K1= Q0 J0= 1 K0= 1

Figure 5. K-Map for J2, K2, J1, K1, J0, and K0 for the excitation Table 3

Step 5) Use the logic expression obtain in step 4 to develop the logic diagram of the designed Mod-
6 counter. For example, the logic diagram given in Fig. 6 is developed for the count sequence
of Fig. 3

Q 2 Q Q
Q 1 Q
2
1
1
0

J Q J Q J Q
Q 0 CLK Q 0 CLK CLK
FF2 Q 2 FF1 Q FF0 Q
K Q K Q 1
K Q 0

Clock
Input

Figure 6: MOD-6 Synchronous counter for the state diagram shown in Fig. 3

PROCEDURE:
1. Make the connections for the logic circuit obtain in step 5 under design procedure.
2. Clear all the FFs.
3. Apply clock pulse and verify the count sequences for the designed MOD-6 synchronous counter.

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OBSERVATIONS:
Verify and note down the count sequence after each clock pulse is applied as given in Table 5.
Table 5: Output sequence of MOD-6 Synchronous counter
Outputs
No. of clock pulses
Q2 Q1 Q0
0 0 0 0
1
2
3
4
5
6

REFERENCES:
1. R. J. Tocci, N Widmer, and G. L. Moss, “Digital Systems, Principles and Applications”, Pearson,
10th Edition, 2013.
2. Mano, M. M., “Digital Logic and Computer Design”, PHI, 1989, 3rd Edition.
3. Millman, and Grabel, A., “Microelectronics”, New York: Mc Graw Hill, 2nd Edition, 2010.

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