Advance Computer Architecture

Lecture 06

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 Recap of Lecture 05
• Optimizing the common case
• Amdahl’s Law
• The processor performance equation
• Using CPI in CPU time formula
• The CPU time triangle
• Fundamentals of CPU
• The Von Neumann Computer Model
• Generic CPU Machine Instruction Processing
Steps
 Recap of Lecture 05
• Functions of processors
• Structure of Processor
• Types of registers
• Example Microprocessor Register Organizations
• Instruction encoding
• Sign-Magnitude Representation
• Four common types of instructions
• Instruction set architecture
• Changing Definitions of Computer Architecture
• Evolution of Instruction Sets
Principles of Instruction set architecture
 Changing Definitions of Computer
Architecture
• The three pillars of computer architecture are:
– hardware,
– Software and
– instruction set
• Hardware facilitates to run the software and
instruction set is the interface between the
hardware and software.
Changing Definitions of Computer
Architecture (cont.)

software

instruction set

hardware
 Changing Definitions of Computer
Architecture (cont.)
• Serves as an interface between software and
hardware.
• Provides a mechanism by which the software
tells the hardware what should be done.

High level language code : C, C++, Java, Fortran,

compiler
Assembly language code: architecture specific statements
assembler
Machine language code: architecture specific bit patterns

software

instruction set
hardware
 Changing Definitions of Computer
Architecture (cont.)
• 1950s to 1960s:
– From the academic point of view, during the period 1950s -
1960s, the focus of computer architecture studies has been on
the Computer arithmetic; i.e., the methodologies for the
optimal solutions to arithmetic and logical problems.

• 1970s to mid 1980s:

– The focus of Computer Architecture Course has been Instruction
Set Design, the portion of the computer visible to programmer
and compiler writer
– Researchers realize that importance must be given to enhance
the performance of the computer and reduce the complexity of
hardware and hence optimize the price-performance.
 Changing Definitions of Computer
Architecture (cont.)
• 1990s to date:
– The focus of the computer architecture studies
is multidimensional & emphasize is on the Design
of CPU, memory system, I/O system,
Multiprocessors based on the quantitative
principles to have price - performance design; i.e.,
maximum performance at minimum price
 Instruction set architecture
• The design of hardware and software can’t be
initiated without defining ISA.

• It describes the instruction word format and

identifies the memory addressing for data
manipulation and control operations
• Major advances in computer architecture are
typically associated with landmark instruction set
designs – stack, accumulator, general purpose
register etc.
Instruction set architecture (cont.)
• Remember in Lecture 01, we define computer
architecture as “attributes of computer system
only visible to compiler writer or system
programmer”
• But we now use the same definition for ISA
• That’s why ISA is called the myopic view of
computer architecture.
– i.e. when you don’t want to dive into the details of
computer architecture, you could consider ISA as the
architecture of a specific computer system.
 Instruction Set Design Issues
• Instruction set design issues include:
– Where are operands stored?
• registers, memory, stack, accumulator
– How many explicit operands are there?
• 0, 1, 2, or 3
– How is the operand location specified?
• register, immediate, indirect, . . .
– What type & size of operands are supported?
• byte, int, float, double, string, vector. . .
– What operations are supported?
• add, sub, mul, move, compare . . .
 Seven dimensions of ISAs
• Class of ISA: e.g. stack, accumulator, GPR
• Memory addressing: how memory addresses specified
& interrupted?
• Addressing modes: given a numeric value for a
memory address how to identify the actual object to
access i.e. effective address? Register, immediate,
displacement, PC relative
• Types and sizes of operands: how the type of operand
is specified? Part of the opcode or something else
• Operations: what type of instructions are support?
ALU, FP, data transfer, control, graphics etc.
 Seven dimensions of ISAs (cont.)
• Control flow instructions: the execution
behavior of jump, branch, procedure
call/return.
– How the effective address is calculated? What is
tested in conditional branches? Where the return
address is stored?
• Encoding an ISA: length & encoding(format) of
instructions
– fixed-length, variable length
Classifying instruction set architectures
 Class of ISAs
• The type of internal storage in a processor is the
most basic differentiation i.e.,
– how the operands of an instruction are store?
• Operands can be specified explicitly in an
instruction or assumed implicitly.

• Three choices for ISA:

1. Stack Architecture
2. Accumulator Architecture
3. Set of registers
 Class of ISAs (cont.)
• Stack Architecture: operands are implicitly at the top of
stack.
• Accumulator Architecture: operand is considered implicitly
in the accumulator.
– An accumulator is a special register within the CPU that serves
both as both implicit source of one operand and as the
destination of results of ALU operations.
– Thus, it accumulates or collect data and doesn’t serve as an
address register at any time
– Limited number of accumulators - usually only one – are used

• General purpose register (GPR) architecture: have only

explicit operands—either registers or memory locations.
Operand Locations in Four ISA Classes
GPR
 Code Sequence C = A + B
for Four Instruction Sets
Stack Accumulator GPR GPR (register-
(register-memory) register / load-
store)
Push A Load A Load R1, A Load R1,A
Push B Add B Add R1, B Load R2, B
Add Store C Store C, R1 Add R3, R1, R2
Pop C Store C, R3

memory memory
acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2
 Three types of GPR architecture
• Previous slide shows two classes of GPR.
– Register-memory: can access memory as part of
any instruction
– Register-register: access memory only with load
and store instructions

• A third class called memory-memory is also

possible but not found in computers shipping
today keeps all operands in memory.
 Evolutions of ISAs
Accumulator (before 1960, e.g. 68HC11):
1-address add A acc acc + mem[A]

Stack (1960s to 1970s):

0-address add tos tos + next

Memory-Memory (1970s to 1980s):

2-address add A, B mem[A] mem[A] + mem[B]
3-address add A, B, C mem[A] mem[B] + mem[C]

Register-Memory (1970s to present, e.g. 80x86):

2-address add R1, A R1 R1 + mem[A]
load R1, A R1 mem[A]

Register-Register (Load/Store, RISC) (1960s to present, e.g. MIPS):

3-address add R1, R2, R3 R1 R2 + R3
load R1, R2 R1 mem[R2]
store R1, R2 mem[R1] R2
 Evolutions of ISAs (cont.)

ISA

Accumulator Stack GPR

- EDSAC 1950 Register-Memory Register-Register

- 68HC11
CISC RISC

- MIPS
- Intel iAPX 432
- SPARC
- Intel 8080, 8086
- IBM Power ISAs
- IBM 360/370
- ARM
 Evolutions of ISAs (cont.)
• Early computers use stack or accumulator type
architecture, new architecture designed after
1980 are GPRs.
• Two reasons for emergence of GPRs
– Registers—like other forms of storage internal to
the processor—are faster than memory.
– Registers are more efficient for a compiler to use
than other forms of internal storage.
 Evolutions of ISAs (cont.)
• For example, on a GPR computer, the expression
(A * B)+(B * C) – (A * D) may be evaluated by
doing the multiplications in any order, which may
be more efficient because of the location of the
operands or because of pipelining concerns.

• Nevertheless, on a stack computer the hardware

must evaluate the expression in only one order,
because operands are hidden on the stack, and it
may have to load an operand multiple times.
 Two distinctions b/w GPRs
• Two characteristics divide further the GPR
both are related to the nature of operand
used in typical ALU instruction.
1. Whether an ALU has two or three operands.
– A three operand format: Add R3, R1, B
result operands source operands

• A two operand format: Add R4, R3

result operands source operands
 Two distinctions b/w GPRs (cont.)
2. How many of the operands may be memory
addresses in ALU instructions?
– The no of memory operands supported by a
typical ALU instruction may vary from none to
three.
Comparison of three alternative GPRs
Memory Addressing
 Least & most significant bits
• Binary representation of decimal number 149

• Value of each position

MSB LSB
 Interpreting memory addresses
• How is a memory address interpreted?
– That is, what object is accessed as a function of
the address and the length?
• Access memory addr X, size 4, what object is
accessed?
• Lets illustrate it further
• Memory holds both data & instructions in a
computer system.
 Note for slide 32-35?
• Slide 32 – 35 are copied from presentation slides of
Lec5 of Yuan F. Zheng , course ECE 5362; source is
– http://www2.ece.ohio-
state.edu/~zheng/ece5362/lecture-
notes/Lecture5.pdf

– Changes made: Few sentences added,

deleted or modified
Interpreting memory addresses (cont.)
• Memory address is k bits
long
• Each addressable memory
location can hold n bits
• n can be 8 bits, 16 bits, 32
bits.
– n is called the word size
• A word is a fixed-sized piece K Number of locations
of data handled as a unit by 10 210 = 1024 = 1K
the instruction set or the 16 216= 65,536 = 64K
hardware of the processor 20 220= 1,048,576 = 1M
24 224= 16,777,216 = 16M
32 232 = 4,294,967,296 = 4096M
Interpreting memory addresses (cont.)
• Consider 32-bit long word in each location
which can store
– 32-bit integer
– 4 ASCII characters

– A machine instruction

• It is often convenient to address operands

which are as short as 1 byte
Interpreting memory addresses (cont.)
• Byte addressable machines are almost
universal
– Successive addresses refer to successive byte
locations
• There are two different conventions used for
ordering the bytes within a larger object.
– Little-endian, Big-endian,
Interpreting memory addresses (cont.)
• Lets consider a 32-bit word size i.e. each block
of memory is 32-bit long, or 4 bytes

Lowest Address Highest Address

 Little/Big Endian byte ordering

• Load/store word instruction uses a

single address e.g. store 0x12345678
at address 0x00400000
– most significant byte is 0x12; the least
significant is 0x78.

• Little-Endian: byte order puts LSB of

the data at the end i.e. memory
location with lowest address (end).

• Big-Endian: puts MSB of the data at

the end

Images source:
http://chortle.ccsu.edu
Little/Big Endian byte ordering (cont.)
• When operating within one computer, the
byte order is often unnoticeable—only
programs that access the same locations as
both, say, words and bytes, can notice the
difference.
• Byte order is a problem when exchanging data
among computers with different orderings.
 Data alignment issue
• In computers where word size is larger than
bytes, system provides word, half word, or
bytes , & even double word access support.

• CPU read/write operations are more efficient

when the data is naturally aligned. i.e.
– the address is a multiple of the data size
• Misaligned data access could require multiple
memory access
 Data alignment issue (cont.)
• If word size is 4 bytes

Image source: http://www.songho.ca/misc/alignment/dataalign.html/assemblytutorial/Chapter-

15/ass15_3.html
 Data alignment issue (cont.)
• If data stored is misaligned of 4-byte
boundary, CPU will require two access
operations to load the actual data

Image source:
http://www.songho.ca/misc/alignment/dataalign.html/assemblytutorial/Cha
 Data alignment issue (cont.)
• Supporting access at different granularity i.e.
byte, half-word, word etc. make the
implementations of ISA complicated.
– E.g. it require alignment network on CPU, or
compiler support (padding or packing)
 Key take away
• Changing Definitions of Computer Architecture
• Instruction set architecture
– Seven dimensions of ISAs
– Class of ISAs
• Operand Locations in Four ISA Classes
• Three types of GPR architecture
• Evolutions of ISAs
– Memory Addressing
• Interpreting memory addresses
• Little/Big Endian byte ordering
• Data alignment issue
 The End
• Quick source to revise this lecture at home:
– Appendix A of text book