Mr.Pradeep Kumar Y
Asst.Professor
Dept.of ECE
Contents
1. Assembly basics
2. Instruction list and description
3. Useful instructions
4. Memory mapping
5. Bit band operations and CMSIS
6. Assembly and C language Programming
1.Assembly Basics
▪ Low-level programming language for microprocessors and other
programmable devices
▪ Symbolic representation of the machine code needed to program a
given CPU architecture
▪ Each assembly language is specific to a particular computer
architecture
label
opcode operand1, operand2, ...; Comments
Instruction Destination
Easy to understand
Optional
Determine the Address of the instruction
Symbol
Assemble Constant
----- Directive
-----
MOV R1,#NVIC_IRQ0_ENABLE
;Move immediate data to register
Data Definition Directives
...
LDR R0,=HELLO_TXT ;Get the starting memory address of HELLO_TXT
BL PrintText ; Call a function called PrintText to display string
...
MY_NUMBER
DCD 0x12345678
HELLO_TXT
DCB "Hello\n",0 ; Null terminated string
Assembler Language: Use of Suffixes
Suffix Description
EQ, NE, LT, GT, and Conditional execution; EQ = Equal, NE = Not Equal, LT = Less Than,
so on GT = Greater Than, and so forth
Example:
BEQ <Label> ; Branch if equal
Unified Assembler Language
Some features
AND R0, R1 ;Traditional Thumb syntax
R0 = R0 + 1
ADDS R0, #1 ; Use 16-bit Thumb instruction by
;default for smaller size
Moving Data
Moving data between register and register
Moving data between memory and register
Moving data between special register and register
Moving an immediate data value into a register
Moving data between register and register
MOV Command to move the data between registers
MOV R8, R3
MOVN R8,R3
Moving data between memory and register
Load-Store Architecture
STR R2,[R1]
Source
LDR Rd, [Rn, #offset]
LDR R3,[R1,#4]
STR R3,[R1,#4]
Commonly Used Memory Access Instructions
Example Description
LDRB Rd, [Rn, #offset] Read byte from memory location Rn + offset
LDRH Rd, [Rn, #offset] Read half word from memory location Rn + offset
LDR Rd, [Rn, #offset] Read word from memory location Rn + offset
LDRD Rd1,Rd2, [Rn, #offset] Read double word from memory location Rn + offset
STRH Rd, [Rn, #offset] Store half word to memory location Rn + offset
STRD Rd1,Rd2, [Rn, #offset] Store double word to memory location Rn + offset
ARM processors also support memory accesses with preindexing
and postindexing
Base register
Initial memory address for the transfer
MRS
MSR
;Now R0=0x3456789A
LDR and ADR Pseudo-Instructions
Arithmetic Instruction
Logical Instruction
Shift and Rotate Instruction
Arithmetic Instruction
Bitwise AND
AND Rd, Rn ; Rd = Rd & Rn
AND.W Rd, Rn,#immed ; Rd = Rn & #immed
AND.W Rd, Rn, Rm ; Rd = Rn & Rd
Bitwise OR
ORR Rd, Rn ; Rd = Rd | Rn
ORR.W Rd, Rn,#immed ; Rd = Rn | #immed
ORR.W Rd, Rn, Rm ; Rd = Rn | Rd
Logic Operation Instructions
Bit clear
BIC Rd, Rn ; Rd = Rd & (~Rn)
BIC.W Rd, Rn,#immed ; Rd = Rn &(~#immed)
BIC.W Rd, Rn, Rm ; Rd = Rn &(~Rd)
Bitwise OR NOT
ORN.W Rd, Rn,#immed ; Rd = Rn | (~#immed)
ORN.W Rd, Rn, Rm ; Rd = Rn | (~Rd)
Logic Operation Instructions
Bitwise Exclusive OR
EOR Rd, Rn ; Rd = Rd ^ Rn
EOR.W Rd, Rn,#immed ; Rd = Rn ^ #immed
EOR.W Rd, Rn, Rm ; Rd = Rn ^ Rd
Shift and Rotate Instructions
For example,
A rotate left by 4-bit operation can be written as a rotate
right by 28-bit instruction, which gives the same result and
takes the same amount of time to execute.
Sign Extend Instructions
REV Rd, Rn
;Rd = rev(Rn) Reverse bytes in word
REV16 Rd, Rn
;Rd = rev16(Rn) Reverse bytes in each half word
REVSH Rd, Rn
; Rd = revsh(Rn) Reverse bytes in bottom
;half word and sign extend the result
Bit field processing
BFC.W Rd,#<lsb>,#<width>
;Clear bit field within a register
RBIT.W Rd, Rn
;Reverse bit order in register
Bit field processing
LSB of the value contained in the register determines the next state.
For Thumb state this bit should be set to 1.
To call a function, the branch and link instructions should be
used.
IT (IF-THEN)
Syntax
IT{x{y{z}}} cond condition switch for the
CMP R2,R3
ITTE NE ; Next 3 instructions are conditional
Example 3
CMP R0, R1 ; Compare R0 and R1
ITTEE GT ; If R0 > R1 Then if true, first 2 statements
;execute, if false, other 2 statements execute
MOVGT R2, R0 ; R2 = R0
MOVGT R3, R1 ; R3 = R1
MOVLE R2, R1 ; Else R2 = R1
MOVLE R3, R0 ; R3 = R0
CMP R1, R2
if (R1<R2) then ITTEE LT
R2=R2−R1 SUBLT.W R2,R1
R2=R2/2 LSRLT.W R2,#1
else
SUBGE.W R1,R2
R1=R1−R2
LSRGE.W R1,#1
R1=R1/2
APSR flags can be affected by the following:
• Most of the 16-bit ALU instructions
• 32-bit (Thumb-2) ALU instructions with the S suffix;
for example, ADDS.W
• Compare (e.g., CMP) and Test (e.g., TST, TEQ)
• Write to APSR/xPSR directly
ADDS.W R0, R1, R2 ; This 32-bit Thumb
;instruction updates flag
“CODE16”
Unless accessing the APSR, the MRS and MSR instructions can be used
in privileged mode only.
Note: After updating the value of the CONTROL register using MSR
instruction, it is recommended to add an ISB instruction to ensure that
the effect of the update takes place immediately
Useful Instructions In the Cortex-M3
2. IF-THEN Instruction Block
Useful Instructions In the Cortex-M3
Bit-band alias: Access to the bit-band alias will cause an access (a bit-
band operation) to the bit-band region.
(Note: A memory remapping is performed.)
Cortex-M3 Programming
Assembly language
C language
Timing-critical routines