EE6311 LIC Lab - Vidyarthiplus

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Anna University , Chennai
B.E. – ELECTRICAL AND ELECTRONICS ENGINEERING
III SEMESTER
EE6311 – Linear and Digital Integrated Circuits Laboratory
LABORATORY MANUAL
CLASS: II YEAR EEE ` SEMESTER: III

www.Vidyarthiplus.com
LIST OF EXPERIMENTS
1. APPLICATION OF OP-AMP I
2. APPLICATION OF OP-AMP II
3. APPLICATION OF 555 TIMER I
4. APPLICATION OF 555 TIMER II
5. STUDY OF BASIC GATES
6. IMPLEMENTATION OF BOOLEAN FUNCTIONS
7. IMPLEMENTATION OF ADDER AND SUBTRACTOR
8. CODE CONVERSION
9. PARITY GENERATORS AND CHECKERS
10. MULTIPLEXER AND DEMULTIPLEXER
11. ENCODER AND DECODER
12. REALISATION OF DIFFERENT FLIP-FLOPS USING LOGIC GATES
13. REALISATION OF COUNTERS
14. REALISATION OF SHIFT REGISTERS
15. FREQUENCY MULTIPLICATION USING PHASE LOCKED LOOP
16. VOLTAGE CONTROLLED OSCILLATOR USING 566
STAFF INCHARGE HOD/EEE
S. No. Date Name of the Experiment Marks Signature
1. APPLICATIONS OF OP-AMP-I
AIM:
To design an inverting amplifier, non-inverting amplifier and voltage follower for the
given specifications using Op-Amp IC 741
REFERENCE BOOKS:
1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition, Pearson

Education, 2003 / PHI. (2000).
2. D.Roy Choudhary, Sheil B.Jani, ‘Linear Integrated Circuits’, II edition, New Age, 2003.
APPARATUS REQUIRED:
Sl. No. Name of the Apparatus Range Quantity

1 Function Generator 20 MHz 1
2 CRO 30 MHz 1
3 Dual RPS 0 – 30 V 1
4 Op-Amp IC 741 1
5 Bread Board 1
6 Resistors As required
7 Connecting wires and probes As required
THEORY:
INVERTING SUMMING AMPLIFIER
Summing amplifier is a type operational amplifier circuit which can be used to sum
signals. The sum of the input signal is amplified by a certain factor and made available at the
output .Any number of input signal can be summed using an op-amp. The circuit shown is a
three input summing amplifier in the inverting mode.
In the circuit, the input signals Va, Vb, Vc are applied to the inverting input of the op-
amp through input resistors Ra, Rb, Rc. Any number of input signals can be applied to the
inverting input in the above manner. Rf is the feedback resistor. Non inverting input of the op-
amp is grounded using resistor Rm. RL is the load resistor.
NON-INVERTING SUMMING AMPLIFIER
A non inverting summing amplifier circuit with three inputs is shown above. The
voltage inputs Va, Vb and Vc are applied to non inverting input of the op-amp. Rf is the
feedback resistor. The output voltage of the circuit is governed by the equation;
Vo = (1+ (Rf/R1)) (( Va+Vb+Vc)/3)
VOLTAGE FOLLOWER
A unity gain buffer amplifier may be constructed by applying a full series negative
feedback (Fig. 2) to an op-amp simply by connecting its output to its inverting input, and
connecting the signal source to the non-inverting input (Fig. 3). In this configuration, the entire
output voltage (β = 1 in Fig. 2) is placed contrary and in series with the input voltage. Thus the
two voltages are subtracted according to Kirchhoff's voltage law (KVL) and their difference is
applied to the op-amp differential input. This connection forces the op-amp to adjust its output
voltage simply equal to the input voltage (Vout follows Vin so the circuit is named op-amp
voltage follower).
PRECAUTIONS:
Output voltage will be saturated if it exceeds ± 15V.
PROCEDURE:
1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriate input voltage is applied to the non - inverting input terminal of the Op-
Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
PIN DIAGRAM:
CIRCUIT DIAGRAM:
Inverting Summing Amplifier
DESIGN:
If resistor Ra, Rb, Rc has same value ie; Ra=Rb=Rc=R

We know for an inverting Amplifier, ACL = RF / R
Vo = - (Rf/R) x (Va + Vb +Vc)
If the values of Rf and R are made equal, then the equation becomes,
Vo = - (Va + Vb +Vc)
Rm = Ra || Rb || Rc || Rf
OBSERVATIONS:
Sl. No. Va in Volt Vb in Volt Vc in Volt Vo in Volt
CIRCUIT DIAGRAM:
Non-Inverting summing Amplifier
DESIGN:
Assume R1=R2=R3=Rf/2=R
We know for a Non-inverting Summing Amplifier
Vo = (1+ (Rf/R1)) (( Va+Vb+Vc)/3)
V0= (V1+V2+V3)
OBSERVATIONS:
Sl. No. Va in Volt Vb in Volt Vc in Volt Vo in Volt
CIRCUIT DIAGRAM:
Voltage Follower
Model Graph:
RESULT:
The design and testing of the Inverting, Non-inverting amplifier and Voltage Follower is
done and the input and output waveforms were drawn.
2. APPLICATIONS OF OP-AMP-II
(Differentiator and Integrator)
AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC 741
REFERENCE BOOKS:

APPARATUS REQUIRED:
S. No Name ofthe Apparatus Range Quantity

1. AFO 20 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Timer IC IC 555 1
5. Bread Board 1
6. Resistors
7. Capacitors
8. Connecting wires and probes As required
THEORY:
Differentiator
The differentiator circuit performs the mathematical operation of differentiation; that

is, the output waveform is the derivative of the input waveform. The differentiator may be
constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor
C1. The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt)
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input
terminal of the op-amp to compensate for the input bias current. A workable differentiator
can be designed by implementing the following steps:
1. Select fa equal to the highest frequency of the input signal to be differentiated. Then,
assuming a value of C1 <1 µF, calculate the value of Rf.
2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.
3. The differentiator is most commonly used in wave shaping circuits to detect high
frequency components in an input signal and also as a rate–of–change detector in FM
modulators.
CIRCUIT DIAGRAM :
(Differentiator)
DESIGN:
Given: fa = ---------------
We know the frequency at which the gain is 0 dB, fa =1 /(2π Rf C1)
Let us assume C1 = 0.1 µF; then
Rf =
Since fb = 10 fa, fb = ---------------
We know that the gain limiting frequency fb = 1 / (2π R1 C1)
Hence R1 =
Also since R1C1 = Rf Cf ;
Cf =
OBSERVATIONS:
Amplitude
Sl. No. Waveforms
in Volt
1 Input Waveform
2 Output Waveform
CIRCUIT DIAGRAM :
(Integrator)
DESIGN:
We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf )
Therefore Rf =
Since fb = 10 fa, and also the gain limiting frequency

fb =1 / (2π R1Cf)
We get, R1 =
OBSERVATIONS:
Amplitude
Sl. No. Waveforms Time Period in ms
in Volt
1 Input Waveform
2 Output Waveform
Pin diagram:
THEORY:
Integrator
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the
output voltage is given as,
Vo = - (1/Rf C1) ∫Vi dt

Here the negative sign indicates input signal. Normally between fa and fb < fb . The
input signal will be integrated or equal to Rf Cf. That is,
that the output voltage is 180 0 out of phase with the the circuit acts as an integrator.
Generally, the value of fa properly if the Time period T of the signal is larger than
T ≥Rf Cf
The integrator is most commonly used in analog computers and ADC and signal-
wave shaping circuits.
PROCEDURE:

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriate input voltage is applied to the inverting input terminal of the Op-Amp.
The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.
MODEL GRAPH:
DISCUSS QUESTIONS:
1. What is integrator?
2. Write the disadvantages of ideal integrator?
3. Write the application ofintegrator?
4. Why compensation resistance is needed inintegrator and how will you findit values?
5. What is differentiator?
6. Write the disadvantages of ideal differentiator.
7. Write the application of differentiator?
8. Why compensation resistance is needed in differentiator and how will you findit
values?
Why integrators are preferred over differentiators in analog comparators?
MODEL GRAPH:
Comparator
OBSERVATIONS:
Amplitude
in Volt
1 Input Waveform
2 Output Waveform
RESULT:
The design of the Integrator, Differentiator and Voltage Follower circuit was done and
the input and output waveforms were obtained.
3. TIMER APPLICATION ASTABLE MULTIVIBRATOR
AIM:
To design an astable multivibrator circuit for the given specifications using 555 Timer
IC.
REFERENCE BOOKS:

APPARATUS REQUIRED:
Sl. No. Name of the Apparatus Range Quantity
1 CRO 30 MHz 1
2 Dual RPS 0 – 30 V 1
3 Timer IC IC 555 1
4 Bread Board 1
5 Connecting wires and probes As required
THEORY:
An astable multivibrator, often called a free-running multivibrator, is a rectangular-

wave-generating circuit. This circuit does not require an external trigger to change the state of
the output. The time during which the output is either high or low is determined by two
resistors and a capacitor, which are connected externally to the 555 timer. The time during
which the capacitor charges from 1/3 Vcc to 2/3Vcc is equal to the time the output is high
and is given by,
tc = 0.69 (R1 +R2) C
Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is
equal to the time the output islow and is given by,
td = 0.69 (R2) C
Thus the total time periodof the output waveform is,
T = tc + td = 0.69 (R1 +2 R2) C
The term duty cycle is often used in conjunction with the astable multivibrator. The
duty cycle is the ratio of the time tc during which the output is high to the total time period
T. It is generally expressed in percentage. In equation form,
% duty cycle =[(R1 +R2) /(R1 + 2 R2)] x 100
PIN DIAGRAM:
CIRCUIT DIAGRAM:
DESIGN:
Given f= 4 KHz,
Therefore, Total time period, T = 1/f =
We know, duty cycle = tc /T
Therefore, tc =______ and td = _________
We also know for an astable multivibrator td = 0.69 (R2) C
Therefore, R2 =
tc = 0.69 (R1 + R2) C Therefore, R1 =

OBSERVATIONS:
Amplitude
in Volt
1 Output Waveform
2 Capacitor voltage
PROCEDURE:

2. + 5V supply is given to the + Vcc terminal of the timer IC.
3. At pin 3the output waveform is observed with the help of a CRO
4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage
DISCUSSION QUESTIONS:
1. Define Offset voltage.

2. Define duty cycle.
3. Mention the applications of IC555.
4. Give the methods for obtaining symmetrical square wave.
5. What is the other name for monostable multivibrator?
6. Explain the operation of IC555 in astable mode..
7. Why negative pulse is used as trigger?
RESULT:
The design of the Astable multivibrator circuit was done and the output voltage and
capacitor voltage waveforms were obtained.
4. TIMER APPLICATION MONOSTABLE MULTIVIBRATOR
AIM:
To designamonostable multivibrator circuit for the given specifications using 555

Timer IC.
REFERENCE BOOKS:
1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition,

Pearson Education, 2003 / PHI. (2000).
2. D.Roy Choudhary, Sheil B.Jani, ‘Linear Integrated Circuits’, II edition, New Age,
2003.
APPARATUS REQUIRED:
Sl. No Name of the Apparatus Range Quantity

1. AFO 20 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Timer IC IC 555 1
5. Bread Board 1
THEORY:
A monostable multivibrator often called a one-shot multivibrator is a pulse
generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand-by state the output of the circuit
is approximately zero or at logic low level. When an external trigger pulse is applied, the
output is forced to go high (approx. Vcc). The time during which the output remains highis
given by,
tp = 1.1 R1 C
At the end of the timing interval, the output automatically reverts back to its logic
low state. The output stays low until a trigger pulse is applied again. Then the cycle
repeats. Thus the monostable state has only one stable state hence the name monostable.
PROCEDURE:
2. + 5V supply is given to the + Vcc terminal of the timer IC.
3. A negative trigger pulse ofless than (1/3 VCC) i.e Groundto pin 2 ofthe 555 IC
4. At pin 3the output time period is observed with the help of a LED or CRO
5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage
CIRCUIT DIAGRAM:
DESIGN:
Consider VCC = 5V, for given tp Output pulse width tp = 1.1 RA C

Assume C in the order of microfarads & Find RA
Typical values:
If C=0.1 µF , RA = 10k then tp = 1.1 mSec Trigger Voltage =4 V
PIN DIAGRAM:
OBSERVATIONS:
Time Period
Sl. No. Value of R1 Value of C
Theoritical Practicle
MODEL GRAPH:
1. Explain the operation of IC555 in monostable mode.

2. What is the charging time for capacitor in monostable mode?
3. What are the modes of operation of 555timers?
4. Give the comparison between combinational circuits and sequential circuits.
5. What do you mean by present state?
6. Give the applications of 555 timers IC.
RESULT:
The design of the Monostable multivibrator circuit was done and the input and output waveforms
were obtained.
5. a. STUDY OF BASIC GATES
AIM:
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
THEORY:
AND gate:
An AND gate is the physical realization of logical multiplication operation. It is an

electronic circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’.
OR gate:
An OR gate is the physical realization of the logical addition operation. It is an electronic

circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.
NOT gate:
A NOT gate is the physical realization of the complementation operation. It is an

electronic circuit which generates an output signal which is the reverse of the input signal. A
NOT gate is also known as an inverter because it inverts the input.
NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate will
be ‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.
NOR gate:
A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’
if all the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.
EX-OR gate:
An Ex-OR gate performs the following Boolean function,
A B = ( A . B’ ) + ( A’ . B )
It is similar to OR gate but excludes the combination of both A and B being

equal to one. The exclusive OR is a function that give an output signal ‘0’ when the two
input signals are equal either ‘0’ or ‘1’.
PROCEDURE:
1. Connections are given as per the circuit diagram

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for all gates.
AND GATE OR GATE
LOGIC DIAGRAM: LOGIC DIAGRAM:
PIN DIAGRAM OF IC
7432 :
PIN DIAGRAM OF IC 7408 :
CIRCUIT DIAGRAM:
CIRCUIT
DIAGRAM:
TRUTH TABLE: TRUTH TABLE:

OUTPU
Sl. INPUT OUTPUT Sl. INPUT T
Y=A+
No A B Y=A.B No A B B
1. 0 0 0 1. 0 0 0
2. 0 1 0 2. 0 1 1
3. 1 0 0 3. 1 0 1
4. 1 1 1 4. 1 1 1
NOR GATE EX-OR GATE
LOGIC DIAGRAM: LOGIC DIAGRAM
PIN DIAGRAM OF IC 7402 : PIN DIAGRAM OF IC 7486 :
CIRCUIT DIAGRAM: CIRCUIT DIAGRAM:
TRUTH TRUTH
TABLE: TABLE:
INPUT OUTPUT INPUT OUTPUT

Sl.No Sl.No
A B Y = (A + B)’ A B Y=A B
1. 0 0 1 1. 0 0 0
2. 0 1 0 2. 0 1 1
3. 1 0 0 3. 1 0 1
4. 1 1 0 4. 1 1 0
RESULT:
The truth tables of all the basic digital ICs were verified.
5. b. IMPLEMENTATION OF BOOLEAN FUNCTIONS
AIM:
To design the logic circuit and verify the truth table of the given Boolean
expression, F (A, B, C, D) = Σ (0, 1, 2, 5, 8, 9, 10)
REFERENCE BOOKS:
2007
APPARATUS REQUIRED:

5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
PROCEDURE:
1. Connections are given as per the circuit diagram

3. Apply the inputs and verify the truth table for the given Boolean expression.
CIRCUIT DIAGRAM:
DESIGN:
Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)
TRUTH TABLE:
INPUT OUTPUT
S. No.
A B C D F=D’B’+C’(B’+A’D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 0
The output function F has four input variables hence a four variable Karnaugh Map is used to
obtain a simplified expression for the output as shown,
From the K-Map,

F = B’ C’ + D’ B’ + A’ C’ D
Since we are using only two input logic gates the above expression can be re-
written as, F = C’ (B’ + A’ D) + D’ B’
Now the logic circuit for the above equation can be drawn.
RESULT:
The truth table of the given Boolean expression was verified.
6. IMPLEMENTATION OF ADDER AND SUBTRACTOR

a. HALF ADDER AND FULL ADDER
AIM:
To design and verify the truth table of the Half Adder & Full Adder circuits.
REFERENCE BOOKS:
2007
APPARATUS REQUIRED:
S. No. Name of the Apparatus Range Quantity

THEORY:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0+0=0
0+1=1
1+0=1
1 + 1 = 102
The first three operations produce a sum of whose length is one digit, but when the last operation
is performed the sum is two digits. The higher significant bit of this result is called a carry and
lower significant bit is called the sum.
HALF ADDER:
A combinational circuit which performs the addition of two bits is called half adder. The input
variables designate the augend and the addend bit, whereas the output variables produce the sum
and carry bits.
FULL ADDER:
A combinational circuit which performs the arithmetic sum of three input bits is called full
adder. The three input bits include two significant bits and a previous carry bit. A full adder
circuit can be implemented with two half adders and one OR gate.
From the truth table the expression for sum and carry bits of the output can be obtained as,
SUM = A’B’C + A’BC’ + AB’C’ + ABC

CARRY = A’BC + AB’C + ABC’ +ABC
HALF ADDER
TRUTH TABLE:
Input Output
Sl.n
o
A B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1
From the truth table the expression for sum and carry bits of the output can be
obtained as, Sum, S = A B
Carry, C = A . B
CIRCUIT DIAGRAM:
FULL ADDER
TRUTH TABLE:
Sl.n Input Output

o
A B C Sum Carry
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
SUM
SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C
CARRY
CARRY = AB + AC + BC
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connections are given as per the circuit diagrams.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
RESULT:
The design of the half adder and full adder circuits was done and their truth tables were
verified.
b. HALF SUBTRACTOR AND FULL SUBTRACTOR
AIM:
To design and verify the truth table of the Half Subtractor & Full Subtractor
circuits.
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd

edition, 2007
APPARATUS REQUIRED:

THEORY:
The arithmetic operation, subtraction of two binary digits has four possible
elementary operations, namely,
0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0
In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the
second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.
HALF SUBTRACTOR:
A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and the subtrahend bit, whereas the
output variables produce the difference and borrow bits.
FULL SUBTRACTOR:
A combinational circuit which performs the subtraction of three input bits is called
full subtractor. The three input bits include two significant bits and a previous borrow bit.
A full subtractor circuit can be implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be
obtained as,
Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABC

Borrow, BORR = A’BC + AB’C + ABC’ +ABC
HALF SUBTRACTOR
TRUTH TABLE:
Input Output
S.no
A B Diff Borr
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be
obtained as,
Difference, DIFF = A B
Borrow, BORR = A’. B
CIRCUIT DIAGRAM:
2. FULL SUBTRACTOR
TRUTH TABLE:
Inpu
t Output
S.no
A B C Diff Borr
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
Using Karnaugh maps the reduced expression for the output bits can be
obtained as,
DIFFERENCE
DIFF = A’B’C + A’BC’ + AB’C’ + ABC = A B

C
BORROW
BORR = A’B + A’C + BC
CIRCUIT DIAGRAM:
PROCEDURE:

3. Apply the inputs and verify the truth table for the half subtractor and full subtractor
circuits.
1. What is combinational circuit?

2. What is different between combinational and sequential circuit?
3. What are the gates involved for binary adder?
4. List the properties of Ex-Nor gate?
5. What is expression for sum and carry?
RESULT:
The design of the half subtractor and full subtractor circuits was done and their truth
tables were verified.
7. a. CODE CONVERSION
AIM:
To design, construct and study the performance of different code converters.
REFERENCE BOOKS:
2007.
APPARATUS REQUIRED:

2. EX-OR gate IC 7486
THEORY:
The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
between the two systems if each uses different codes for same information. Thus, code converter
is a circuit that makes the two systems compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four bits
to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted
code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines must
supply the bit combination of elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents one of the four
outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each of
three outputs.
DESIGN:
TRUTH TABLE:
4-bit binary 4-bit gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
From the truth table the expression for the output gray bits are,
G3 (B3, B2, B1, B0) = Σ (8, 9, 10, 11, 12, 13, 14, 15)
G2 (B3, B2, B1, B0) = Σ (4, 5, 6, 7, 8, 9, 10, 11)
G1 (B3, B2, B1, B0) = Σ (2, 3, 4, 5, 9, 10, 11, 12, 13)
G0 (B3, B2, B1, B0) = Σ (1, 2, 5, 6, 9, 10, 13. 14)
Hence obtain the reduced SOP expression using Karnaugh maps as follows,
K-Map for G3: K-Map for G2:
G3 = B3
K-Map for G1: K-Map for G0:
CIRCUIT DIAGRAM:
4- BIT BINARY TO GRAY CODE CONVERTER
PROCEDURE:

3. Apply the inputs and verify the truth table for the three bit binary to gray code
converter.
1. List the procedures to convert gray code into binary?

2. Why weighted code is called as reflective codes?
3. What is a sequential code?
4. What is error deducting code?
5. What is ASCII code?
RESULT:
The design of the 4-bit Binary to Gray code converter circuit was done and its truth table was
verified.
7. b. PARITY GENERATORS AND CHECKERS
AIM:
To implement the odd and even parity checkers using the logic gates and also to generate
the odd parity and even parity numbers using the generators.
REFERENCE BOOKS:
2007.
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006.
APPARATUS
REQUIRED:
Sl.No Component Type Quantity

1 Trainer Kit - 1
2 EX-OR IC7486 1
3 NOT gate IC 7404 1
4 Connecting wires - Required
THEORY:
Parity checking is used for error detection in data transmission.
Odd parity checkers:
It counts the number of 1’s in the given input and produces a 1 in the output when the
number of 1’s is odd.
Even parity checker:
It counts the number of 1’s in the given input and produces a 1 in the output when the
number of 1’s is even.
Odd parity generators:
It generates an odd parity number. The odd parity checker circuit is used with the
inverted output and also the input bits. So when the input is a 4-bit number then the output of the
generator circuit will have 5 bits which is an odd parity number.
Even parity generator:
It generates an even parity number. The even parity checker circuit is used with the
inverted output and also the input bits. So when the input is a 4-bit number then the output of the
generator circuit will have 5 bits which is an even parity number.
PROCEDURE:
1. The circuit is implemented using logic gates.

2. The inputs are given as per the truth table.
3. The corresponding outputs are noted.
4. The theoretical and practical values were verified.
TRUTH TABLE:
Input Checker output Generator output

A B C D odd even odd even
0 0 0 0 0 1 00001 00000
0 0 0 1 1 0 00010 00011
0 0 1 0 1 0 00100 00101
0 0 1 1 0 1 00111 00110
0 1 0 0 1 0 01000 01001
0 1 0 1 0 1 01011 01010
0 1 1 0 0 1 01101 01100
0 1 1 1 1 0 01110 01111
1 0 0 0 1 0 10000 10001
1 0 0 1 0 1 10011 10010
1 0 1 0 0 1 10101 10100
1 0 1 1 1 0 10110 10111
1 1 0 0 0 1 11001 11000
1 1 0 1 1 0 11010 11011
1 1 1 0 1 0 11100 11101
1 1 1 1 0 1 11111 11110
1. What is parity bit?

2. Why parity bit is added to message?
3. What is parity checker?
4. What is odd parity and even parity?
5. What are the gates involved for parity generator?
RESULT:
The odd and even parity checkers are implemented using the logic gates and the odd
parity and even parity numbers are generated using the corresponding generators.
8. a. MULTIPLEXERAND DEMULTIPLEXER
AIM:
To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.
REFERENCE BOOKS:
2007
APPARATUS REQUIRED:

4. AND gate ( three input ) IC 7411 1
THEORY:
Multiplexing means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of
particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines
and n selection lines whose bit combinations determines which input is selected.
A multiplexer is called a data selector, since it selects one of many inputs and steers the binary
information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead
can be selected. This feature is very useful where data might be changing the same time
DATA SELECT leads change. It is a very useful Medium Scale Integration (MSI) function
and has a multitude of applications. It is used for connecting two or more sources to a single
destination among the computer units and itis useful for constructing acommon bus system.
A decoder with an enable input can function as a demultiplexer. A Demultiplexer is a

circuit that receives information on a single line and transmits this information on one of 2n
possible output lines. The selection of specific output line is controlled by the bit values of n
selection lines. The decoder and demultiplexer operations are obtained from the same circuit; a
decoder with an enable input is referred to as a decoder / de-multiplexer. The Strobe lead can
be used to active or de-active the entire IC, allowing time for the address lines to change the
informationis fed to the output. Demultiplexers are useful anytime information from one
source must be fed several places.
4 X 1 MULTIPLEXER
LOGIC SYMBOL:
TRUTH TABLE:
Selection input Output

S.no
S1 S2 Y
1. 0 0 I0
2. 0 1 I1
3. 1 0 I2
4. 1 1 I3
PIN DIAGRAM OF IC 7411:
CIRCUIT DIAGRAM:
1X4 DEMULTIPLEXER
LOGIC SYMBOL: TRUTH TABLE:
Input Output
S.no
S1 S2 Din Y0 Y1 Y2 Y3
1. 0 0 0 0 0 0 0
2. 0 0 1 1 0 0 0
3. 0 1 0 0 0 0 0
4. 0 1 1 0 1 0 0
5. 1 0 0 0 0 0 0
6. 1 0 1 0 0 1 0
7. 1 1 0 0 0 0 0
8. 1 1 1 0 0 0 1
CIRCUIT DIAGRAM:
1. What is multiplexer?
2. What are the applications of multiplexer?
3. What is the difference between multiplexer & demultiplexer?
RESULT:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their
truth tables were verified.
8. b. ENCODER AND DECODER
AIM:
To study the operation of Encoder and Decoder circuits using logic gates
REFERENCE BOOKS:

Education, 2003 / PHI. (2000)
APPARATUS REQUIRED:

1. Digital IC trainer 1
2. NOT Gate IC 7404 1
3. OR Gate IC 7432 1
4. AND Gate IC7408 1
5. Bread Board 1
6. NOT Gate IC7404 1
THEORY:
DECODER
In digital electronics, a decoder can take the form of a multiple-input, multiple-output

logic circuit that converts coded inputs into coded outputs, where the input and output codes are
different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications
such as data multiplexing, 7 segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate
is "High" (1) only when all its inputs are "High." Such output is called as "active High output".
If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all
its inputs are "High". Such output is called as "active low output".
A slightly more complex decoder would be the n-to-2n type binary decoders. These types
of decoders are combinational circuits that convert binary information from 'n' coded inputs to a
maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-
16 decoder are other examples.
The input to a decoder is parallel binary number and it is used to detect the presence of a
particular binary number at the input. The output indicates presence or absence of specific
number at the decoder input.
OBSERVATIONS:
Inputs Outputs
A B Y3 Y2 Y1 Yo
B
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
OBSERVATIONS:
Input Output
D7 D6 D5 D4 D3 D2 D1 D0 A B C
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
ENCODER
An encoder is a device, circuit, transducer, software program, algorithm or person that
converts information from one format or code to another. The purpose of encoder is
standardization, speed, secrecy, security, or saving space by shrinking size. Encoders are
combinational logic circuits and they are exactly opposite of decoders. They accept one or more
inputs and generate a multibit output code.
Encoders perform exactly reverse operation than decoder. An encoder has M input and N output
lines. Out of M input lines only one is activated at a time and produces equivalent code on
output N lines. If a device output code has fewer bits than the input code has, the device is
usually called an encoder
PROCEDURE:
1. Make the circuit connections as shown in the figure.

2. Check the corresponding truth table.
RESULT:
The design of the Encoder and Decoder circuit was done and the input and output were
obtained
9. REALISATION OF DIFFERENT FLIP-FLOPS USING LOGIC GATES
AIM:
To verify the characteristic table of RS, D, JK, and T Flip flops.
REFERENCE BOOKS:
2007
APPARATUS REQUIRED:

2. NOR gate IC 7402
3. NOT gate IC 7404
4. AND gate ( three input ) IC 7410
5. NAND gate IC 7400
THEORY:
A Flip Flop is a sequential device that samples its input signals and changes its output
states only at times determined by clocking signal. Flip Flops may vary in the number of inputs
they possess and the manner in which the inputs affect the binary states.
RS FLIP FLOP:
The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset
when the R input high and S input is low. The Flip Flop is set when the S input is high and R
input is low. When both the inputs are high the output is in an indeterminate state.
D FLIP FLOP:
To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the
same time. This is obtained by making the two inputs complement of each other.
Circuit Diagram:
SR FLIP – FLOP:
S
7400
Q
7400
CLK
7400 Q
7400
R
JK FLIP – FLOP:
J 7411
7400 Q
CLK
7400 Q
7411
K
D FLIP FLOP:
D
7400
Q
7400
CLK
7400 Q
7400
T FLIP FLOP:
7408 7400
7400
T CLK
7400
7408 7400
RS Flip -Flop
Clock Input Present Next

Pulse S R State (Q) State(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 X
8 1 1 1 X
JK Flip -Flop

Pulse J K State (Q) State(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 0
D Flip -Flop
Pulse D State (Q) State(Q+1)

1 0 0 0
2 0 1 0
3 1 0 1
4 1 1 1
T Flip -Flop
Pulse T State (Q) State(Q+1)

1 0 0 0
2 0 1 0
3 1 0 1
4 1 1 T
JK FLIP FLOP:
The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs
behave like S and R inputs to set and reset the Flip Flop. The output Q is NAND with K input
and the clock pulse, similarly the output Q’ is NAND with J input and the Clock pulse. When
the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their
previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When
both the inputs are high the output toggles continuously. This is called Race around condition
and this must be avoided.
T FLIP FLOP:
This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs
together. T Flip Flop is also called Toggle Flip Flop.
RESULT:
The Characteristic tables of RS, D, JK, T flip flops were verified.
10. REALISATION OF SHIFT REGISTERS
AIM:
To implement and verify the truth table of a serial in serial out and
parallel in parallel out shift
register.
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education

2nd edition, 2007
APPARATUS REQUIRED:
S. No. Name of the Apparatus Range Quantity

2. D Flip Flop IC 7474 2
3. AND Gate IC 7408 1
4. NOT Gate IC7404 1
4. OR Gate IC 7432 1
THEORY:
A register capable of shifting its binary information either to the left or to

the right is called a shift register. The logical configuration of a shift register
consists of a chain of flip flops connected in cascade with the output of one flip
flop connected to the input of the next flip flop. All the flip flops receive a
common clock pulse which causes the shift from one stage to the next.
The Q output of a D flip flop is connected to the D input of the flip flop to
the left. Each clock pulse shifts the contents of the register one bit position to the
right. The serial input determines, what goes into the right most flip flop during
the shift. The serial output is taken from the output of the left most flip flop prior
to the application of a pulse. Although this register shifts its contents to its left, if
we turn the page upside down we find that the register shifts its contents to the
right. Thus a unidirectional shift register can function either as a shift right or a
shift left register.
CIRCUIT DIAGRAM:
Serial in – Serial out Shift Register:
Q4
D1
D Q D Q D Q D Q
1 7 1 2 7 2 3 7 3 4 7 4
cp1 74 cp2 74 cp3 74 cp4 74

4 4 4 4
Clock pulse
Parallel in - Serial out Shift Register
D D
D4 740 3 D2 1
4
Load/
shift
74 740
08 7408 8
74
32 7432 7432
O/
P
D Q D Q D Q D 7
1 7 1 2 7 2 3 7 3 4 Q4
cp cp cp cp
1 74 2 74 3 74 4 74
4 4 4 4
Clock pulse
PIN DIAGRAM OF IC 7474:
TRUTH TABLE:
For a serial data input of 1101,
Clock Inputs Outputs

S.no
Pulse D1 D2 D3 D4 Q1 Q2 Q3 Q4
1 1 1 X X X 1 X X X
2 2 1 1 X X 1 1 X X
3 3 0 1 1 X 0 1 1 X
4 4 1 0 1 1 1 0 1 1
5 5 X 1 0 1 X 1 0 1
6 6 X X 1 0 1 X 1 0
7 7 X X X 1 0 X X 1
8 8 X X X X X X X X
For a Parallel data input of 1101,
Clock Inputs Outputs

S.no
Pulse D1 D2 D3 D4 Q4
1 1 1 1 0 0 1
2 2 1 1 0 0 1
3 3 1 1 0 0 0
4 4 1 1 0 0 1
PROCEDURE:

2. Apply the input and verify the truth table of the counter.
RESULT:
The truth table of a serial in serial out left shiftregister was hence verified.
11. a. FREQUENCY MULTIPLICATION USING PHASE

LOCKED LOOP
AIM
To perform the frequency multiplication using phase locked loop (NE

565) and to draw the output wave form
REFERENCE BOOKS:
1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’,

IV edition, Pearson Education, 2003 / PHI. (2000)
2. D.Roy Choudhary, Sheil B.Jani, ‘Linear Integrated Circuits’, II
edition, New Age, 2003.
APPARATUS REQUIRED:

1. Digital IC trainer
2. PLL NE565 1
3. Decade Counter IC 7490 1
4. Resistor 2K, 4.7K,10K 3
5. Capacitor 0.001µF, 0.01µF, 10µF 3
6. Signal Generator 1
7. POT 20K 1
8. RPS (0-30V) 1
THERORY
To use PLL as a multiplier make connections as shown in fig the circuit

uses and bit binary counter 7490 used as a divide by 5 circuit. Set the lip signal at 1
Vpp square wave at 500 HZ vary the VCO frequency by adjusting the by adjusting
the 20k potentiometer till the PLL is locked Measure the output frequency it
should be 5 times the input frequency repeat steps for input frequency of 1 KHZ
Fo=1.2/4R1 C1
PROCEDURE
1. The connections are made as shown in figure

2. we get a output frequency which is in five times of inputs frequency
then plot the graph
CIRCUIT DIAGRAM:
OBSERVATIONS:
S. No. Input Frequency Output Frequency
MODEL GRAPH:
Input
Vin
Time (ms)
Output
Vo
Time (ms)
RESULT
Thus the frequency multiplication using phase locked loop was done and the
output wave forms were drawn.
CIRCUIT DIAGRAM:
+15V
10 KΏ
8 6
2K
Ώ
4
5
20 3
KΏ
NE566
7 1
0.01µF
The frequency of the output waveforms is approximated by Fo=2(VCC-VC )/ CT RT VCC
INTERNAL DIAGRAM:
11. b. VOLTAGE CONTROLLED OSCILLATOR USING NE 566
AIM:
To obtain square wave and triangular wave using voltage controlled oscillator
REFERENCE BOOKS:
Education, 2003 / PHI. (2000)
APPARATUS REQUIRED:
1. Digital IC trainer 1
2. VCO NE566 1
4. Resistor 2K, 10K 2
5. Capacitor 0.01µF 1
7. POT 20K 1
THEORY:
In most cases, the frequency of an oscillator is determined by the time constant RC.
However, in cases or applications such as FM, tone generators, and frequency-shift keying
(FSK), the frequency is to be controlled by means of an input voltage, called the control voltage.
This can be achieved in a voltage-controlled oscillator (VCO). A VCO is a circuit that provides
an oscillating output signal (typically of square-wave or triangular waveform) whose
frequency can be adjusted over a range by a dc voltage. An example of a VCO is the 566 IC
unit, that provides simultaneously the square-wave and triangular-wave outputs as a function of
input voltage. The frequency of oscillation is set by an external resistor R1 and a capacitor C1
and the voltage Vc applied to the control terminals. Figure shows that the 566 IC unit contains
current sources to charge and discharge an external capacitor Cv at a rate set by an external
resistor R1 and the modulating dc input voltage. A Schmitt trigger circuit is employed to switch
the current sources between charging and discharging the capacitor, and the triangular voltage
produced across the capacitor and square-wave from the Schmitt trigger are provided as outputs
through buffer amplifiers. Both the output waveforms are buffered so that the output impedance
of each is 50 f2. The typical magnitude of the triangular wave and the square wave are
2.4 V peak.to-peak and 5.4 Vpeak.to.peak.
PROCEDURE:
1. Connections are made as shown in diagram.

2. The square and triangular wave is obtained in terminal 3&4 respectively.
3. The Modulating Input at Pin 5 Is Changed by varying rheostat the voltage at
pin 5 and corresponding frequency at output are noted and characteristics were
drawn
RESULT:
Thus the voltage controlled oscillator using NE566 was done and the output was verified.

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Anna University , Chennai

B.E. – ELECTRICAL AND ELECTRONICS ENGINEERING

EE6311 – Linear and Digital Integrated Circuits Laboratory

CLASS: II YEAR EEE ` SEMESTER: III

3. APPLICATION OF 555 TIMER I

4. APPLICATION OF 555 TIMER II

5. STUDY OF BASIC GATES

6. IMPLEMENTATION OF BOOLEAN FUNCTIONS

7. IMPLEMENTATION OF ADDER AND SUBTRACTOR

9. PARITY GENERATORS AND CHECKERS

10. MULTIPLEXER AND DEMULTIPLEXER

11. ENCODER AND DECODER

12. REALISATION OF DIFFERENT FLIP-FLOPS USING LOGIC GATES

13. REALISATION OF COUNTERS

14. REALISATION OF SHIFT REGISTERS

15. FREQUENCY MULTIPLICATION USING PHASE LOCKED LOOP

16. VOLTAGE CONTROLLED OSCILLATOR USING 566

STAFF INCHARGE HOD/EEE

S. No. Date Name of the Experiment Marks Signature

1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition, Pearson

Sl. No. Name of the Apparatus Range Quantity

7 Connecting wires and probes As required

INVERTING SUMMING AMPLIFIER

NON-INVERTING SUMMING AMPLIFIER

Vo = (1+ (Rf/R1)) (( Va+Vb+Vc)/3)

1. Connections are given as per the circuit diagram.

Inverting Summing Amplifier

If resistor Ra, Rb, Rc has same value ie; Ra=Rb=Rc=R

Sl. No. Va in Volt Vb in Volt Vc in Volt Vo in Volt

Non-Inverting summing Amplifier

Sl. No. Va in Volt Vb in Volt Vc in Volt Vo in Volt

1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition, Pearson

S. No Name ofthe Apparatus Range Quantity

The differentiator circuit performs the mathematical operation of differentiation; that

We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf )

Since fb = 10 fa, and also the gain limiting frequency

Vo = - (1/Rf C1) ∫Vi dt

1. Connections are given as per the circuit diagram.

3. TIMER APPLICATION ASTABLE MULTIVIBRATOR

1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition, Pearson

Sl. No. Name of the Apparatus Range Quantity

An astable multivibrator, often called a free-running multivibrator, is a rectangular-

Therefore, Total time period, T = 1/f =

We know, duty cycle = tc /T

Therefore, tc =______ and td = _________

We also know for an astable multivibrator td = 0.69 (R2) C

tc = 0.69 (R1 + R2) C Therefore, R1 =

1. Connections are given as per the circuit diagram.

1. Define Offset voltage.

4. TIMER APPLICATION MONOSTABLE MULTIVIBRATOR

To designamonostable multivibrator circuit for the given specifications using 555

1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition,

Sl. No Name of the Apparatus Range Quantity

Consider VCC = 5V, for given tp Output pulse width tp = 1.1 RA C

If C=0.1 µF , RA = 10k then tp = 1.1 mSec Trigger Voltage =4 V

1. Explain the operation of IC555 in monostable mode.

5. a. STUDY OF BASIC GATES

S.No Name of the Apparatus Range Quantity

An AND gate is the physical realization of logical multiplication operation. It is an

An OR gate is the physical realization of the logical addition operation. It is an electronic

A NOT gate is the physical realization of the complementation operation. It is an

An Ex-OR gate performs the following Boolean function,

It is similar to OR gate but excludes the combination of both A and B being

Therefore, tc = and td = ___