Schematic Verification Report

Project Information Verification Information

Items Details # Item

Project Name ASRS_03_Step16 1 Schematics Name:ASRS_03_Step16
Author Devender Nath Maurya 2 Board Name:ASRS_03_Step16
Last saved 02/09/19 12:03 PM 3 Provided by:
Project Manager Devender Nath Maurya 4 Received Date
Signed by 5 Verified by :Sandeep kumar

# Items Details Remark

1 Check ERC No errors found ok
2 Check Hierarchy No errors found ok
3 Net Classes ok ok
Default(must be 0)
4 Header information NA NA
5 I2C (pull-ups and properly connected to all I2C ports Both I2C Pulled with 10k ok
(devices).
6 SPI (Master/Slave/individual slave selects for each device) ok ok
7 UART connections. ok ok
8 Use functional names in nets/buses ok ok
9 Shield connections for USB/RJ45 and any other connector NA NA
10 Ethernet phy leds @3V3 NC NC
11 Boot options ok
12 NTC{3K01(horticulture) or 50K(In building)} used? NA NA
13 Datasheets ckt suggestion considered ok ok
14 Leds Info Single Led for Power ok
15 Switches Info Only RST switch no use switch ok
16 Miscellaneous NA NA
17 “RefDes By Hierarchy” in BOM ok ok
18 Biasing resistors of variable voltage LDO/convertor ok ok
19 Add 10uF or big cap at ldo output for secure ok ok
20 BOM analysis Caps footprint and voltage ok
availability

Project Specific Design Check points

# Items Details Remark

1 LORA02 header Pinouts NA NA
2 Sensor Header NA NA
3 PSOC-MIO Error NA NA
4 2 GPIOs to Linux header NA NA
5 RJ45 con to Linux header NA NA
connection
6 PCIe header verification NA NA
7 Check new RJ45 connector NA NA