VSYN VRF
Kbd_St rb[ 7: 0]
KBDSRB[ 7: 0] GND
GSM : 890~915MHz
Kbd_Rt n[ 2: 0] KBDRTN[ 2: 0] Txr f 1
Tx_I + TXI N
MM I C ON . Red_Led_En Bu zzer _En Buzze r TXL_P Tx_I - I+ TXI NR M QW0 10 DUAL_COUPLER DCS : 1710 ~1785 MHz
RED_LED_EN
Green_Led_Eb GREEN_LED ci r cui t TXL_M
TX_Q_P
Tx_Q+ I-
Q+ Tx V CO RM 008 ( LDC15D)
- 30 PI N Lde_Ct l LED_CNTL Tx_Q- Gsm_Pa
Fl i p_Sns TX_Q_M Q-
FLI P_SNS Tl cpo OUT2 GSMI N GSMOUT FL FL_OUT
HI _BAND_SEL Hi ghband TLCPO VC Dcs _Pa
Psw_Sns
PSW_SNS XTL0 OUT1 DCSI N DCSOUT FH FH_OUT
X- t al
XTLI 32. 768ß’ Txi f + SW1
Txi f - TXI F+ SW2
TXI F-
Dcs _Sw
Pwr _OnOf f VRTC GSM 369MHz
Txmop Gs m_Sw
BAT TXMO+ DCS 358MHz
LC Txmom
GND
f i l t er TXMO- Hi ghband
Tx _En1 GATE PA M
I rda_En VRF
IRD A I RDA_EN
Sds _Rx SDS_RX
- HSDL- 3201 Sds _Tx SDS_TX XTAL_OUT
OSC1 0 1 XTAL_I N Temp_Sns
AUX_ADC_I N LM 60CIM RF 14 2
19. 5MHz
TX_PWR_P Tx_Pwr + VAPC+ VPCGSM GSMAPC
Sds _Rx Tx_Pwr -
Mi c + TX_PWR_M VAPC-
Sds _Tx VPCDCS DCSAPC
Mi c -
Debug_Rx Spk r+ Li ne_Q-
IF CON . Debug_Tx BAND Dcs _Sw
Spk r- Li ne_Q+
TX_EN2 Tx_En2
Li ne_I + Rf _Cpl
- HSDL- 3201 Mi c - Li ne_I -
Por Por RFPC+
Mi c + Bp_Det
Ta_Det Mi c _Bi as
Vex t
Bp_Vf
VSI M
Vex t
Si m_Cl amp VBat
Bp_Det
VPACVCCD Rx_En1 Vset
VCCA1 Tx_En1 Bp_Vf Power I c
VOSC Sys _Ee Bat _Det _En Bat _Det _En
VRF Pwr _OnOf f Ta_Pr esent
VTI C Al arm Ta_Pr esent
Ta_Det
VSI M
VSYN
PM IC Ta_Det Charger _Di sabl e
Charger_Di s abl e
VSW S_Dat
20 436 S_Cl k
Vbat Res et _B Send_End
Vsi m_Ref Si m_Reset Hds t _Det
Vt est Si m_Cl k Rmt _Ct l
Si m_Dat Audi o ci r c ui t
Si m_En Dai _Reset
Cl k _Rqst Dai _Cl k
Por
Boost _En
2000. 03. 07
SGH-A110
Integrated Analog
Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
Integrated Analog
Circuit Diagram
REV:
2000.6.12 MP1.4
2000. 03. 07
SGH-A1
SGH-A110
M46 Asic Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
M46 Asic Circuit Diagram
REV:
2000.6.12 MP1.4
200. 03.0 7
SGH-A110
Dual Synthesizer + Transceiver
Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
Dual Synthesizer + Transceiver
Circuit Diagram
REV:
2000.6.12 MP1.4
2000 .03. 07
SGH-A110
Power Managenemt
Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
Power Managenemt
Circuit Diagram
REV
2000.6.12 MP1.4
Receiver FrontEnd
Transmit/Receive Switch
M em ory
Transmitter
Receiver Front End
Memory
Transmitter SGH-A188
Transmit / Receive Switch Transmitter
Receiver Front End Memory
Circuit Diagram
REV:
2000.6.12 MP1.3
Receiver Front End
Memory
Transmitter SGH-A188
Transmit / Receive Switch Transmitter
Receiver Front End Memory
Circuit Diagram
REV:
2000.6.12 MP1.4
SGH-A110
MMI and System Connector Interface
MMI and System Connector Interface Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
MMI and System Connector Interface
MMI and System Connector Interface REV:
Circuit Diagram
2000.6.12 MP1.4