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VCCD/ VBAT VCCA1/ VCCD/ VOs c

VSYN VRF

Spk r+ M4 6 20420 T FS4 00 B 7


Spk r-
RF13 7 (SA W RF21 0
Led_ct l Rxmxo 4 00 M Hz)
LCD Vbat
CERAMI C
RXMO Rf i f i n+ Hi ghband ( M46)
Rx_En1 ( 20420)
Lcd_Se I FI N+ OUT2 I N2 FI RST
CS3/ LCD_SEL FI LTER I FI 2+ 385. 4MHz Rx_Gai n0 ( 20420)
Mi r _En MOTOR_EN Rf i f i n- MI XER
CON . Cl k_Rqs t CLK_RQST RX_I F_P
Rx _I f +
Rx _I f -
I
( 14. 6MHz ) I
FI 2-
F20+
mi xer &
Amp
I FI N- OUT1 I N1
& SAW- FI L TER
Res et _B Res et _B RESET_B RX_I F_M I F20-
- KS0 723( Ω ± ) LNA FAR- F5 CE
D[ 7: 0] SYS_CLK Sys _Cl k SYS_CLK
F_RT F_Rt F_RT Gsm_ Rx
A(0) RXCLK Rx_Cl k RX_CLK Tx_En1 SAW- FI L TER
RX_DAT TX_EN1 TX_ENA
RXDATA Rx_Dat Rx_En1 RXENA Rxl o1 FAR- F5 CE
RXRATE Rx_Rt RX_RT RX_EN1 Syn_En
SYN_EN SXENA
A[ 20: 0] CDCRATE Cdc _Rt CDC_RT GSM : 935~960MHz
D[ 15: 0] DECDATA Dcdr_Dat Tx_En0
DEC_DAT TX_EN0 Tx _En2 Dcs_ Rx
A[ 20: 0] ENCDATA Enc dr _Dat ENC_DAT DCS : 1805 ~1880 MHz
D[ 15: 0] TX_EN2 Syn_Ref Uhf _Tune
CDCCLK Cdc _Cl k CDC_CLK SYN_REF UHF_TUNE
Fl ash_Sel FLASH_SEL CTLRATE Cnt l _Frm FREF
MEM ORY Read CLT_FRM RX_GAI N0 Rx_Gai n0 Hi ghband
RD CTLDATA Cnt l _Dat AN T _SWIT CH MHC- 173
Wri t e CTL_DAT_I N
Cl k _Rqst WR RESPDATA Rspns _Dat CTL_DAT_OUT VHF_TUNE Vhf _Tune ( LMC36- )
- 16M FLASH & CLKREQ CTLCLK Cnt l _Cl k Syn_Cl k OSC 3 01
2M SRAM Res et _B CTL_CLK SYN_CLK CLK
Audi o_Fl as h RESET SYN_DAT Syn_Dat DATA VCC6 RX_GSM ANT
Upper _By t e CS4/ AUD_FLAS SYN_EN1 Syn1_En LE RES1 RXV C O RX_DCS Gsm_Tr
- ONE CHI P( SHARP) H JTAG VC1
Lower _By t e RES2 Hi ghband ( M46)
Ram_Sel BS1 TRES SYN_LCK SYN0_LCK LD VCC5 TX_GSM VC2 Dcs _Tr
BS0 Tx_En0 ( 20420)
TCLK Txl o1 TX_DCS VC3
S_Dat RAM_SEL TMS VC4
EEP ROM S_Cl k SDA
TDI
SCL LOI N
TDO LOI NR
- 126K

Kbd_St rb[ 7: 0]
KBDSRB[ 7: 0] GND
GSM : 890~915MHz
Kbd_Rt n[ 2: 0] KBDRTN[ 2: 0] Txr f 1
Tx_I + TXI N
MM I C ON . Red_Led_En Bu zzer _En Buzze r TXL_P Tx_I - I+ TXI NR M QW0 10 DUAL_COUPLER DCS : 1710 ~1785 MHz
RED_LED_EN
Green_Led_Eb GREEN_LED ci r cui t TXL_M
TX_Q_P
Tx_Q+ I-
Q+ Tx V CO RM 008 ( LDC15D)
- 30 PI N Lde_Ct l LED_CNTL Tx_Q- Gsm_Pa
Fl i p_Sns TX_Q_M Q-
FLI P_SNS Tl cpo OUT2 GSMI N GSMOUT FL FL_OUT
HI _BAND_SEL Hi ghband TLCPO VC Dcs _Pa
Psw_Sns
PSW_SNS XTL0 OUT1 DCSI N DCSOUT FH FH_OUT
X- t al
XTLI 32. 768ß’ Txi f + SW1
Txi f - TXI F+ SW2
TXI F-
Dcs _Sw
Pwr _OnOf f VRTC GSM 369MHz
Txmop Gs m_Sw
BAT TXMO+ DCS 358MHz
LC Txmom
GND
f i l t er TXMO- Hi ghband
Tx _En1 GATE PA M
I rda_En VRF
IRD A I RDA_EN
Sds _Rx SDS_RX
- HSDL- 3201 Sds _Tx SDS_TX XTAL_OUT
OSC1 0 1 XTAL_I N Temp_Sns
AUX_ADC_I N LM 60CIM RF 14 2
19. 5MHz
TX_PWR_P Tx_Pwr + VAPC+ VPCGSM GSMAPC
Sds _Rx Tx_Pwr -
Mi c + TX_PWR_M VAPC-
Sds _Tx VPCDCS DCSAPC
Mi c -
Debug_Rx Spk r+ Li ne_Q-
IF CON . Debug_Tx BAND Dcs _Sw
Spk r- Li ne_Q+
TX_EN2 Tx_En2
Li ne_I + Rf _Cpl
- HSDL- 3201 Mi c - Li ne_I -
Por Por RFPC+
Mi c + Bp_Det
Ta_Det Mi c _Bi as
Vex t
Bp_Vf
VSI M
Vex t
Si m_Cl amp VBat
Bp_Det
VPACVCCD Rx_En1 Vset
VCCA1 Tx_En1 Bp_Vf Power I c
VOSC Sys _Ee Bat _Det _En Bat _Det _En
VRF Pwr _OnOf f Ta_Pr esent
VTI C Al arm Ta_Pr esent
Ta_Det
VSI M
VSYN
PM IC Ta_Det Charger _Di sabl e
Charger_Di s abl e
VSW S_Dat
20 436 S_Cl k
Vbat Res et _B Send_End
Vsi m_Ref Si m_Reset Hds t _Det
Vt est Si m_Cl k Rmt _Ct l
Si m_Dat Audi o ci r c ui t
Si m_En Dai _Reset
Cl k _Rqst Dai _Cl k
Por
Boost _En
2000. 03. 07
SGH-A110
Integrated Analog
Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
Integrated Analog
Circuit Diagram
REV:
2000.6.12 MP1.4
2000. 03. 07
SGH-A1
SGH-A110
M46 Asic Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
M46 Asic Circuit Diagram

REV:
2000.6.12 MP1.4
200. 03.0 7
SGH-A110
Dual Synthesizer + Transceiver
Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
Dual Synthesizer + Transceiver
Circuit Diagram
REV:
2000.6.12 MP1.4
2000 .03. 07
SGH-A110
Power Managenemt
Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
Power Managenemt
Circuit Diagram
REV
2000.6.12 MP1.4
Receiver FrontEnd

Transmit/Receive Switch

M em ory

Transmitter
Receiver Front End

Transmit / Receive Switch

Memory

Transmitter SGH-A188
Transmit / Receive Switch Transmitter
Receiver Front End Memory
Circuit Diagram
REV:
2000.6.12 MP1.3
Receiver Front End

Transmit / Receive Switch

Memory

Transmitter SGH-A188
Transmit / Receive Switch Transmitter
Receiver Front End Memory
Circuit Diagram
REV:
2000.6.12 MP1.4
SGH-A110
MMI and System Connector Interface
MMI and System Connector Interface Circuit Diagram
REV:
2000.6.12 MP1.3
SGH-A188
MMI and System Connector Interface
MMI and System Connector Interface REV:
Circuit Diagram
2000.6.12 MP1.4