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Asia/Oceania http://biz.lgservice.com

LED LCD TV
SERVICE MANUAL
CHASSIS : LD12C

MODEL : 42LW650G/S/T/W 42LW659S


MODEL : 42LW650G/S/T/W-ZC 42LW659S-ZC
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL67002306 (1108-REV01) Printed in Korea


CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ...................................................................................... 4

ADJUSTMENT INSTRUCTION ............................................................. 10

BLOCK DIAGRAM ................................................................................. 19

EXPLODED VIEW .................................................................................. 20

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Copyright © 2011 LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE


Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)


Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer, AC Volt-meter

always perform an AC leakage current check on the exposed


metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
shock. such as WATER PIPE,
To Instrument’s CONDUIT etc.
0.15 uF
Leakage Current Cold Check(Antenna Cold Check) exposed
With the instrument AC plug removed from AC source, connect an METALLIC PARTS
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc. When 25A is impressed between Earth and 2nd Ground
If the exposed metallic part has a return path to the chassis, the for 1 second, Resistance must be less than 0.1 Ω
measured resistance should be between 1 MΩ and 5.2 MΩ.
*Base on Adjustment standard
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright © 2011 LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range 3. Test method


This specification is applied to the LED LCD TV used LD12C 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC :CE, IEC
2. Requirement for Test
Each part is tested as below without special appointment.

1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC


2) Relative Humidity : 65 % ± 10 %
3) Power Voltage : Standard input voltage (AC 100-240 V~ 50
/ 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.

4. Model General Specification


No. Item Specification Remarks
1 Market EU(PAL Market-36Countries) DTV & Analog (Total 36 countries)
DTV (MPEG2/4, DVB-T) : 31 countries
(England/Italy/Germany/France/Spain/Sweden/Finland/Netherlands/Belgium/Luxemburg/
Greece/Denmark/Czech/Austria/Hungary/Swiss/Croatia/Turkey/Norway/Slovenia/Poland/
Ukraine/Portugal/Ireland/Morocco/Latvia/Estonia/Lithuania/Romania/Russia/Slovakia)

DTV (MPEG2/4, DVB-T2): 5 countries (England/Denmark/Sweden/Finland/Norway)

DTV (MPEG2/4, DVB-C): 10 countries


Sweden/Finland/Austria/Swiss/Germany/Netherlands/Hungary/Slovenia/Norway/Denmark

DTV (MPEG2/4,DVB-S): 31 countries


Albania/Austria/Belgium/Bosnia/Bulgaria/Croatia/Czech/Estonia/France/Germany/Greece/
Hungary/Ireland/Italy/Kazakhstan/Latvia/Lithuania/Luxembourg/Morocco/Netherlands/Poland/
Portugal/Romania/Russia/Serbia/Slovenia/Spain/Slovakia/Switzerland/Turkey/Ukraine

Analog Only - 5 countries (Bosnia/Serbia/Bulgaria/Albania/Kazakhstan)

Supported satellite : 22 satellites


HISPASAT 1C/1D, ATLANTIC BIRD 2, NILESAT 101/102, ATLANTIC BIRD 3, AMOS 2/3,
THOR 5/6, IRIUS 4, EUTELSAT-W3A, EUROBIRD 9A, EUTELSAT-W2A, HOTBIRD 6/8/9,
EUTELSAT-SESAT, ASTRA 1L/H/M/KR, ASTRA 3A/3B, BADR 4/6, ASTRA 2D, EUROBIRD
3, EUTELSAT-W7, HELLASSAT 2, EXPRESS AM1, TURKSAT 2A/3A, INTERSAT10
2 Broadcasting system 1) PAL-BG
2) PAL-DK
3) PAL-I/I’
4) SECAM L/L’, DK, BG, I
5) DVB-T
6) DVB-C
7) DVB-T2
8) DVB-S DVB-S :Satellite

Copyright © 2011 LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
No. Item Specification Remarks
3 Receiving system Analog : Upper Heterodyne G DVB-T
Digital : COFDM , QAM - Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

G DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4,1/8,1/16,1/32,1/128,19/128,19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

G DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

G DVB-S
- Symbolrate
DVB-S2 (8PSK/ QPSK) : 2 ~ 45 Msymbol/s
DVB-S (QPSK) : 2~ 45 Msymbol/s
-viterbi
DVB-S mode :1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 23, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
4 Scart Gender Jack(1EA) PAL, SECAM Scart Jack is Full scart and support MNT/DTV-OUT, DTV Recording(not support DTV Auto AV)
5 Video Input RCA(2EA) PAL, SECAM, NTSC 4System : PAL, SECAM, NTSC, PAL60
Rear 1EA, AV gender jack 1EA
6 Head phone out Antenna, AV1, AV2, AV3,
Component, RGB, HDMI1, HDMI2,
HDMI3, HDMI4 USB
7 Component Input(1EA) Y/Cb/Cr, Y/Pb/Pr Component Gender 1EA
8 RGB Input RGB-PC Analog(D-SUB 15PIN)
9 HDMI Input (4EA) HDMI1-DTV/DVI PC(HDMI version 1.3)
HDMI2-DTV Support HDCP
HDMI3-DTV
HDMI4-DTV
10 Audio Input (4EA) RGB/DVI Audio, Component, AV1, 2 L/R Input
11 SDPIF out (1EA) SPDIF out
12 USB (2EA) EMF, DivX HD, JPEG, MP3, DivX HD
For Service (download) - USB current : max 500 mA
- USB voltage : 4.75 V - 5.25 V
13 Wireless jack (1EA) 24V power & control Voltage : 24 V, Power : max 8 W

Copyright © 2011 LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
5. Component Video Input (Y, CB/PB, CR/PR)
Specification
No. Remark
Resolution H-freq(kHz) V-freq(Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080i
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 67.5 60 HDTV 1080p

6. RGB (PC)
Specification
No. Proposed Remarks
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08 28.321 For only DOS mode
2. 640*480 31.469 59.94 25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
-> 640*480 60 Hz Display
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1360*768 47.72 59.8 84.75 WXGA
6. 1920*1080 66.587 59.93 138.625 WUXGA FHD model

Copyright © 2011 LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
7. HDMI Input
(1) DTV Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469 /31.5 59.94 /60 27.00/27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96 /45 59.94 /60 74.17/74.25 HDTV 720P
5. 1920*1080 33.72 /33.75 59.94 /60 74.17/74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97 /27 23.97 /24 74.17/74.25 HDTV 1080P
8. 1920*1080 33.716 /33.75 29.976 /30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43 /67.5 59.94 /60 148.35/148.50 HDTV 1080P

(2) PC Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*400 31.468 70.08 28.321 HDCP
2. 640*480 31.469 59.94 25.17 VESA HDCP
3. 800*600 37.879 60.31 40.00 VESA HDCP
4. 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP
5. 1360*768 47.72 59.8 84.75 WXGA HDCP
6. 1280*1024 63.595 60.0 108.875 SXGA HDCP/FHD model
7. 1920*1080 67.5 60.00 138.625 WUXGA HDCP/FHD model

Copyright © 2011 LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
8. 3D Mode
(1) HDMI Input (1.4a)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1920*1080 53.95 / 54 23.98 / 24 148.35/148.5 HDTV 1080P Frame packing
2 1280*720 89.9 / 90 59.94/60 148.35/148.5 HDTV 720P Frame packing
3 1280*720 75 50 148.5 HDTV 720P Frame packing
4 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side(half), Top and bottom
5 1920*1080 56.3 50 148.5 HDTV 1080P Side by Side(half), Top and bottom
6 1280*720 45 60 74.25 HDTV 720P Side by Side(half), Top and Bottom
7 1280*720 37.5 50 74.25 HDTV 720P Side by Side(half), Top and Bottom
8 1920*1080 33.7 60 74.25 HDTV 1080i Side by Side(half), Top and Bottom
9 1920*1080 28.1 50 74.25 HDTV 1080i Side by Side(half), Top and Bottom
10 1920*1080 27 24 74.25 HDTV 1080P Side by Side(half), Top and Bottom
11 1920*1080 33.7 30 89.1 HDTV 1080P Side by Side(half), Top and Bottom

(2) HDMI Input (1.3)


No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom
2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom
3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom
4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom
5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard
6 1920*1080 33.75 30.00 74.25 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard
7 1920*1080 67.50 60.00 148.5 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard, Single Frame Sequential
8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard, Single Frame Sequential

(3) RF 3D Input(DTV)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom
2 1920*1080 28.125 50 74.25 HDTV 1080I Side by Side, Top & Bottom

(4) USB Input


No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed
1 1920*1080 33.75 30.000 74.25 Side by Side HDTV 1080P
Top & Bottom
Checkerboard

Copyright © 2011 LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
(5) RGB-PC Input
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side, Top & Bottom

(6) DLNA
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1920*1080 33.75 30 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard

(7) 3D Input mode


No. Side by Side Top & Bottom Checkerboard Single Frame Sequential Frame Packing
1.
L R
L

Copyright © 2011 LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range (3) Adjustment
1) Adjustment method
This specification sheet is applied to all of the LED LCD TV - Using RS-232, adjust items in the other shown in
with LD12C chassis. “3.1.(3).3)”

2) Adj. protocol
2. Designation Protocol Command Set ACK
(1) Because this is not a hot chassis, it is not necessary to use Enter adj. mode aa 00 00 a 00 OK00x
an isolation transformer. However, the use of isolation Source change xb 00 40 b 00 OK40x (Adjust 480i, 1080p Comp1 )
transformer will help protect test instrument.
xb 00 60 b 00 OK60x (Adjust 1920*1080 RGB)
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of Begin adj. ad 00 10
25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative Return adj. result OKx (Case of Success)
humidity if there is no specific designation. NGx (Case of Fail)
(4) The input voltage of the receiver must keep AC 100-240 Read adj. data (main) (main)
V~ 50 / 60Hz.
ad 00 20 000000000000000000000000007c007b006dx
(5) The receiver must be operated for about 5 minutes prior to
(sub) (Sub)
the adjustment when module is in the circumstance of over
15. ad 00 21 000000070000000000000000007c00830077x
Confirm adj. ad 00 99 NG 03 00x (Fail)
In case of keeping module is in the circumstance of 0 °C, it NG 03 01x (Fail)
should be placed in the circumstance of above 15 °C for 2 NG 03 02x (Fail)
hours
OK 03 03x (Success)

In case of keeping module is in the circumstance of below - End adj. aa 00 90 a 00 OK90x


20 °C, it should be placed in the circumstance of above 15
°C for 3 hours. Ref.) ADC Adj. RS232C Protocol_Ver1.0

[Caution] 3) Adj. order


When still image is displayed for a period of 20 minutes or - aa 00 00 [Enter ADC adj. mode]
longer (especially where W/B scale is strong. Digital pattern - xb 00 04 [Change input source to Component1(480i&1080p)]
13ch and/or Cross hatch pattern 09ch), there can some - ad 00 10 [Adjust 480i Comp1]
afterimage in the black level area. - xb 00 06 [Change input source to RGB(1024*768)]
- ad 00 10 [Adjust 1024*768 RGB]
- ad 00 90 End adj.

3. Automatic Adjustment 3.2. MAC Address


3.1. ADC Adjustment (1) Equipment & Condition
(1) Overview - Play file: Serial.exe
ADC adjustment is needed to find the optimum black level - MAC Address edit
and gain in Analog-to-Digital device and to compensate - Input Start / End MAC address
RGB deviation.
* If Adjust ADC is “OTP”, It doesn’t need ADC adjustment. (2) Download method
(GP3-BCM) 1) Communication Prot connection

(2) Equipment & Condition PCBA PC(RS-232C)


1) Jig (RS-232C protocol)
2) MSPG-925 Series Pattern Generator(MSPG-925FA,
pattern - 65)
- Resolution : 480i Comp1 RS-232C Po rt
1080P Comp1
1920*1080 RGB
- Pattern : Horizontal 100% Color Bar Pattern Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
- Pattern level : 0.7±0.1 Vp-p
- Image

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
2) MAC Address Download 3.4. LAN PORT INSPECTION(PING TEST)
- Com 1,2,3,4 and 115200(Baud rate) Connect SET -> LAN port == PC -> LAN Port
- Port connection button click(1)
SET PC
(1) Equipment setting
1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test
Program.
*IP Number : 12.12.2.2
(2) LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN CABLE

- Load button click(2) for MAC Address write.


- Start MAC Address write button(3)
- Check the OK Or NG

3.3. LAN Inspection


(1) Equipment & Condition
A Each other connection to LAN Port of IP Hub and Jig

3.5. Model name & Serial number Download


(2) LAN inspection solution (1) Model name & Serial number D/L
A LAN Port connection with PCB
A Press “Power on” key of service remote control.(Baud
A Network setting at MENU Mode of TV
rate : 115200 bps)
A setting automatic IP
A Connect RS232 Signal Cable to RS-232 Jack.
A Setting state confirmation
A Write Serial number by use RS-232.
-> If automatic setting is finished, you confirm IP and A Must check the serial number at Instart menu.
MAC Address.
(2) Method & notice
A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C.Serial number D/L must be conformed when it is
produced in production line, because serial number D/L
is mandatory by D-book 4.0

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
* Manual Download (Model Name and Serial Number) 2) Check the method of CI+ key by command (RS232 : ci
If the TV set is downloaded by OTA or service man, 00 20)
sometimes model name or serial number is initialized.(Not
CMD 1 CMD 2 Data 0
always)
There is impossible to download by bar code scan, so It C I 2 0
need Manual download.
a. Press the ‘instart’ key of ADJ remote control. 3) Result value
b. Go to the menu ‘5.Model Number D/L’ like below photo. i 01 OK 1d1852d21c1ed5dcx
c. Input the Factory model name(ex 42LW950-ZA) or Serial CI+ key Value
number like photo.

3.7. Widevine Key Download method


3.7.1. Widevine key Download
(1) Press "Power on" key of a Service Remote control (Baud
rate : 115200 bps)
(2) Connect RS232-C Signal Cable.
(3) Write Widevine Key through RS-232-C.
(4) Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).

d. Check the model name Instart menu -> Factory name


displayed (ex 42LW750S-ZA)
e. Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LW750S-ZA)

3.6. CI+ Key Download method => Check the Download to Widevine Key value in LGset.
3.6.1. Download Procedure
(1) Press "Power on" key of a Service Remote control. 3.7.2. check the method of Widevine Key value.
(Baud rate : 115200 bps) (1) Check the method on Instart menu.
(2) Connect RS232-C Signal Cable. (2) Check the method of RS232C Command.
(3) Write CI+ Key through RS-232-C. 1) into the main ass’y mode (RS232 : aa 00 00)
(4) Check whether the key was downloaded or not at ‘In Start’
CMD 1 CMD 2 Data 0
menu. (Refer to below).
A A 0 0

2) Check the key download for transmitted command


(RS232 : ci 00 10)

=> Check the Download to CI+ Key value in LGset. CMD 1 CMD 2 Data 0
C I 1 0
3.6.2. Check the method of CI+ Key value
(1) check the method on Instart menu
(2) check the method of RS232C Command 3) result value
1) into the main ass’y mode (RS232 : aa 00 00) - normally status for download : OKx
- abnormally status for download : NGx
CMD 1 CMD 2 Data 0
-
A A 0 0 3.7.3 check the method of Widevine Key value (RS232)
1) into the main ass’y mode (RS232 : aa 00 00)
2) check the key download for transmitted command
(RS232 : ci 00 10) CMD 1 CMD 2 Data 0
A A 0 0
CMD 1 CMD 2 Data 0
C I 1 0 2) Check the method of Widevine key by command
(RS232 : ci 00 20)
3) result value
CMD 1 CMD 2 Data 0
- normally status for download : OKx
- abnormally status for download : NGx C I 2 0

3.6.3. Check the method of CI+ Key value (RS232) 3) result value
1) into the main ass’y mode (RS232 : aa 00 00) i 01 OK 1d1852d21c1ed5dcx
CMD 1 CMD 2 Data 0 Widevine key Value

A A 0 0

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
3.8. Mac+Widevine+GP3 BCM CI+ download 4. Manual Adjustment
3.8.1 Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
4.1. ADC(GP3) Adjustment
4.1.1. Overview
ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation.

4.1.2. Equipment & Condition


(1) Adjust Remote control
(2) 801GF(802B, 802F, 802R) or MSPG925FA Pattern Generator
- Resolution :
3.8.2 MAC Address, CI Plus key and Widevine Key write. 480i, 720*480(MSPG-925FA->Model:209, Pattern:65)-480i
11Y LCD TV + MAC + Widevine + GP3_BCM CI Plus 1080p, 1920*1080(MSPG-925FA->Model:225, Pattern:65)-1080p
MARLIN Key : MAC + CI + WIDEVINE - Pattern : Horizontal 100 % Color Bar Pattern
- Pattern level: 0.7 ± 0.1 Vp-p
Com Port Check
- Image

PCBA Power ON Check

MAC Address Write

CI + Key Write

WIDEVINE Key Write

Result Play

(3) Must use standard cable

(1) Equipment setting 4.1.3. Adjust method


- Play file: keydownload.exe * If Adjust ADC is “OTP”, It doesn’t need ADC adjustment.
- select the download items.(MARLIN) (GP3-BM)
(2) Communication Prot connection (1) ADC 480i, 1080p Comp1
- Key Write :Com 1,2,3,4 and 115200(Baudrate) 1) Check connected condition of Component 1 cable to the
- Barcode : Com 1,2,3,4 and 9600(Baudrate) equipment.
(3) Mode check: Online Only 2) Give a 480i, 1080p Mode, Horizontal 100% Color Bar
(4) Check the test process: DETECT -> MAC -> CI -> Pattern to Component 1.
WIDEVINE (MSPG-925FA -> Model: 209, Pattern: 65) - 480i
(5) Play: START (MSPG-925FA -> Model: 225, Pattern: 65) - 1080p
(6) Result: Ready, Test, OK or NG 3) Change input mode as Component 1 and picture mode
as “Standard”
3.9. LNB voltage and 22KHz tone check 4) Press the In-start Key on the ADJ remote after at least 1
- only for DVB-S/S2 model min of signal reception. Then, select 7. External ADC ->
(1) Test method 1. COMP 1080p on the menu. Press enter key. The
1) Press "Power on" key of a service Remote control. adjustment will start automatically.
(Baud rate : 115200 bps) 5) If ADC calibration is successful, “ADC RGB Success” is
2) Connect cable between satellite ANT and test JIG. displayed.
3). Connect RS232-C Signal Cable. If ADC calibration is failure, “ADC RGB Fail” is displayed.
4) Write LNB ON control command through RS-232-C. 6) If ADC calibration is failure, after recheck ADC pattern or
5) check LED light ‘ON’ at 18V menu. condition retry calibration Error message refer to 5).
6) check LED light ‘ON’ at 22KHz tone menu.
7) Write LNB OFF control command through RS-232-C. (2) ADC 1920*1080 RGB
8) check LED light ‘OFF’ at 18V menu. 1) Check connected condition of Component & RGB cable
9) check LED light ‘OFF’ at 22KHz tone menu. to the equipment
2) Give a 1920*1080 Mode, 100 % Horizontal Color Bar
(2) RS-232 command for test LNB Pattern to RGB port.
(MSPG-925 Series -> model: 225 , pattern: 65 )
Command Set ACK
3) Change input mode as RGB and picture mode as “Standard”.
LNB On [A][I][ ][Set ID][ ][30][Cr] [O][K][x] or NG : [N][G][x] 4) Press the In-start Key on the ADJ remote after at least 1
LNB Off [A][I][ ][Set ID][ ][40][Cr] [O][K][x] or NG : [N][G][x] min of signal reception. Then, select 7. External ADC ->
1. COMP 1080p on the menu. Press enter key. The
adjustment will start automatically.
(3) Test result 5) If ADC calibration is successful, “ADC RGB Success” is
- After send LNB On command, ‘18V LED’ and ‘22KHz displayed.
tone LED’ should be ON. If ADC calibration is failure, “ADC RGB Fail” is displayed.
- After send LNB OFF command, ‘18V LED’ and ‘22KHz 6) If ADC calibration is failure, after recheck ADC pattern or
tone LED’ should be OFF. condition retry calibration Error message refer to 5).

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
4.2. EDID(The Extended Display Identification (5) EDID DATA_2D
A HDMI
Data)/DDC(Display Data Channel) download
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
(1) Overview
0x00 0 FF FF FF FF FF FF 0 1E 6D ⓐ ⓑ
It is a VESA regulation. A PC or a MNT will display an
0x01 ⓒ 1 3 80 10 9 78 0A EE 91 A3 54 4C 99 26
optimal resolution through information sharing without any
0x02 0F 50 54 A1 8 0 71 40 81 C0 81 0 81 80 95 0
necessity of user input. It is a realization of “Plug and Play”.
0x03 90 40 A9 C0 B3 0 2 3A 80 18 71 38 2D 40 58 2C
0x04 45 0 A0 5A 0 0 0 1E 66 21 50 B0 51 0 1B 30
(2) Equipment
0x05 40 70 36 0 A0 5A 0 0 0 1E 0 0 0 FD 0 39
- Adjust remote control
0x06 3F 1F 52 10 0 0A 20 20 20 20 20 20 ⓓ
- Since embedded EDID data is used, EDID download JIG,
0x07 ⓓ 1 ⓔ1
HDMI cable and D-sub cable are not need. 0x00 2 3 26 F1 4E 10 1F 84 13 5 14 3 2 12 20 21
0x01 22 15 1 26 15 7 50 9 57 7 67 ⓕ
(3) Download method 0x02 ⓕ E3 5 3 1 1 1D 80 18 71 1C 16 20 58 2C
1) Press Adj. key on the Adj. R/C, then select “10.EDID 0x03 25 0 A0 5A 0 0 0 9E 1 1D 0 80 51 D0 1A 20
D/L”, By pressing Enter key, enter EDID D/L menu. 0x04 6E 88 55 0 A0 5A 0 0 0 1A 2 3A 80 18 71 38
2) Select [Start] key by pressing Enter key, HDMI1/ HDMI2/ 0x05 2D 40 58 2C 45 0 A0 5A 0 0 0 1E 66 21 50 B0
HDMI3/ RGB are Writing and display OK or NG. 0x06 51 0 1B 30 40 70 36 0 A0 5A 0 0 0 1E 0 0
For Analog EDID For HDMI EDID 0x07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ⓔ2

D-sub to D-sub DVI-D to HDMI or HDMI to HDMI A RGB


0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x00 0 FF FF FF FF FF FF 0 1E 6D ⓐ ⓑ
0x01 ⓒ 1 3 68 10 9 78 0A EE 91 A3 54 4C 99 26
0x02 0F 50 54 A1 8 0 71 40 81 C0 81 0 81 80 95 0
0x03 90 40 A9 C0 B3 0 2 3A 80 18 71 38 2D 40 58 2C
0x04 45 0 A0 5A 0 0 0 1E 66 21 50 B0 51 0 1B 30
0x05 40 70 36 0 A0 5A 0 0 0 1E 0 0 0 FD 0 3A
0x06 3E 1E 53 10 0 0A 20 20 20 20 20 20 ⓓ
(4) EDID DATA_3D 0x07 ⓓ 0 ⓔ3
A HDMI

0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F A Reference
0x00 0 FF FF FF FF FF FF 0 1E 6D ⓐ ⓑ - HDMI1 ~ HDMI4 / RGB
0x01 ⓒ 1 3 80 10 9 78 0A EE 91 A3 54 4C 99 26 - In the data of EDID, bellows may be different by S/W or
0x02 0F 50 54 A1 8 0 71 40 81 C0 81 0 81 80 95 0 Input mode.
0x03 90 40 A9 C0 B3 0 2 3A 80 18 71 38 2D 40 58 2C ⓐ Product ID
0x04 45 0 A0 5A 0 0 0 1E 66 21 50 B0 51 0 1B 30 Model Name HEX EDID Table DDC Function
0x05 40 70 36 0 A0 5A 0 0 0 1E 0 0 0 FD 0 39
ALL 0001 0100 Analog
0x06 3F 1F 52 10 0 0A 20 20 20 20 20 20 ⓓ
0x07 ⓓ 1 ⓔ1
0001 0100 Digital
0x00 2 3 37 F1 4E 10 1F 84 13 5 14 3 2 12 20 21 ⓑ Serial No. : Controlled on product line
0x01 22 15 1 26 15 7 50 9 57 7 ⓕ ⓒ Month, Year: Controlled on production line:
0x02 ⓕ ex) Monthly : ‘01’ -> ‘01’
0x03 ⓕ E3 5 3 1 1 1D 80 18 71 1C 16 20 58
Year : ‘2010’ -> ‘14’
0x04 2C 25 0 A0 5A 0 0 0 9E 1 1D 0 80 51 D0 1A
ⓓ Model Name(Hex):
0x05 20 6E 88 55 0 A0 5A 0 0 0 1A 2 3A 80 18 71
0x06 38 2D 40 58 2C 45 0 A0 5A 0 0 0 1E 0 0 0
MODEL MODEL NAME(HEX)
0x07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ⓔ2 all 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

A RGB ⓔ Checksum: Changeable by total EDID data._3D


0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F INPUT 1 2 3
0x00 0 FF FF FF FF FF FF 0 1E 6D ⓐ ⓑ HDMI1 7F CB X
0x01 ⓒ 1 3 68 10 9 78 0A EE 91 A3 54 4C 99 26
HDMI2 7F BB X
0x02 0F 50 54 A1 8 0 71 40 81 C0 81 0 81 80 95 0
HDMI3 7F AB X
0x03 90 40 A9 C0 B3 0 2 3A 80 18 71 38 2D 40 58 2C
0x04 45 0 A0 5A 0 0 0 1E 66 21 50 B0 51 0 1B 30 HDMI4 7F 9B X
0x05 40 70 36 0 A0 5A 0 0 0 1E 0 0 0 FD 0 3A RGB X X 98
0x06 3E 1E 53 10 0 0A 20 20 20 20 20 20 ⓓ
0x07 ⓓ 0 ⓔ3 ⓔ Checksum: Changeable by total EDID data._2D
INPUT 1 2 3
HDMI1 7F D9 X
HDMI2 7F C9 X
HDMI3 7F B9 X
HDMI4 7F A9 X
RGB X X 98

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
ⓕ Vendor Specific(HDMI)_3D 4.3.3. Equipment connection MAP
INPUT MODEL NAME(HEX)
Co lo r Analyzer
HDMI1 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
Probe RS -232C
HDMI2 78 03 0C 00 20 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
Co m p ut er
HDMI3 78 03 0C 00 30 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10 RS -232C
RS -232C
HDMI4 78 03 0C 00 40 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10 Pat t ern Generat o r

ⓕ Vendor Specific(HDMI)_2D Signal Source

* If TV internal pattern is used, not needed


INPUT MODEL NAME(HEX)
HDMI1 67 03 0C 00 10 00 B8 2D
HDMI2 67 03 0C 00 20 00 B8 2D 4.3.4. Adj. Command (Protocol)
HDMI3 67 03 0C 00 30 00 B8 2D <Command Format>
HDMI4 67 03 0C 00 40 00 B8 2D LEN CMD VAL CS

- LEN: Number of Data Byte to be sent


4.3. White Balance Adjustment - CMD: Command
4.3.1 Overview - VAL: FOS Data value
(1) W/B adj. Objective & How-it-works - CS: Checksum of sent data
(2) Objective: To reduce each Panel’s W/B deviation - A: Acknowledge
(3) How-it-works : When R/G/B gain in the OSD is at 192, it Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of A RS-232C Command used during auto-adj.
R/G/B is fixed at 192, and the other two is lowered to find RS-232C COMMAND Explanation
the desired value. [CMD ID DATA]
(4) Adj. condition : normal temperature wb 00 00 Begin White Balance adj.
1) Surrounding Temperature : 25 ºC ± 5 ºC
wb 00 10 Gain adj.(internal white pattern)
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 % wb 00 1f Gain adj. completed
* Before White balance adjustment, Keep power on status. wb 00 20 Offset adj.(internal white pattern)
don’t power off. wb 00 2f Offset adj. completed
* ALEF Header(Module with T-con) supplied as SKD has wb 00 ff End White Balance adj.(Internal pattern disappears)
White Balance data. (White balance data is stored in
EEPROM of the T-con Board) Ex) wb 00 00 -> Begin white balance auto-adj.
It doesn’t need to adjust White balance if “3. Adjust White wb 00 10 -> Gain adj.
Balance” is OK as figure below. ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f -> Gain adj. completed
*(wb 00 20(Start), wb 00 2f(completed)) -> Off-set adj.
wb 00 ff -> End white balance auto-adj.

A Adj. Map
ITEM Command Data Range(Hex.) Default(Decimal)
Cmd 1 Cmd 2 Min Max
Cool R-Gain j g 00 C0
G-Gain j h 00 C0

4.3.2 Equipment B-Gain j i 00 C0


1) Color Analyzer: CA-210 (LED Module : CH 14) R-Cut
2) Adj. Computer(During auto adj., RS-232C protocol is needed) G-Cut
3) Adjust Remote control B-Cut
4) Video Signal Generator MSPG-925F 720p/216-Gray Medium R-Gain j a 00 C0
(Model:204, Pattern:80IRE)
G-Gain j b 00 C0
-> Only when internal pattern is not available
B-Gain j c 00 C0
A Color Analyzer Matrix should be calibrated using CS-1000 R-Cut
G-Cut
B-Cut
Warm R-Gain j d 00 C0
G-Gain j e 00 C0
B-Gain j f 00 C0
R-Cut
G-Cut

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
4.3.5. Adjustment method A Standard color coordinate and temperature using CA-210
(1) Auto adjustment method (CH 14)
1) Set TV in adj. mode using POWER ON key. Mode Color Coordination Temp ∆UV
2) Zero calibrate probe then place it on the center of the
Display. x y
3) Connect Cable (RS-232C) COOL 0.269 ± 0.002 0.273 ± 0.002 13000 K 0.0000
4) Select mode in adj. Program and begin adjustment.
MEDIUM 0.285 ± 0.002 0.293 ± 0.002 9300 K 0.0000
5) When adjustment is complete (OK Sign), check
adjustment status pre mode. (Warm, Medium, Cool) WARM 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
6) Remove probe and RS-232C cable to complete adj.

A W/B Adj. must begin as start command “wb 00 00” , and 4.3.7. White balance table
finish as end command “wb 00 ff”, and Adj. offset if need. A Module change color coordinate because of aging time.
A Apply under the color coordinate table, for compensated
(2) Manual adjustment method aging time.
1) Set TV in Adjustment mode using POWER ON GP2 Aging Time Cool Medium Warm
2) Zero Calibrate the probe of Color Analyzer, then place it on
(Min.) X Y X Y X Y
the center of LCD module within 10 cm of the surface.
3) Press ADJ key -> EZ adjust using adjustment R/C -> 7. 269 273 285 293 313 329
White-Balance then press the cursor to the right key(G). 1 0-2 279 288 295 308 319 338
(When key(G) is pressed 216 Gray internal pattern will 2 3-5 278 286 294 306 318 336
be displayed) 3 6-9 277 285 293 305 317 335
4) One of R Gain / G Gain / B Gain should be fixed at 192,
4 10-19 276 283 292 303 316 333
and the rest will be lowered to meet the desired value.
5 20-35 274 280 290 300 314 330
5) Adj. is performed in COOL, MEDIUM, WARM 3 modes
of color temperature. 6 36-49 272 277 288 297 312 327
7 50-79 271 275 287 295 311 325
A If internal pattern is not available, use RF input. In EZ 8 80-149 270 274 286 294 310 324
Adj. menu 7.White Balance, you can select one of 2 9 Over 150 269 273 285 293 309 323
Test-pattern: ON, OFF. Default is inner(ON). By
selecting OFF, you can adjust using RF signal in 216
Gray pattern. 4.4. Wireless function check
Step 1) Connect set and Dongle of Wireless to Cable of HDMI
A Adj. condition and cautionary items & TTA 20Pin
1) Lighting condition in surrounding area Step 2) At OSD of SET, check the message like Fig.3
Surrounding lighting should be lower 10 lux. Try to Step 3) Detach Cable of Wireless Dongle
isolate adj. area into dark surrounding.
2) Probe location : Color Analyzer(CA-210) probe should
be within 10 cm and perpendicular of the module
surface (80° ~ 100°)
3) Aging time
Connect
- After Aging Start, Keep the Power ON status during 5
Minutes.
- In case of LCD, Back-light on should be checked
Fig . 1 Fig . 2
using no signal or Full-white pattern. < Do ng le> < Wireless Read y Set >

4.3.6. Reference(White Balance Adj. coordinate and


temperature)
A Luminance : 204 Gray
A Standard color coordinate and temperature using CS-1000
(over 26 inch)
Mode Color Coordination Temp ∆UV
x y
COOL 0.269 0.273 13000 K 0.0000
MEDIUM 0.285 0.293 9300 K 0.0000 Fig . 3 Connect the Dongle
( Do ng le Co nnec t io n Disp lay)
WARM 0.313 0.329 6500 K 0.0000

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
Only for training and service purposes
4.5. EYE-Q function check 4.8. 3D function test
Step 1) Turn on TV (Pattern Generator MSHG-600, MSPG-6100 [Support HDMI 1.4])
Step 2) Press EYE key of Adj. R/C * HDMI mode No. 872, pattern No. 83)
Step 3) Cover the Eye Q II sensor on the front of the using 1) Please input 3D test pattern like below
your hand and wait for 6 seconds
Step 4) Confirm that R/G/B value is lower than 10 of the “Raw
Data (Sensor data, Back light)”. If after 6 seconds,
R/G/B value is not lower than 10, replace Eye Q II
sensor.
Step 5) Remove your hand from the Eye Q II sensor and wait
for 6 seconds.
Step 6) Confirm that “ok” pop up. If change is not seen,
replace Eye Q II sensor.

2) When 3D OSD appear automatically, then select OK key.

4.6. Local Dimming Function Check


(1) Turn on TV.
(2) At the Local Dimming mode, module Edge Backlight 3) Don’t wear a 3D Glasses, Check the picture like below.
moving Top to Bottom Back light of IOP module moving.
(3) Confirm the Local Dimming mode.
(4) Press “exit” key

4.9. LNB voltage and 22 KHz tone check


(only for DVB-S/S2 model)
(1) Test method
1) Set TV in Adj. mode using POWER ON.
2) Connect cable between satellite ANT and test JIG.
3) Press Yellow key (ETC+SWAP) in Adj Remote control to
make LNB on.
4.7. Magic Motion Remote control test 4) check LED light ‘ON’ at 18V menu.
- Equipment : RF Remote control for test, IR-KEY-Code 5) check LED light ‘ON’ at 22KHz tone menu.
Remote control for test 6) Press Blue key (ETC+PIP INPUT) in Adj Remote control
- You must confirm the battery power of RF-Remote control to make LNB off.
before test.(recommend that change the battery per every lot) 7) Check LED light ‘OFF’ at 18 V menu.
- Sequence (test) 8) Check LED light ‘OFF’ at 22 KHz tone menu.
1) if you select the ‘start key(Mute)’ on the controller, you can
pairing with the TV SET. (2) Test result
2) You can check the cursor on the TV Screen, when select - After press LNB On key, ‘18 V LED’ and ‘22 KHz tone
the ‘OK’ key on the controller. LED’ should be ON.
3) You must remove the pairing with the TV Set by select - After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone
‘Vol+(STOP)’ key on the controller. LED’ should be OFF.

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
4.10. Option selection per country 6. Audio
(1) Overview
No. Item Min. Typ. Max. Unit
- Option selection is only done for models in Non-EU.
- Applied model: LD03D/03E Chassis applied EU model. 1. Audio practical max 9 10 12 W EQ Off
Output, L/R AVL Off
(2) Method
1) Press ADJ key on the Adj. Remote Control, then select (Distortion=10 % 0.5 Vrms Clear Voice Off
Country Group Menu. max Output)
2) Depending on destination, select Country Group Code
2. Speaker (8 Ω 9 10.0 12.0 W EQ On
04 or Country Group EU then on the lower Country
option, select US, CA, MX. Selection is done using +, - Impedance) AVL On
or GF KEY. Clear Voice On

4.11. Tool Option selection Measurement condition:


- Method : Press Adj. key on the Adj. Remote Control, then 1. RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
select Tool option. 2. CVBS, Component: 1 KHz sine wave signal 0.4 Vrms
3. RGB PC: 1 KHz sine wave signal 0.7 Vrms
4.12. Ship-out mode check(In-stop)
After final inspection, press IN-STOP key of the Adj. R/C and
check that the unit goes to Stand-by mode. 7. USB S/W Download (option, Service only)
1) Put the USB Stick to the USB socket.
2) Automatically detecting update file in USB Stick.
- If your downloaded program version in USB Stick is Low,
5. GND and Internal Pressure check it didn’t work. But your downloaded version is High, USB
5.1. Method data is automatically detecting.
1) GND & Internal Pressure auto-check preparation 3) Show the message “Copying files from memory”.
- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
4) Updating is starting.
5.2. Checkpoint
• TEST voltage
- GND: 1.5 KV/min at 100 mA
- SIGNAL: 3 KV/min at 100 mA
• TEST time: 1 second
• TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL 5) Updating Completed, The TV will restart automatically
• LEAKAGE CURRENT: At 0.5 mArms 6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have, TV
can lost all channel data. In this case, you have to channel
recover. if all channel data is cleared, you didn’t have a
DTV/ATV test on production line.

* After downloading, have to adjust TOOL OPTION again.


1) Push "IN-START" key in service remote control.
2) Select "Tool Option 1" and push “OK” key.
3) Push in the number. (Each model has their number.)

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
Only for training and service purposes
BLOCK DIAGRAM

Copyright © 2011 LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only
Only for training and service purposes
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

710
700
400

900
521

910
540
530
LV2

800
LV1

810

A10
200

A5
120

AG1
511

A21
A2
510
300

Copyright LG Electronics. Inc. All rights reserved. - 20 - LGE Internal Use Only
Only for training and service purposes
NAND FLASH MEMORY 8Gbit 16Gbit Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1) Strap Setting
+3.3V_Normal
+3.3V_Normal
+3.3V_Normal 0000: ST Micro M25P or compatible Serial Flash
IC102-*1
TH58DVG4S0ETA20 0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
IC102 0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
TC58DVG3S0ETA00 0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
R113 R117 R122 R127 R154 R157 R160 R164 R167 R170 R175 R177 R179 R181 R183 R187 R192
10K 10K 10K 10K 1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
NC_1 NC_26 OPT OPT 1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O) OPT OPT OPT OPT OPT OPT OPT OPT OPT OPT
1 DEV_NAND_16Gbit 48 CI_ADDR[4]
NC_1 NC_28 0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
1 NAND_8Gbit 48 NC_2 NC_25 NAND_DATA[7] 0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices NAND_DATA[0]
2 47
NC_2 NC_27 NAND_DATA[2] 0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
2.7K

2 47 NC_3 NC_24 CI_ADDR[7]


0111: 3B dual IO Serial Flash
3 46 NAND_DATA[1] 1001: NAND_DATA[6]
NC_3 NC_26 BB dual IO Serial Flash
3 46 NC_4 NC_23 R114 R118 R123 R128 1011: fast Serail Flash > 50Mhz
4 45 10K 10K 10K 10K CI_ADDR[6]
NC_4 NC_25 NAND_DATA[0-7] OPT OPT 1100: OneNAND Flash (always 16-bit)
4 45 NC_5 I/O8 NAND_CLE
1110: Reserved
R107

5 44 NAND_DATA[4]
NC_5 I/O8 1101, 1111: Reserved
5 44 NAND_DATA[7] RY/BY2 I/O7 CI_ADDR[9]
16Gbit 6 43
R149 0 NC_6 I/O7 CI_ADDR[11]
6 43 NAND_DATA[6] RY/BY1 I/O6
7 42 CI_ADDR[12]
RY/BY I/O6
NAND_RBb 7 42 NAND_DATA[5] RE I/O5 CI_ADDR[13]
8 41
RE I/O5 CI_ADDR[8]
NAND_REb 8 41 NAND_DATA[4] CE1 NC_22
CE NC_24
9 40 NAND ECC (FA3, FA2, FALE) NAND_DATA[3]
NAND_CEb 9 40 CE2 PSL NAND_DATA[5]
16Gbit 16Gbit 10 39 +3.3V_Normal
NC_7 PSL 0
NAND_CEb2 R148 0 10 39 R151 NC_6 NC_21 R155 R158 R161 R165 R168 R171 R176 R178 R180 R182 R184 R188 R193
11 38 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
NC_8 NC_23
C102 11 38 VCC_1 VCC_2 OPT OPT OPT
4700pF 12 37 R111 R115 R119
VCC_1 VCC_2 +3.3V_Normal 10K 10K 10K
12 37 VSS_1 VSS_2 OPT 000 = ECC disabled
C101 13 36 OPT
VSS_1 VSS_2 C104 10uF CI_ADDR[3] 001 = ECC 1-bit repair
0.1uF 13 36 NC_7 NC_20
10V 010 = ECC 4-bit BCH (O)
14 35 CI_ADDR[2]
NC_9 NC_22 011 = ECC 8-bit BCH, 27 byte spare
14 35 C103 NC_8 NC_19 NAND_ALE 100 = ECC 12-bit BCH, 27 byte spare
0.1uF 15 34
NC_10 NC_21 R112 R116 R120 101 = ECC 8-bit BCH, 16 byte spare NAND_DATA[0]:
15 34 CLE NC_18 10K 10K 10K 110, 111 = Reservedd 0: System is LITTLE endian (O) CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
16 33 OPT TVM Crystal oscillator bias/gain control
CLE NC_20 1: System is BIG endian
NAND_CLE 16 33 ALE I/O4 0000: 210uA
17 32
ALE I/O4 CI_ADDR[7]: 0001: 390uA
NAND_ALE 17 32 NAND_DATA[3] WE I/O3 0: Disable EDID automatic Downloading from Flash (O) 0010: 570uA
18 31
WE I/O3 1: Enable EDID automatic Downloading from Flash 0011: 730uA
NAND_WEb 18 31 NAND_DATA[2] WP I/O2 0100: 890uA (O)
19 30
WP I/O2 NAND_DATA[6] : 0111: 1290uA
Write Protection +3.3V_Normal 19 30 NAND_DATA[1] NC_9 I/O1 0: Disable OSC clock output on chip Pin (O) 1000: 1416uA
20 29
NC_11 I/O1 1: Enable OSC clock output on chip pin. 1111: 2196uA
- High : Normal Operation 20 29 NAND_DATA[0] NC_10 NC_17 DUAL COMPONENT 0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
R103
4.7K

- Low : Write Protection 21 28


OPT

NC_12 NC_19 CI_ADDR[6]:


21 28 NC_11 NC_16 0: Host MIPS run at 500 MHz (O) CI_ADDR[8]:
NC_13 NC_18
22 27 IC102 1ST : EAN61000101 2ND : T-TH58DVG4S0ETA20 1: Host MIPS run at 250 MHz 0: RESETOUTb (in On/Off only) stay asserted until software releases them.
22 27 NC_12 NC_15 1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
FLASH_WP 23 26
NC_14 NC_17 NAND_CLE: at end of RESETb pulse (O)
23 26 NC_13
24 25
NC_14 IC102-*1 0: Differential Oscillators TVM not bypassed (O)
NC_15 NC_16 1: Differential Oscillators TVM bypassed NAND_DATA[3]:
24 25 0: MIPS will boot from external flash (O)
NAND_DATA[4]: 1: MIPS will boot from ROM
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O) NAND_DATA[5]:
0: FLASH MODE (O)
1: BSC_SLAVE(BBS) MODE

BCM_NVM_256K
IC103-*1
+3.3V_Normal
NVRAM AT24C256C-SSHL-T

A0
1 8
VCC

A1 WP
R196 2 7
IC101 10K A2 SCL
LGE35230(BCM35230KFSBG) +3.3V_Normal 3 6

RGB_DDC_SDA GND SDA


4 5
S
B
D

BCM_WITHOUT_CAP
B5 AE27 BCM_NVM_1M +3.3V_Normal
HDMI_CLK- HDMI0_CLKN TXOUT0_L0N TXB4P Q101 IC101

4.7K

4.7K
IC103

OPT
R173

R174
C5 AE28
HDMI_CLK+ HDMI0_CLKP TXOUT0_L0P TXB4N BSS83 LGE35230(BCM35230KFSBG) M24M01-HRMN6TP
G

AF27
TXOUT0_L1N TXB3P NAND_DATA[0-7]
A4 AF28
HDMI_RX0- HDMI0_D0N TXOUT0_L1P TXB3N C118 NC VCC
B4 AG27 BCM_WITHOUT_CAP 1 8 Write Protection
HDMI_RX0+ HDMI0_D0P TXOUT0_L2N TXBCLKP 0.1uF AG6 AB1 NAND_DATA[7]
AG28 16V 54MHz_XTAL_P TVM_XTALIN FAD_7 R169
TXOUT0_L2P TXBCLKN AB3 NAND_DATA[6] 0 E1 WP - Low : Normal Operation
+3.3V_Normal A3 AE26 FAD_6 2 7
HDMI_RX1- HDMI0_D1N TXCLK_LN TXB2P AF6 AC1 NAND_DATA[5] A8’h - High : Write Protection
B3 AF26 54MHz_XTAL_N TVM_XTALOUT FAD_5
HDMI_RX1+ HDMI0_D1P TXCLK_LP TXB2N AC2 NAND_DATA[4] E2 SCL
AH27 +3.3V_Normal FAD_4 3 6 R190 33
TXB1P AC3 SCL3_3.3V
TXOUT0_L3N

4.7K
NAND_DATA[3]

OPT
R172
A2 AG26 FAD_3
R101 R105 R104 R195 HDMI_RX2- HDMI0_D2N TXOUT0_L3P TXB1N V5 AD2 NAND_DATA[2] VSS SDA
B2 AF25 LNB_INT IRRXDA FAD_2 4 5 R191 33
4.7K 4.7K 4.7K 4.7K HDMI_RX2+ TXB0P AD3 SDA3_3.3V
HDMI0_D2P TXOUT0_L4N NAND_DATA[1]
AE25 R198 FAD_1
TXOUT0_L4P TXB0N 10K AE2 NAND_DATA[0]
FAD_0
AB4
W2 FP_IN0
CEC RGB_DDC_SCL Y4
AH26
S
B
D

FP_IN1
TXOUT0_U0N TXA4P AG1
V4 AG25 FALE NAND_ALE
DDC0_SCL TXOUT0_U0P TXA4N Q102 AA4 AF1
W4 AE24 SPARE_ADC1 FCEB_0 NAND_CEb
DDC0_SDA TXOUT0_U1N TXA3P BSS83 Y5 AC5
AD24 SPARE_ADC2 FCEB_1 NAND_CEb2 X101-*2
G

TXOUT0_U1P TXA3N AE6


V3
V2
HDMI0_HTPLG_IN TXOUT0_U2N
AH25
AF24
TXACLKP
TXACLKN
C119 SC_ID
AB2
FS_IN1
FCEB_2
FCEB_3
AG5
/CI_CE1
/CI_CE2
54MHz X-TAL X-TAL_1
1
54MHz
4
GND_2

HDMI0_HTPLG_OUT TXOUT0_U2P 0.1uF AB5 GND_1 X-TAL_2


AE23 16V FS_IN2
TXCLK_UN TXA2P 2 3
D13 AD23 C113
HDMI_ARC HDMI0_ARC TXCLK_UP TXA2N AF3 12pF CRYSTAL_BCM_KDS
E6 AG24 NFWPB FLASH_WP R185 0 EAW58239604
HDMI0_RESREF TXOUT0_U3N TXA1P U3 AG2 54MHz_XTAL_N
AF23 VGA_SDA FWE NAND_WEb DAISHINKU CORPORATION.
TXA1N +3.3V_Normal U2 AE3 50V
R106 TXOUT0_U3P 3 2
AC22 VGA_SCL FRD NAND_REb X-TAL_2 GND_1 X101-*1
3K TXOUT0_U4N TXA0P AA5 R189 54MHz
AD22 FRDYB /PCM_WAIT 4 1 X-TAL_1 GND_2
TXOUT0_U4P TXA0N GND_2 X-TAL_1 1M
1 4
Y2 54MHz OPT
BCM_RX RDA X101 GND_1 X-TAL_2
BBS CONNECT R121 R126 R129 R131 Y1 AF2 R186 0 2 3
CI_ADDR[2-14] 54MHz_XTAL_P
AG23 1.2K 1.2K 1.2K 1.2K BCM_TX TDA FA_0 NAND_CLE C114 CRYSTAL_BCM_Sunny
TXOUT1_L0N TXD4P +3.3V_Normal AE1 12pF CRYSTAL_BCM_Lihom
AH23 P101 FA_1 NAND_RBb EAW58812611 EAW60763703
TXD4N 33 AA3 AC4 50V
TXOUT1_L0P SDA0_3.3V R135 CI_ADDR[2] SUNNY ELECTRONICS CORPORATION LIHOM CO., LTD.
AE22 TJC2508-4A BSCDATAA FA_2
TXOUT1_L1N TXD3P R136 33 AA2 AD5 CI_ADDR[3]
AE21 SCL0_3.3V BSCCLKA FA_3
TXOUT1_L1P TXD3N AD4 CI_ADDR[4]
AF22 FA_4
TXOUT1_L2N TXDCLKP VCC H3 AE4 CI_ADDR[5]
AH22 1 SCL2_3.3V RDB/GPIO FA_5
TXOUT1_L2P TXDCLKN C106 R109 R110 H2 AE5 CI_ADDR[6]
AG22 1.5K 1.5K SDA2_3.3V TDB/GPIO FA_6
TXCLK1_LN TXD2P 4.7uF AD6
AF21 CI_ADDR[7]
SCL R199 22 FA_7
TXCLK1_LP TXD2N 2 H4 AH3 CI_ADDR[8]
AG21 R197 22 BSC_S_SCL FA_8
TXOUT1_L3N TXD1P H5 AF4 CI_ADDR[9]
AF20 BSC_S_SDA FA_9
TXOUT1_L3P TXD1N SDA AH4 CI_ADDR[10]
AD21 3 +3.3V_Normal FA_10
TXOUT1_L4N TXD0P C107 C108 C109 C110 AG4 CI_ADDR[11]
AC21 33pF 33pF 33pF 33pF FA_11
TXOUT1_L4P TXD0N R141 4.7K F25 AF5 CI_ADDR[12]
GND 50V 50V 50V 50V NMIB FA_12
4 DVB_S DVB_S AG3 CI_ADDR[13] +3.3V_Normal
FA_13
W5 AH2 CI_ADDR[14]
AG20 DVB_S Option: apply EU Satellite model PCM_5V_CTL POWER_CTRL FA_14
TXOUT1_U0N TXC4P AH5
AH20 5V_HDMI_1 OPT FA_15
TXOUT1_U0P TXC4N R142 22 U5 R146 10K R147 R150 R153 R156 R159 R162 R166
AD19 AON_HSYNC 1K 1K 1K 1K 1K 1K 1K
TXOUT1_U1N TXC3P 5V_HDMI_2 U4
AE19 R143 22
AON_VSYNC
TXOUT1_U1P TXC3N OPT AD15
AF19 FOR HDMI STANDARD 5V_HDMI_3 TRSTB
TXOUT1_U2N TXCCLKP APPLY ONLY WHEN CONNECT TO PULL-UP GPIO OPT W3 AF14
AH19 R144 22
AON_GPIO_36 TDI/GPIO
TXOUT1_U2P TXCCLKN R130 5V_HDMI_4 R145 22 W1 AH14
AE18 OPT 2K AON_GPIO_37 TDO R163
TXCLK1_UN TXC2P OPT AD14 1K
AD18 +3.3V_Normal TMS/GPIO
TXCLK1_UP TXC2N AB6 AG14
AG19 AON_RESETOUTB TCK/GPIO
TXOUT1_U3N TXC1P R132 4.7K Y6 AC16
AF18 TVM_BYPASS DINT/GPIO
TXOUT1_U3P TXC1N
AG18 R139 0
TXOUT1_U4N TXC0P SRST
AF17
TXOUT1_U4P TXC0N +3.3V_Normal +3.3V_Normal Y3 AH7
SOC_RESET RESETB AVS_VFB
G24 AG7
RESETOUTB AVS_VSENSE
AD7 SRST
AC18 R194 R124 AVS_RESETB
LT0VCAL_MONITOR 2.7K 1K J6 AF7
AH16 OPT TMODE AVS_NDRIVE_1
GPIO_BL_ON W6 AH8
AG16 R108 10K TESTEN AVS_PDRIVE_1
BL_PWM/GPIO A_DIM +3.3V_Normal
R125
C105 1K
2.2uF C111 0.01uF F7 C6
10V VDAC_VREG VDAC_1 DTV/MNT_V_OUT
E7 D7
C112 0.1uF VDAC_RBIAS VDAC_2
R140
560
1%

BCM REFRENCE is 562ohm

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230 2010.09.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN & NAND FLASH 01

Copyright © 2011 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
POWER 2.5V
+2.5V_BCM35230 ADAC_AVDD25 CORE 0.9V
+2.5V_BCM35230 AADC_AVDD25
+0.9V_CORE HDMI_AVDD +0.9V_CORE USB_AVDD +0.9V_CORE VAFE2_DVDD
L202 L205 L209
BLM18PG121SN1D BLM18PG121SN1D L214 L219
+3.3V_Normal
BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
+0.9V_CORE +0.9V_CORE
NFM18PS105R0J NFM18PS105R0J C249 C253 C256 C258
C233 C204 10uF 10uF 0.1uF 0.1uF C280 C284 C285 C288 C292 C296 C299
C261 C263 C267 C271 C274 22uF 22uF 4.7uF 0.1uF
6.3V 6.3V 10V 10V 10uF 4.7uF 0.1uF 0.01uF 22uF 0.1uF 4.7uF 0.1uF
C225 C221 C223 C247 10V
BCM_FRC/URSA5

0.22uF 0.1uF 0.01uF IN OUT IN OUT 22uF


6.3V
S_TUNER
T2_TUNER
FRC2/URSA5

GND GND
R254

R256

R257
R253

R255

PHM
R251

R252

OLED
R250

FHD

1K

1K

1K
1K

1K
1K

1K
1K

+2.5V_BCM35230 EPHY_VDD25 +2.5V_BCM35230


+0.9V_CORE PLL_AUD_AVDD +0.9V_CORE VAFE3_DVDD +0.9V_CORE PLL_MAIN_AVDD
L203
BLM18PG121SN1D L210 L215 L217
NFM18PS105R0J +3.3V_Normal BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
MODEL_OPT_0 C244 C259 C260 C262 C266 C270 C272
6.3V C251 C252 C255
0.1uF 4.7uF 0.1uF 10uF 4.7uF 10uF 4.7uF 0.1uF 0.01uF C277 C281 C294 C297
MODEL_OPT_1 16V 10V 10V 4.7uF 0.1uF C287 C290 4.7uF 0.1uF
C232 C234 C236 C238 IN OUT C248 4.7uF 0.1uF
MODEL_OPT_2 4.7uF 0.1uF 0.1uF 4.7uF 10uF
10V 10V GND 10V
MODEL_OPT_3
MODEL_OPT_4
+2.5V_BCM35230 VAFE2_VDD25
MODEL_OPT_5 +0.9V_CORE PLL_MIPS_AVDD
L206 +0.9V_CORE PLL_VAFE_AVDD
+1.5V_DDR
MODEL_OPT_6 BLM18PG121SN1D L211 L218
BLM18PG121SN1D BLM18PG121SN1D
MODEL_OPT_7
NO_FRC/BCM_FRC

NO_FRC/FRC2

NO_T2_TUNER

NO_S_TUNNER

C295 C298
C203 C205 C207 C209 C211 C213 C215 C220 C222 C265 C269 C279 C282 4.7uF 0.1uF
NO_PHM
R260

R265
R261

10uF 10uF 4.7uF 4.7uF 0.1uF 0.1uF 0.01uF 0.1uF 0.01uF 4.7uF 0.1uF 4.7uF 0.1uF
R262

R263

R264

R266

R267
LCD

OPT
HD

10V 10V
1K

1K

10V 10V
1K

1K

1K

1K

1K

1K

+2.5V_BCM35230 VAFE3_VDD25 +2.5V_BCM35230 PLL_VAFE_AVDD25


L204 L207
BLM18PG121SN1D BLM18PG121SN1D

C254 C257 C264 C268 POWER 3.3V


C250
4.7uF 4.7uF 0.1uF 4.7uF 0.1uF
MODEL OPTION 10V +3.3V_Normal USB_AVDD33 +3.3V_Normal HDMI_AVDD33
BCM L212 L216
external
NO_FRC internal LG FRC2 BLM18PG121SN1D BLM18PG121SN1D
URSA5
FRC
C283
MODEL_OPT_0 0 0 1 1 C291 C293
0.1uF
4.7uF 0.1uF
MODEL_OPT_1 0 1 0 1

HIGH LOW IC101


+0.9V_CORE LGE35230(BCM35230KFSBG)
MODEL_OPT_2 FHD HD
+3.3V_Normal VDAC_AVDD33
MODEL_OPT_3 OLED LCD BCM_WITHOUT_CAP
L213
V12 K10 BLM18PG121SN1D
MODEL_OPT_4 DDR speed 1333 1600 VDDC_1 VSS_1
V7 K11
VDDC_2 VSS_2
MODEL_OPT_5 T2 Tuner Support Not Support M10 K12
VDDC_3 VSS_3 C286 C289
N10 L12 4.7uF 0.1uF
MODEL_OPT_6 S Tuner Support Not Support VDDC_4 VSS_4
P10 M12
VDDC_5 VSS_5
MODEL_OPT_7 PHM Enable Disable R10 N12
VDDC_6 VSS_6
T10 P12
VDDC_7 VSS_7
U10 R12
VDDC_8 VSS_8
V10 T12
close to soc VDDC_9 VSS_9
W10 U12
IC101 C217 V13
VDDC_10 VSS_10
W12
LGE35230(BCM35230KFSBG) 16V
L11
VDDC_11 VSS_11
K13
0.1uF 100
Non_CHB R241 +3.3V_Normal VDDC_12 VSS_12
M11 L13
IF_P VDDC_13 VSS_13 IC101
BCM_WITHOUT_CAP R212 L201 N11 M13
F26 C17 1K C218
100 P11
VDDC_14 VSS_14
N13
LGE35230(BCM35230KFSBG)
EPHY_VREF VI_IFP0 0.1uF R242 BLM18PG121SN1D
D26 B17 16V VDDC_15 VSS_15 AADC_AVDD25
EPHY_RDAC VI_IFM0 IF_N R11 P13
R211 D15 VDDC_16 VSS_16 BCM_WITHOUT_CAP
VDDR_AGC +3.3V_Normal T11 R13
6.04K F27 VDDC_17 VSS_17 F19 F20
EPHY_TDP EPHY_TDP C229 U11 T13 AADC_AVDD25 AADC_AVSS
F28 B16 closed to soc VDDC_18 VSS_18 ADAC_AVDD25
0.1uF V11 U13
EPHY_TDN EPHY_TDN AGC_SDM_2
E27 A16 R213 2K VDDC_19 VSS_19 D25 G22
EPHY_RDP EPHY_RDP AGC_SDM_1 IF_AGC R233 R234 W11 W16 ADACA_AVDD25 ADACA_AVSS
E26 C216 0.01uF 1.2K 1.2K VDDC_20 VSS_20 D24 G21
EPHY_RDN EPHY_RDN V14 K14 ADACC_AVDD25 ADACC_AVSS
A15 VDDC_21 VSS_21 E24 F22
GPIO_0 SDA1_3.3V L18 L14 ADACD_AVDD25 ADACD_AVSS
C16 VDDC_22 VSS_22 EPHY_VDD25
GPIO_1 SCL1_3.3V M18 M14
F5 G28 VDDC_23 VSS_23 F24 F23
USB_MONCDR GPIO_2 3D_SYNC C227 C231 N18 N14 EPHY_BVDD25 EPHY_AVSS
+3.3V_Normal E5 G26 33pF 33pF NON_NTP VDDC_24 VSS_24 E25
USB_RREF GPIO_3 NON_NTP P18 P14 EPHY_AVDD25
C201 R210 50V 50V VDDC_25 VSS_25
100pF 4.87K +3.3V_Normal R18 R14
1% C2 VDDC_26 VSS_26 HDMI_AVDD
OPT SIDE_USB_DM USB_PORT1DN T18 T14
R287 D1 W14 VDDC_27 VSS_27
10K SIDE_USB_DP USB_PORT1DP PCI_VIO_0 U18 U14 HDMI_AVDD33
W15 VDDC_28 VSS_28 D5 F6
WIFI PCI_VIO_1 V18 K15 HDMI0_AVDD HDMI0_AVSS_1
E1 W13 VDDC_29 VSS_29 D4 G6
SIDE_USB_OCD1 USB_PWRFLT_1/GPIO PCI_VIO_2 W18 L15 +2.5V_BCM35230 HDMI0_AVDD33 HDMI0_AVSS_2
D2 VDDC_30 VSS_30
SIDE_USB_CTL1 USB_PWRON_1/GPIO V15 M15
VDDC_31 VSS_31 AE20 AB22
R286 L19 N15 LT0VDD25_1 LT0VSS_1
10K B1 J5 R280 VDDC_32 VSS_32 AD20 AB21
WIFI_DM USB_PORT2DN GPIO_4 M_REMOTE_RX M19 P15 LT0VDD25_2 LT0VSS_2
WIFI C1 R5 22 VDDC_33 VSS_33 AC20 AB19
WIFI_DP USB_PORT2DP GPIO_5 MODEL_OPT_0 N19 R15 +2.5V_BCM35230 LT0VDD25_3 LT0VSS_3
V6 VDDC_34 VSS_34 AB20 AC19
GPIO_6 CI_DET P19 T15 LT0VDD25_4 LT0VSS_4
C3 H6 VDDC_35 VSS_35 AB18
SIDE_USB_OCD2 USB_PWRFLT_2/GPIO GPIO_7 M_RFModule_RESET R19 U15 LT0VSS_5
C4 AE15 VDDC_36 VSS_36 C275 AB17
SIDE_USB_CTL2 USB_PWRON_2/GPIO GPIO_70 EPHY_ACTIVITY T19 K16 LT0VSS_6
AF15 VDDC_37 VSS_37 0.1uF AC17
GPIO_71 EPHY_LINK U19 L16 OPT LT0VSS_7
PCM_TS_DATA[0-7] AG15 R214 22 +3.3V_Normal VDDC_38 VSS_38
GPIO_72 DTV_ATV_SELECT V19 M16
M4 AF16 R215 22 VDDC_39 VSS_39 USB_AVDD D14 SPDIF_IN_AVDD25 F15
PCM_TS_CLK TCLKA/GPIO GPIO_73 RF_SWITCH_CTL_2 +1.5V_DDR W19 N16
L5 AD16 R281 22 VDDC_40 VSS_40 SPDIF_IN_AVSS
PCM_TS_DATA[0] R240 V16 P16
TDATA_0/GPIO GPIO_74 MODEL_OPT_1 USB_AVDD33
PCM_TS_DATA[1] M5 AE16 R282 22 2.7K VDDC_41 VSS_41 E4 G7
TDATA_1/GPIO GPIO_75 MODEL_OPT_2 V17 R16 USB_AVDD USB_AVSS_1
PCM_TS_DATA[2] L6 AG17 R216 22 Place Cap VDDC_42 VSS_42 VDAC_AVDD33 D3 G8
TDATA_2/GPIO GPIO_76 MODEL_OPT_3 Very close to R22 Ball T16 USB_AVDD33 USB_AVSS_2
PCM_TS_DATA[3] N3 AH17 R228 22 VSS_43
TDATA_3/GPIO GPIO_77 PWM_DIM L10 U16
PCM_TS_DATA[4] N1 AE17 R230 22 MLG1005S22NJT POR_VDD VSS_44 VAFE2_DVDD D6 G9
TDATA_4/GPIO GPIO_78 L/DIM0_VS K17 VDAC_AVDD33 VDAC_AVSS
PCM_TS_DATA[5] N2 AD17 BCM_L/DIM C224 C226 VSS_45 VAFE2_VDD25
OPT TDATA_5/GPIO GPIO_79 INSTANT_MODE L220 L17
R201 0 PCM_TS_DATA[6] M3 1uF 0.1uF VSS_46 D18 G20
TDATA_6/GPIO L22 M17 VAFE2_DVDD VAFE2_VSS_1
M2 25V 16V VDDR1_1 VSS_47 E17 E18
PCM_TS_DATA[7] OPT OPT AA28 N17
TDATA_7/GPIO Place as close as possible to the pad VAFE2_AVDD25_1 VAFE2_VSS_2
L4 AB13 +3.3V_Normal VDDR1_2 VSS_48 C212 C214 D16 G18
PCM_TS_SYNC TSTRTA/GPIO PCI_AD05 V28 P17 VAFE2_AVDD25_2 VAFE2_VSS_3
N4 AC15 VDDR1_3 VSS_49 VAFE3_DVDD 390pF 390pF D17 G17
URSA5_RESET

R28 R17
FRC2_RESET

PCM_TS_VAL TVLDA/GPIO PCI_AD06 50V 50V VAFE2_DVDD25 VAFE2_VSS_4


AB12 VDDR1_4 VSS_50 F18
R232-*1

FE_TS_DATA[0-7] F/NIM_EU_CN PCI_AD07 M28 T17 VAFE3_VDD25 VAFE2_VSS_5


R202 K6 AB11 VDDR1_5 VSS_51 D9 G16
J28 U17
4.7K

TU_TS_CLK
4.7K
R232

0 TCLKD/GPIO PCI_AD08 VAFE3_DVDD VAFE2_VSS_6


FE_TS_DATA[0] J4 AE14 R231-*1 0 VDDR1_6 VSS_52 D8 F16
TDATD_0/GPIO PCI_AD09/GPIO SC_DET/COMP2_DET K23 W17 VAFE3_AVDD25_1 VAFE2_VSS_7
FE_TS_DATA[1] R203 0 F/NIM_EU_CN K5 AG13 VDDR1_7 VSS_53 E8
TDATD_1/GPIO PCI_AD10/GPIO CHB_RESET FRC2_RESET M22 K18 C208 C210 VAFE3_AVDD25_2
F/NIM_EU_CN J2 AH13 VDDR1_8 VSS_54 use only for A0/B0 chip F9 G13
FE_TS_DATA[2] R204 0 R231 100 FRC_RESET T22 K19 390pF 390pF
TDATD_2/GPIO PCI_AD11/GPIO VAFE3_AVDD25_3 VAFE3_VSS_1
FE_TS_DATA[3] R205 0 F/NIM_EU_CN J3 AF13 VDDR1_9 VSS_55 C210-*1 50V 50V E9 G12
TDATD_3/GPIO PCI_AD12/GPIO TW9910_RESET URSA5_RESET T23 H7 VAFE3_DVDD25 VAFE3_VSS_2
VDDR1_10 VSS_56 220pF BCM_C0
FE_TS_DATA[4] R206 0 F/NIM_EU_CN K2 AE13 F8 F12
TDATD_4/GPIO PCI_AD13/GPIO AV2_CVBS_DET Place Cap U22 G14 50V POR_VDD25 VAFE3_VSS_3
FE_TS_DATA[5] R207 0 F/NIM_EU_CN K1 AD12 R218 22 Very close to R22 Ball VDDR1_11 VSS_57 PLL_AUD_AVDD G11
TDATD_5/GPIO PCI_AD14/GPIO RF_BOOSTER_CTL Y22 AB16 BCM_A0/B0 VAFE3_VSS_4
F/NIM_EU_CN K3 AF12 VDDR1_12 VSS_58 Place as close as possible to the pad G10
FE_TS_DATA[6] R208 0 DSUB_DET C242 R7 PLL_MAIN_AVDD
TDATD_6/GPIO PCI_AD15/GPIO VAFE3_VSS_5
FE_TS_DATA[7] R209 0 F/NIM_EU_CN L1 AG10 0.1uF VSS_59 G25 F10
TDATD_7/GPIO PCI_AD16/GPIO PCM_RST R22 M6 PLL_AUD_AVDD VAFE3_VSS_6
CHBO_TS_CLK L3 AF10 DDR_LDO_VDDO VSS_60 PLL_MIPS_AVDD K4
TU_TS_SYNC R220 22 MODEL_OPT_4 AB23 PLL_VAFE_AVDD
CHBO_TS_SERIAL TSTRTD/GPIO PCI_AD17/GPIO PLL_MAIN_AVDD
L2 AE10 +3.3V_Normal VSS_61 AD25
TS_VAL_ERR TVLDD/GPIO PCI_AD18/GPIO DC_MREMOTE P7 PLL_MIPS_AVDD
CHBO_TS_SYNC AD10 VSS_62 PLL_VAFE_AVDD25 D11 AD26
PCI_AD19/GPIO DD_MREMOTE G15 W7 PLL_MIPS_AVSS
CHBO_TS_VAL_ERR AE9 VDDR3_1 VSS_63 D12 PLL_VAFE_AVDD
PCM_MDI[0-7] R221 22 BCM_L/DIM L/DIM0_MOSI H22 J7
PCI_AD20/GPIO +0.9V_CORE PLL_VAFE_AVDD25
P4 AE8 R222 22 BCM_L/DIM VDDR3_2 VSS_64
PCM_MCLKI MPEG_CLK/GPIO PCI_AD21/GPIO L/DIM0_SCLK G23 N7
PCM_MDI[0] T2 AC10 VDDR3_3 VSS_65 AE7 AC7
MPEG_D_0/GPIO PCI_AD22 AB9 AB10 TVM_OSC_AVDD TVM_OSC_AVSS
PCM_MDI[1] R3 AC11 VDDR3_4 VSS_66 C273
MPEG_D_1/GPIO PCI_AD23 K7 AC23 C276 +3.3V_Normal
PCM_MDI[2] R2 AC8 VDDR3_5 VSS_67 C202 C206 0.1uF 0.01uF U6
MPEG_D_2/GPIO PCI_AD24 AB15 AC6 AUX_AVDD33
P3 AB8 VDDR3_6 VSS_68 390pF 390pF OPT
PCM_MDI[3] L7 G19 50V 50V
MPEG_D_3/GPIO PCI_AD25
PCM_MDI[4] P2 VDDR3_7 VSS_69
MPEG_D_4/GPIO AB14 AA22
PCM_MDI[5] P1 AC14 VDDR3_8 VSS_70 C278
MPEG_D_5/GPIO PCI_CBE00 M7 J23
R6 AG12 VDDR3_9 VSS_71 0.1uF
PCM_MDI[6] R283 COMP1_DET N6 J22
MPEG_D_6/GPIO PCI_CBE01/GPIO 22
PCM_MDI[7] N5 AH10 VDDR3_10 VSS_72
MPEG_D_7/GPIO PCI_CBE02/GPIO MODEL_OPT_5 P6 K22
T4 AB7 VDDR3_11 VSS_73
PCM_MISTRT MPEG_SYNC/GPIO PCI_CBE03 +0.9V_CORE J25 Place as close as possible to the pad
P5 VSS_74
PCM_MIVAL_ERR MPEG_DATA_EN/GPIO N22
AG11 R223 22 VSS_75
PCI_DEVSELB/GPIO 3D_GPIO_0 +3.3V_Normal AA6 N23
AD11 R284 22 AON_VDDC_1 VSS_76
PCI_FRAMEB/GPIO MODEL_OPT_6 AA7 M25
R4 AE11 R224 22 AON_VDDC_2 VSS_77
MCIF_RESET/GPIO PCI_IRDYB/GPIO MODEL_OPT_7 Y7 P22
U1 AD13 AON_POR_VDD VSS_78
MCIF_SCLK/GPIO PCI_PAR/GPIO R25
T3 AE12 R235 100 VSS_79
MCIF_SCTL/GPIO PCI_PERRB/GPIO ERROR_OUT U7 V22
T1 AC12 R225 0 OPT AON_VDDR3 VSS_80
/PCM_IRQA MCIF_SDI/GPIO PCI_REQ1B W22
T5 AC13 R226 22 VSS_81
MCIF_SDO/GPIO PCI_SERRB/GPIO RF_SWITCH_CTL T7 W23
AH11 R285 22 AON_VDDR10_1 VSS_82
PCI_STOPB/GPIO 3D_GPIO_1 T6 V25
AF11 R227 22 AON_VDDR10_2 VSS_83
PCI_TRDYB/GPIO 3D_GPIO_2 AA25
VSS_84

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN POWER 02

Copyright © 2011 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC101
C320 0.1uF LGE35230(BCM35230KFSBG)
DSUB_R+
INCM_R C321 0.1uF
R311 DSUB_G+ C327 0.1uF
BCM_WITHOUT_CAP
36 C328 0.1uF B6
INCM_G
VI_R
R317 A6
36 VI_INCM_R
C7
VI_G
A7

DSUB_B+ C322 0.1uF B7


C8
VI_INCM_G
VI_B
BCM35230_with_CAP_220pF
INCM_B C323 0.1uF
VI_INCM_B
R312 IC101-*1
36 C13
DSUB_HSYNC HSYNC_IN
LGE35230
A13
DSUB_VSYNC VSYNC_IN
BCM_WITH_CAP
C9
COMP1_Y C329
C330
0.1uF
0.1uF A9
VI_Y1 VIDEO INCM B6
A6
VI_R
COMP1_Pr VI_PR1 VI_INCM_R
C331 0.1uF B9 C7
COMP1_Pb VI_PB1 VI_G
C332 0.1uF B8 A7
INCM_VID_COMP1 VI_INCM_COMP1 VI_INCM_G
R310 B7
0 Run Along DSUB_R Trace VI_B
C333 0.1uF C11 Near P801 INCM_R C8
SC_R/COMP2_Pr VI_SC_R1 VI_INCM_B
C334 0.1uF A10
SC_G/COMP2_Y VI_SC_G1 Run Along DSUB_G Trace
C335 0.1uF B10 Near P801 INCM_G C13
SC_B/COMP2_Pb VI_SC_B1 HSYNC_IN
C336 0.1uF C10 A13
INCM_VID_SC/COMP2 VI_INCM_SC1 Run Along DSUB_B Trace VSYNC_IN
R318 Near P801 INCM_B
0 D10
SC_FB C9
VI_FB_1/GPIO Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace VI_Y1
F13 Near JK1101 INCM_VID_COMP1 A9
VI_FS1 VI_PR1
B9
Run Along AV2_CVBS Trace VI_PB1
A12 Near JK1104 INCM_VID_AV2 B8
VI_SC_R2 VI_INCM_COMP1
C12
VI_SC_G2 Run Along TUNER_CVBS_IF_P Trace
B12 Near TU2101/2
TU2201/2/3
INCM_TUNER C11
VI_SC_B2 VI_SC_R1
B11 A10
VI_INCM_SC2 Run Along AV1_CVBS Trace VI_SC_G1
Near JK1102 INCM_VID_AV1 B10
E12 VI_SC_B1
JK1103 Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace C10
VI_FB_2/GPIO Near INCM_VID_SC/COMP2 VI_INCM_SC1
E14 JK2501
VI_FS2
D10
E15 VI_FB_1/GPIO
F13
VI_L1 VI_FS1
F17
VI_C1_1
E16 A12
VI_INCM_LC1_1 VI_SC_R2
SC_CVBS_IN F14 C12
VI_C1_2 VI_SC_G2
INCM_VID_SC E11 B12
C303 0.1uF VI_INCM_LC1_2 VI_SC_B2
AV2_CVBS_IN B11
INCM_VID_AV2 C304 0.1uF C18 VI_INCM_SC2
NON_EU VI_CVBS1
R303 R325 0 B18
36 TU_CVBS C325 0.1uF E12
VI_INCM_CVBS1 VI_FB_2/GPIO
C326 0.1uF A18 E14
EU INCM_TUNER VI_CVBS2 VI_FS2
R306 R316 C19
R325-*1 VI_INCM_CVBS2
75 36 A19
10 1% E15
OPT VI_CVBS3 VI_L1
B19 F17
VI_INCM_CVBS3 VI_C1_1
C317 0.1uF C20 E16
AV1_CVBS_IN VI_CVBS4 VI_INCM_LC1_1
C318 0.1uF B20 F14
INCM_VID_AV1 VI_INCM_CVBS4 VI_C1_2
R304 +2.5V_BCM35230 E11
36 E19 VI_INCM_LC1_2
VI_SIF1_1
D19 C18
R313 VI_INCM_SIF1_1 VI_CVBS1
10K E10 B18
VI_SIF1_2 VI_INCM_CVBS1
C319 0.1uF F11 A18
TU_SIF VI_INCM_SIF1_2 VI_CVBS2
C19
R305 R314 +2.5V_BCM35230 VI_INCM_CVBS2
240 12K A19
OPT VI_CVBS3
B19
R319 VI_INCM_CVBS3
10K C20
OPT VI_CVBS4
B20
C324 0.1uF VI_INCM_CVBS4
INCM_SIF
R315 R320 E19
120 12K VI_SIF1_1
OPT OPT D19
VI_INCM_SIF1_1
E10
VI_SIF1_2
F11
VI_INCM_SIF1_2

IC101
LGE35230(BCM35230KFSBG)

BCM_WITHOUT_CAP
B15 AF8 R326 100
SPDIF_INC_P I2SSCK_OUTA/GPIO AUD_SCK
C15 AF9 R327 100
+3.3V_Normal SPDIF_INC_N I2SWS_OUTA/GPIO AUD_LRCK
AG9 R328 100
I2SSD_OUTA0/GPIO AUD_LRCH
C14 AC9 R329 100
SPDIF_IND_P I2SSOSCK_OUTA/GPIO AUD_MASTER_CLK
B14 AD8
SPDIF_IND_N I2SSD_OUTA1/GPIO TU_RESET_SUB C337 C338 C339 C340
R301 R302 AD9 22pF 22pF
I2SSD_OUTA2/GPIO 22pF 33pF
1.2K 1.2K G4
M_REMOTE_TX OPT OPT OPT OPT
I2SSCK_IN/GPIO
F4 E2
SCL3_3.3V I2SWS_IN I2SSCK_OUTC/GPIO HP_DET
G5 F2
SDA3_3.3V I2SSD_IN/GPIO I2SWS_OUTC/GPIO AV1_CVBS_DET
C301 C302 E3
I2SSD_OUTC/GPIO TU_RESET
33pF 33pF F3
50V 50V I2SSOSCK_OUTC/GPIO
C305 1uF 10V C25
PC_L_IN AADC_LINE_L1
C306 1uF 10V B24 G2
PC_R_IN AADC_LINE_R1 I2SSCK_OUTD/GPIO SC_RE1
C307 1uF 10V A24 G3
INCM_AUD_PC AADC_INCM1 I2SWS_OUTD/GPIO SC_RE2
I2SSD_OUTD/GPIO
G1
/RST_HUB AUDIO INCM
C308 1uF 10V E22 H1
PHONE JACK AV1_L_IN AADC_LINE_L2 I2SSOSCK_OUTD/GPIO S2_RESET
C309 1uF 10V E23
AV1_R_IN AADC_LINE_R2
C310 1uF 10V D23
INCM_AUD_AV1 AADC_INCM2
B13 Route Between AV1_L_IN & AV1_R_IN Trace
C24
SPDIF_OUTA/GPIO SPDIF_OUT Near JK1102 R321 0 INCM_AUD_AV1
AV2_L_IN C311 1uF 10V
AADC_LINE_L3
C312 1uF 10V C23 AG8 Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace
AV2_R_IN AADC_LINE_R3 AUDMUTE_0/GPIO Near JK1103 R322 0
B23 E13 INCM_AUD_SC/COMP2
C313 1uF 10V JK2501
INCM_AUD_AV2 AADC_INCM3 AUDMUTE_1
R323 0 Route Between AV2_L_IN & AV2_R_IN Trace
E21 C28 Near JK1104 INCM_AUD_AV2
SC/COMP2_L_IN C314 1uF 10V HP_LOUT_N
AADC_LINE_L4 ADAC_AL_N
C315 1uF 10V D21 C27 Route Between PC_L_IN & PC_R_IN Trace
SC/COMP2_R_IN
D22
AADC_LINE_R4 ADAC_AL_P HP_LOUT_P Near JK801 R324 0 INCM_AUD_PC
INCM_AUD_SC/COMP2 C316 1uF 10V
AADC_INCM4
D28
ADAC_AR_N HP_ROUT_N
B22 D27
AADC_LINE_L5 ADAC_AR_P HP_ROUT_P
C22
AADC_LINE_R5
A22 C26
AADC_INCM5 ADAC_CL_N SCART1_Lout_N Near TU2101/2
TU2201/2/3
Route Along With TUNER_SIF_IF_N
INCM_SIF
A27
ADAC_CL_P SCART1_Lout_P
F21
AADC_LINE_L6
D20 B27
AADC_LINE_R6 ADAC_CR_N SCART1_Rout_N
E20 B28
AADC_INCM6 ADAC_CR_P SCART1_Rout_P

A21 B25
AADC_LINE_L7 ADAC_DL_N
C21 A25
AADC_LINE_R7 ADAC_DL_P
B21
AADC_INCM7
A26
ADAC_DR_N
B26
ADAC_DR_P

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
MAIN AUDIO/VIDEO
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 03

Copyright © 2011 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DDR STRAP DUAL COMPONENT
DDR_DQ[0] +1.5V_DDR
DDR_DQ[1] NFM18PS105R0J IC401,IC402 1ST : EAN61667501, 2ND : EAN61570701
DDR_DQ[2] C410
6.3V
DDR_DQ[3] IC401-*1
DDR_DQ[4]
C403 C405 C407 C417 1ST : T-K4B2G1646B_HCK0, 2ND : T-H5TQ2G63BFR-PBC
2.2uF 10uF 2.2uF IN OUT 470pF IC402-*1
GND +1.5V_DDR
NFM18PS105R0J
JEDEC Types : DDR_DQ[0:4] C432
R401 R403 R405 R407 R409 6.3V
4.7K 4.7K 4.7K 4.7K 4.7K 00001 : DDR3-1333H (CasL=9)
OPT
DDR_1333 DDR_1333 10101 : DDR3-1600K (CasL=11) (O) +1.5V_DDR C421 C423 C425
NFM18PS105R0J 2.2uF 10uF 10uF IN OUT
C402 GND
6.3V

C412
IN OUT 1uF
DDR_DQ[10]
GND +1.5V_DDR
DDR_DQ[9]
NFM18PS105R0J
DDR_DQ[7]
C433
DDR_DQ[8] 6.3V
+1.5V_DDR
DDR_DQ[6] C426
DDR_DQ[5] Bus Width : DDR_DQ[10] IN OUT 1uF
0 - 16b GND
R402 R432 R404 R406 R408 R410 1 - 32b (O)
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K Chip Width : DDR_DQ[8]
OPT OPT OPT OPT C453 C454 C455
OPT
0 - 8b 1uF 1uF 1uF
6.3V 6.3V 6.3V
1 - 16b (O)
Chip Size : DDR_DQ[6:5]
00 - 4Gbit
01 - 2Gbit (O)
10 - 1Gbit
11 - 512Mbit
+1.5V_DDR +1.5V_DDR
IC401 IC402
K4B2G1646C R416 K4B2G1646C R422
4.99K 4.99K
1% 1%

N3 DDR_1333_SS M8 N3 M8 +1.5V_DDR
DDR_AA0 A0 VREFCA C415 R417 DDR_AA0 A0 DDR_1333_SS VREFCA C435 R423
IC101 P7 4.99K P7 4.99K
DDR_AA1 0.01uF 1% DDR_AA1 0.01uF 1%
A1 A1
LGE35230(BCM35230KFSBG) P3 P3
DDR_AA2 A2 DDR_AA2 A2 R430
N2 H1 N2 H1 4.7K
DDR_DQ[0-7] BCM_WITHOUT_CAP DDR_AA3 A3 VREFDQ C416 DDR_VREFA DDR_AA3 A3 VREFDQ C436 DDR_VREFA OPT
P8 P8 R429
DDR01_AA4 A4 0.01uF DDR23_AA4 A4 0.01uF 82
DDR_DQ[0] U26 V23 P2 P2 DDR_RESETb
DDR_DQA_0 DDR_ADA_0 DDR_AA0 DDR01_AA5 A5 DDR23_AA5 A5
DDR_DQ[1] R26 AB27 R8 L8 R415 240 R8 L8 R421 240
DDR_DQA_1 DDR_ADA_1 DDR_AA1 DDR01_AA6 A6 ZQ DDR23_AA6 A6 ZQ C442
DDR_DQ[2] U27 Y23 R2 1% +1.5V_DDR R2 1% +1.5V_DDR 100pF
DDR_DQA_2 DDR_ADA_2 DDR_AA2 DDR_AA7 A7 DDR_AA7 A7
DDR_DQ[3] R27 Y26 T8 T8
DDR_DQA_3 DDR_ADA_3 DDR_AA3 DDR_AA8 A8 DDR_AA8 A8 R428
DDR_DQ[4] V27 R3 B2 R3 B2 82
DDR_DQA_4 DDR_AA9 A9 VDD_1 DDR_AA9 A9 VDD_1
DDR_DQ[5] P26 AB26 L7 D9 L7 D9 DDR_CKE
DDR_DQA_5 DDR_ADA_4 DDR01_AA4 DDR_AA10 A10/AP VDD_2 DDR_AA10 A10/AP VDD_2 C437 R431
DDR_DQ[6] U25 Y24 R7 G7 R7 G7 4.7K
DDR_DQ[8-15] DDR_DQA_6 DDR_ADA_5 DDR01_AA5 DDR_AA11 A11 VDD_3 DDR_AA11 A11 VDD_3 100pF
P27 AC26 N7 K2 N7 K2 OPT
DDR_DQ[7] DDR01_AA6 DDR_AA12 DDR_AA12
DDR_DQA_7 DDR_ADA_6 A12/BC VDD_4 A12/BC VDD_4
DDR_DQ[8] R24 T3 K8 T3 K8
DDR_DQA_8 DDR_AA13 A13 VDD_5 DDR_AA13 A13 VDD_5
DDR_DQ[9] N24 AB24 N1 N1
DDR_DQA_9 DDR_ADA_ALT_4 DDR23_AA4 VDD_6 VDD_6
DDR_DQ[10] T25 AC25 M7 N9 M7 N9
DDR_DQA_10 DDR_ADA_ALT_5 DDR23_AA5 NC_5 VDD_7 NC_5 VDD_7 DDR_AA13 R424 56
DDR_DQ[11] M23 AC24 R1 R1
DDR_DQA_11 DDR_ADA_ALT_6 DDR23_AA6 VDD_8 VDD_8 DDR_AA14 R425 56 OPT
DDR_DQ[12] R23 M2 R9 M2 R9
DDR_DQA_12 DDR_BAA0 BA0 VDD_9 DDR_BAA0 BA0 VDD_9 C438 1uF
DDR_DQ[13] N25 AB25 N8 N8 AR401 56
DDR_DQA_13 DDR_ADA_7 DDR_AA7 DDR_BAA1 BA1 DDR_BAA1 BA1 DDR_AA2
DDR_DQ[14] T24 AD28 M3 M3
DDR_DQ[16-23] DDR_DQA_14 DDR_ADA_8 DDR_AA8 DDR_BAA2 BA2 DDR_BAA2 BA2 C404 0.1uF
N26 Y25 A1 A1 DDR_AA11
DDR_DQ[15] DDR_AA9
DDR_DQA_15 DDR_ADA_9 VDDQ_1 VDDQ_1 DDR_AA3
DDR_DQ[16] L26 AA27 J7 A8 J7 A8
DDR_DQA_16 DDR_ADA_10 DDR_AA10 CK VDDQ_2 DDR23_CLK CK VDDQ_2 DDR_AA7 C406 0.1uF
DDR_DQ[17] H27 AC27 K7 C1 K7 C1 AR402 56
DDR_DQA_17 DDR_ADA_11 DDR_AA11 DDR01_CLK CK VDDQ_3 DDR23_CLKb CK VDDQ_3
DDR_DQ[18] L27 AA26 K9 C9 K9 C9
DDR_DQA_18 DDR_ADA_12 DDR_AA12 R412 DDR01_CLKb
R413 DDR_CKE CKE VDDQ_4 R418 R419 DDR_CKE CKE VDDQ_4 DDR_AA9
DDR_DQ[19] J26 AA24 56 56 D2 56 56 D2 C450 0.1uF
DDR_DQA_19 DDR_ADA_13 DDR_AA13 1% 1% VDDQ_5 1% 1% VDDQ_5 DDR_AA8
DDR_DQ[20] M27 AD27 +1.5V_DDR L2 E9 +1.5V_DDR L2 E9
DDR_DQA_20 DDR_ADA_14 DDR_AA14 CS VDDQ_6 CS VDDQ_6 C408 0.1uF
G27 K1 F1 K1 F1 DDR_AA0
DDR_DQ[21] C401 R414 10K ODT C419 R420 10K ODT AR403 56
DDR_DQA_21 VDDQ_7 VDDQ_7 DDR_AA1
DDR_DQ[22] M26 Y27 1000pF J3 H2 1000pF J3 H2 C439
DDR_DQ[24-31] DDR_DQA_22 DDR_BAA_0 DDR_BAA0 DDR_RASb RAS VDDQ_8 DDR_RASb RAS VDDQ_8 DDR_BAA0 1uF
DDR_DQ[23] H26 AB28 K3 H9 K3 H9
DDR_DQA_23 DDR_BAA_1 DDR_BAA1 DDR_CASb CAS VDDQ_9 DDR_CASb CAS VDDQ_9 DDR_BAA2
DDR_DQ[24] L23 W24 L3 L3
DDR_DQA_24 DDR_BAA_2 DDR_BAA2 DDR_WEb WE DDR_WEb WE DDR_BAA1 C409 0.1uF
DDR_DQ[25] H25 J1 J1 AR404 56
DDR_DQA_25 NC_1 NC_1 DDR_AA10
DDR_DQ[26] L24 V24 T2 J9 T2 J9 C451 0.1uF
DDR_DQA_26 DDR_RASA_N DDR_RASb DDR_RESETb RESET NC_2 DDR_RESETb RESET NC_2 DDR_AA12
DDR_DQ[27] J24 W25 L1 L1
DDR_DQA_27 DDR_CASA_N DDR_CASb NC_3 NC_3 DDR_WEb
DDR_DQ[28] M24 V26 L9 L9
DDR_DQA_28 DDR_WEA_N DDR_WEb NC_4 NC_4 C411 0.1uF
DDR_DQ[29] H23 F3 T7 F3 T7 AR405 56
DDR_DQA_29 DDR_QS0 DQSL NC_6 DDR_AA14 DDR_QS2 DQSL NC_6 DDR_AA14 DDR23_AA6
DDR_DQ[30] L25 U24 G3 G3 C440
DDR_DQA_30 DDR_CKEA DDR_CKE DDR_QS0b DQSL DDR_QS2b DQSL DDR23_AA4 1uF
DDR_DQ[31] H24
DDR_DQA_31 DDR23_AA5
W27 C7 A9 C7 A9
DDR_DM[0-3] DDR_CKA01_P DDR01_CLK DDR_QS1 DQSU VSS_1 DDR_QS3 DQSU VSS_1
W28 B7 B3 B7 B3 AR406 56 C452 0.1uF
DDR_CKA01_N DDR01_CLKb DDR_QS1b DQSU VSS_2 DDR_QS3b DQSU VSS_2 DDR01_AA6
DDR_DM[0] T26 E1 E1
DDR_DMA_0 VSS_3 VSS_3 DDR01_AA4
DDR_DM[1] P25 N28 E7 G8 E7 G8
DDR_DMA_1 DDR_CKA23_P DDR23_CLK DDR_DM[0] DML VSS_4 DDR_DM[2] DML VSS_4 DDR01_AA5
DDR_DM[2] J27 N27 D3 J2 D3 J2
DDR_DMA_2 DDR_CKA23_N DDR23_CLKb DDR_DQ[0-7] DDR_DM[1] DMU VSS_5 DDR_DQ[16-23] DDR_DM[3] DMU VSS_5 R426 56
DDR_DM[3] K24 J8 J8 DDR_CASb
DDR_DMA_3 VSS_6 VSS_6 R427 56 C441 1uF
U23 DDR_DQ[0] E3 M1 DDR_DQ[16] E3 M1 DDR_RASb
DDR_VREFA DDR_VREFA DQL0 VSS_7 DQL0 VSS_7
DDR_DQ[1] F7 M9 DDR_DQ[17] F7 M9
DQL1 VSS_8 DQL1 VSS_8
T27 AA23 DDR_DQ[2] F2 P1 DDR_DQ[18] F2 P1
DDR_QS0 DDR_DQSA_P_0 DDR_RST_N DDR_RESETb DQL2 VSS_9 DQL2 VSS_9
T28 DDR_DQ[3] F8 P9 DDR_DQ[19] F8 P9
DDR_QS0b DDR_DQSA_N_0 DQL3 VSS_10 DQL3 VSS_10
W26 R411 240 DDR_DQ[4] H3 T1 DDR_DQ[20] H3 T1
DDR_ZQ DQL4 VSS_11 DQL4 VSS_11
P24 1% DDR_DQ[5] H8 T9 DDR_DQ[21] H8 T9
DDR_QS1 DDR_DQSA_P_1 DQL5 VSS_12 DQL5 VSS_12
P23 DDR_DQ[6] G2 DDR_DQ[22] G2
DDR_QS1b DDR_DQSA_N_1 DQL6 DQL6
DDR_DQ[7] H7 DDR_DQ[23] H7
DDR_DQ[8-15] DQL7 DDR_DQ[24-31] DQL7
K27 B1 B1
DDR_QS2 DDR_DQSA_P_2 VSSQ_1 VSSQ_1
K28 DDR_DQ[8] D7 B9 DDR_DQ[24] D7 B9
DDR_QS2b DDR_DQSA_N_2 DQU0 VSSQ_2 DQU0 VSSQ_2
DDR_DQ[14] C3 D1 DDR_DQ[30] C3 D1
DQU1 VSSQ_3 DQU1 VSSQ_3
K25 DDR_DQ[13] C8 D8 DDR_DQ[29] C8 D8
DDR_QS3 DDR_DQSA_P_3 DQU2 VSSQ_4 DQU2 VSSQ_4
K26 DDR_DQ[12] C2 E2 DDR_DQ[28] C2 E2
DDR_QS3b DDR_DQSA_N_3 DQU3 VSSQ_5 DQU3 VSSQ_5
DDR_DQ[9] A7 E8 DDR_DQ[25] A7 E8
DQU4 VSSQ_6 DQU4 VSSQ_6
DDR_DQ[10] A2 F9 DDR_DQ[26] A2 F9
DQU5 VSSQ_7 DQU5 VSSQ_7
DDR_DQ[15] B8 G1 DDR_DQ[31] B8 G1
DQU6 VSSQ_8 DQU6 VSSQ_8
DDR_DQ[11] A3 G9 DDR_DQ[27] A3 G9
DQU7 VSSQ_9 DQU7 VSSQ_9

IC401-*2 IC402-*2 IC401-*3 IC402-*3 IC401-*1 IC402-*1


NT5CB128M16BP-CG NT5CB128M16BP-CG NT5CB128M16BP-DI NT5CB128M16BP-DI K4B2G1646C-HCK0 K4B2G1646C-HCK0

DDR_1333_NANYA DDR_1333_NANYA DDR_1600_NANYA


DDR_1600_NANYA DDR_1600_SS DDR_1600_SS
N3 M8 N3 M8 N3 M8 N3 M8 N3 M8
A0 VREFCA A0 VREFCA N3 M8 A0 VREFCA A0 VREFCA
P7 A0 VREFCA P7 A0 VREFCA P7 P7
P7 P7
A1 A1 A1 A1 A1
P3 P3 P3 A1 P3 P3
A2 A2 P3 A2 A2
N2 H1 A2 N2 H1 A2 N2 H1 N2 H1
N2 H1 N2 H1
A3 VREFDQ A3 VREFDQ A3 VREFDQ A3 VREFDQ A3 VREFDQ
P8 P8 P8 A3 VREFDQ P8 P8
A4 A4 P8 A4 A4
P2 A4 P2 A4 P2 P2
P2 P2
A5 A5 A5 A5 A5
R8 L8 R8 L8 R8 L8 A5 R8 L8 R8 L8
A6 ZQ A6 ZQ R8 L8 A6 ZQ A6 ZQ
R2 A6 ZQ R2 A6 ZQ R2 R2
R2 R2
A7 A7 A7 A7 A7
T8 T8 T8 A7 T8 T8
A8 A8 T8 A8 A8
R3 B2 A8 R3 B2 A8 R3 B2 R3 B2
R3 B2 R3 B2
A9 VDD_1 A9 VDD_1 A9 VDD_1 A9 VDD_1 A9 VDD_1
L7 D9 L7 D9 L7 D9 A9 VDD_1 L7 D9 L7 D9
A10/AP VDD_2 A10/AP VDD_2 L7 D9 A10/AP VDD_2 A10/AP VDD_2
R7 G7 A10/AP VDD_2 R7 G7 A10/AP VDD_2 R7 G7 R7 G7
R7 G7 R7 G7
A11 VDD_3 A11 VDD_3 A11 VDD_3 A11 VDD_3 A11 VDD_3
N7 K2 N7 K2 N7 K2 A11 VDD_3 N7 K2 N7 K2
A12 VDD_4 A12 VDD_4 N7 K2 A12/BC VDD_4 A12/BC VDD_4
T3 K8 A12 VDD_4 T3 K8 A12 VDD_4 T3 K8 T3 K8
T3 K8 T3 K8
NC_6 VDD_5 NC_6 VDD_5 NC_6 VDD_5 A13 VDD_5 A13 VDD_5
N1 N1 N1 NC_6 VDD_5 N1 N1
VDD_6 VDD_6 N1 VDD_6 VDD_6
M7 N9 VDD_6 M7 N9 VDD_6 M7 N9 M7 N9
M7 N9 M7 N9
NC_5 VDD_7 NC_5 VDD_7 NC_5 VDD_7 NC_5 VDD_7 NC_5 VDD_7
R1 R1 R1 NC_5 VDD_7 R1 R1
VDD_8 VDD_8 R1 VDD_8 VDD_8
M2 R9 VDD_8 M2 R9 VDD_8 M2 R9 M2 R9
M2 R9 M2 R9
BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9
N8 N8 N8 BA0 VDD_9 N8 N8
BA1 BA1 N8 BA1 BA1
M3 BA1 M3 BA1 M3 M3
M3 M3
BA2 BA2 BA2 BA2 BA2
A1 A1 A1 BA2 A1 A1
VDDQ_1 VDDQ_1 A1 VDDQ_1 VDDQ_1
J7 A8 VDDQ_1 J7 A8 VDDQ_1 J7 A8 J7 A8
J7 A8 J7 A8
CK VDDQ_2 CK VDDQ_2 CK VDDQ_2 CK VDDQ_2 CK VDDQ_2
K7 C1 K7 C1 K7 C1 CK VDDQ_2 K7 C1 K7 C1
CK VDDQ_3 CK VDDQ_3 K7 C1 CK VDDQ_3 CK VDDQ_3
K9 C9 CK VDDQ_3 K9 C9 CK VDDQ_3 K9 C9 K9 C9
K9 C9 K9 C9
CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4
D2 D2 D2 CKE VDDQ_4 D2 D2
VDDQ_5 VDDQ_5 D2 VDDQ_5 VDDQ_5
L2 E9 VDDQ_5 L2 E9 VDDQ_5 L2 E9 L2 E9
L2 E9 L2 E9
CS VDDQ_6 CS VDDQ_6 CS VDDQ_6 CS VDDQ_6 CS VDDQ_6
K1 F1 K1 F1 K1 F1 CS VDDQ_6 K1 F1 K1 F1
ODT VDDQ_7 ODT VDDQ_7 K1 F1 ODT VDDQ_7 ODT VDDQ_7
J3 H2 ODT VDDQ_7 J3 H2 ODT VDDQ_7 J3 H2 J3 H2
J3 H2 J3 H2
RAS VDDQ_8 RAS VDDQ_8 RAS VDDQ_8 RAS VDDQ_8 RAS VDDQ_8
K3 H9 K3 H9 K3 H9 RAS VDDQ_8 K3 H9 K3 H9
CAS VDDQ_9 CAS VDDQ_9 K3 H9 CAS VDDQ_9 CAS VDDQ_9
L3 CAS VDDQ_9 L3 CAS VDDQ_9 L3 L3
L3 L3
WE WE WE WE WE
J1 J1 J1 WE J1 J1
NC_1 NC_1 J1 NC_1 NC_1
T2 J9 NC_1 T2 J9 NC_1 T2 J9 T2 J9
T2 J9 T2 J9
RESET NC_2 RESET NC_2 RESET NC_2 RESET NC_2 RESET NC_2
L1 L1 L1 RESET NC_2 L1 L1
NC_3 NC_3 L1 NC_3 NC_3
L9 NC_3 L9 NC_3 L9 L9
L9 L9
NC_4 NC_4 NC_4 NC_4 NC_4
F3 T7 F3 T7 F3 T7 NC_4 F3 T7 F3 T7
DQSL NC_7 DQSL NC_7 F3 T7 DQSL NC_6 DQSL NC_6
G3 DQSL NC_7 G3 DQSL NC_7 G3 G3
G3 G3
DQSL DQSL DQSL DQSL DQSL
DQSL
C7 A9 C7 A9 C7 A9 C7 A9 C7 A9
DQSU VSS_1 DQSU VSS_1 C7 A9 DQSU VSS_1 DQSU VSS_1
B7 B3 DQSU VSS_1 B7 B3 DQSU VSS_1 B7 B3 B7 B3
B7 B3 B7 B3
DQSU VSS_2 DQSU VSS_2 DQSU VSS_2 DQSU VSS_2 DQSU VSS_2
E1 E1 E1 DQSU VSS_2 E1 E1
VSS_3 VSS_3 E1 VSS_3 VSS_3
E7 G8 VSS_3 E7 G8 VSS_3 E7 G8 E7 G8
E7 G8 E7 G8
DML VSS_4 DML VSS_4 DML VSS_4 DML VSS_4 DML VSS_4
D3 J2 D3 J2 D3 J2 DML VSS_4 D3 J2 D3 J2
DMU VSS_5 DMU VSS_5 D3 J2 DMU VSS_5 DMU VSS_5
J8 DMU VSS_5 J8 DMU VSS_5 J8 J8
J8 J8
VSS_6 VSS_6 VSS_6 VSS_6 VSS_6
E3 M1 E3 M1 E3 M1 VSS_6 E3 M1 E3 M1
DQL0 VSS_7 DQL0 VSS_7 E3 M1 DQL0 VSS_7 DQL0 VSS_7
F7 M9 DQL0 VSS_7 F7 M9 DQL0 VSS_7 F7 M9 F7 M9
F7 M9 F7 M9
DQL1 VSS_8 DQL1 VSS_8 DQL1 VSS_8 DQL1 VSS_8 DQL1 VSS_8
F2 P1 F2 P1 F2 P1 DQL1 VSS_8 F2 P1 F2 P1
DQL2 VSS_9 DQL2 VSS_9 F2 P1 DQL2 VSS_9 DQL2 VSS_9
F8 P9 DQL2 VSS_9 F8 P9 DQL2 VSS_9 F8 P9 F8 P9
F8 P9 F8 P9
DQL3 VSS_10 DQL3 VSS_10 DQL3 VSS_10 DQL3 VSS_10 DQL3 VSS_10
H3 T1 H3 T1 H3 T1 DQL3 VSS_10 H3 T1 H3 T1
DQL4 VSS_11 DQL4 VSS_11 H3 T1 DQL4 VSS_11 DQL4 VSS_11
H8 T9 DQL4 VSS_11 H8 T9 DQL4 VSS_11 H8 T9 H8 T9
H8 T9 H8 T9
DQL5 VSS_12 DQL5 VSS_12 DQL5 VSS_12 DQL5 VSS_12 DQL5 VSS_12
G2 G2 G2 DQL5 VSS_12 G2 G2
DQL6 DQL6 G2 DQL6 DQL6
H7 DQL6 H7 DQL6 H7 H7
H7 H7
DQL7 DQL7 DQL7 DQL7 DQL7
B1 B1 B1 DQL7 B1 B1
VSSQ_1 VSSQ_1 B1 VSSQ_1 VSSQ_1
D7 B9 VSSQ_1 D7 B9 VSSQ_1 D7 B9 D7 B9
D7 B9 D7 B9
DQU0 VSSQ_2 DQU0 VSSQ_2 DQU0 VSSQ_2 DQU0 VSSQ_2 DQU0 VSSQ_2
C3 D1 C3 D1 C3 D1 DQU0 VSSQ_2 C3 D1 C3 D1
DQU1 VSSQ_3 DQU1 VSSQ_3 C3 D1 DQU1 VSSQ_3 DQU1 VSSQ_3
C8 D8 DQU1 VSSQ_3 C8 D8 DQU1 VSSQ_3 C8 D8 C8 D8
C8 D8 C8 D8
DQU2 VSSQ_4 DQU2 VSSQ_4 DQU2 VSSQ_4 DQU2 VSSQ_4 DQU2 VSSQ_4
C2 E2 C2 E2 C2 E2 DQU2 VSSQ_4 C2 E2 C2 E2
DQU3 VSSQ_5 DQU3 VSSQ_5 C2 E2 DQU3 VSSQ_5 DQU3 VSSQ_5
A7 E8 DQU3 VSSQ_5 A7 E8 DQU3 VSSQ_5 A7 E8 A7 E8
A7 E8 A7 E8
DQU4 VSSQ_6 DQU4 VSSQ_6 DQU4 VSSQ_6 DQU4 VSSQ_6 DQU4 VSSQ_6
A2 F9 A2 F9 A2 F9 DQU4 VSSQ_6 A2 F9 A2 F9
DQU5 VSSQ_7 DQU5 VSSQ_7 A2 F9 DQU5 VSSQ_7 DQU5 VSSQ_7
B8 G1 DQU5 VSSQ_7 B8 G1 DQU5 VSSQ_7 B8 G1 B8 G1
B8 G1 B8 G1
DQU6 VSSQ_8 DQU6 VSSQ_8 DQU6 VSSQ_8 DQU6 VSSQ_8 DQU6 VSSQ_8
A3 G9 A3 G9 A3 G9 DQU6 VSSQ_8 A3 G9 A3 G9
DQU7 VSSQ_9 DQU7 VSSQ_9 A3 G9 DQU7 VSSQ_9 DQU7 VSSQ_9
DQU7 VSSQ_9 DQU7 VSSQ_9

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN DDR 04

Copyright © 2011 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
NEC MICOM

FLMD0
GND

+3.5V_ST

10K
47K
C602 C603 R641
50V 50V MICOM_DOWNLOAD

OPT

R639
13pF 13pF 0

R637
X601

For Debug 10MHz

15pF

15pF

WIRELESS_PWR_EN
C606

C607
P601 +3.5V_ST

WIRELESS_DET
12505WS-12A00

MICOM_RESET
1 X602
+3.5V_ST

2
MICOM_RESET 32.768KHz
3 R615 22
NEC_ISP_Tx R642 +3.5V_ST
10Mhz Crystal
4 4.7M
R617 22 OPT
5 NEC_ISP_Rx

47K
6

7
OCD1A
8

P122/X2/EXCLK/OCD0B

R644
9
OCD1B GND SW1
+3.5V_ST
10
JTP-1127WEM
2 1

22

P120/INTP0/EXLVI
R621 22

270K
11
FLMD0

OPT
C608

R645
P124/XT2/EXCLKS
0.1uF

0.1uF
12
4 3
R606 10K 16V

P121/X1/OCD0A
13

R643
C604
0.1uF

C605

P123/XT1
R607 10K +3.5V_ST R647 20K
NEC_ISP_Rx
R610 10K 1/16W

FLMD0

RESET
NEC_ISP_Tx 1%

REGC

1/16W
R646
VDD
VSS

P40
P41

20K

1%
R626 4.7K

R628 4.7K

48
47
46
45
44
43
42
41
40
39
38
37
R629 22
P60/SCL0 1 36 P140/PCL/INTP6 RL_ON
SCL2_3.3V

R630 22
P61/SDA0 2 35 P00/TI000
SDA2_3.3V SCART_MUTE
P62/EXSCL0 3 34 P01/TI010/TO00 R648 10K C
EDID_WP

EEPROM for Micom EEPROM_SCL

P63 P130 B Q601


4 33 2SC3052
EEPROM_SDA
P33/TI51/TO51/INTP4 IC602 P20/ANI0 E
+3.5V_ST HDMI_CEC
R631 22
5 32 R649 0

OPT
P75 6 uPD78F0514 31 ANI1/P21
POWER_ON/OFF2_1 MODEL1_OPT_3
IC601 P74 ANI2/P22
M24C16-WMN6T AMP_MUTE 7 30 MODEL1_OPT_2
P73/KR3 NEC_MICOM ANI3/P23
MODEL1_OPT_0 8 29 POWER_ON/OFF1
NC/E0 VCC
1 8 R632 22 P72/KR2 9 28 ANI4/P24
R601

SOC_RESET MICOM_DOWNLOAD
47K

NC/E1
2 7
WC P71/KR1 10 27 ANI5/P25
INV_CTL SIDE_HP_MUTE

NC/E2 SCL R619


P70/KR0 11 26 ANI6/P26
3 6 EEPROM_SCL MODEL1_OPT_1 KEY2
R633
22
22 P32/INTP3/OCD1B 12 25 ANI7/P27
VSS SDA R616 OCD1B KEY1
4 5 EEPROM_SDA OPT
22

13
14
15
16
17
18
19
20
21
22
23
24
S/T_SCL

R627
4.7K

P31/INTP2/OCD1A
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RXD6
P13/TXD6
P12/SO10
P11/SL10/RXD0
P10/SCK10/TXD0
AVREF
AVSS
+3.5V_ST

+3.5V_ST

MODEL OPTION

PIN NAME

C609 1uF
PIN NO. HIGH LOW
MICOM MODEL OPTION MODEL_OPT_0 8
10YEAR_TOOL
(10 SENSOR)
11YEAR_TOOL
(11 SENSOR)

MODEL_OPT_1 11 I2C_LED PWM_LED


+3.5V_ST
MODEL_OPT_2 30 TOUCH_KEY TACT_KEY

MODEL_OPT_3
10K

10K

10K

10K

31 PDP/3D LCD/OLED
10YEAR_TOOL
TOUCH_KEY

I2C LED
PDP/3D

OPT
R611

R613

R622

R624

LCD PDP OLED 3D


R604 100
AMP_RESET_N

10K
MODEL1_OPT_0 MODEL_OPT_3
22

R605 100 0 1 0 1 +3.5V_ST


PANEL_CTL MODEL1_OPT_1
R602 100
INSTANT_MODE MODEL1_OPT_2
R603 100
MODEL1_OPT_3
R638

R640

LOW LOW_SMALL TBD HIGH


10K

10K

10K

10K
11YEAR_TOOL

R636
LCD/OLED

TACT_KEY

PWM_LED

4.7K
MODEL_OPT_1 0 0 1 1
R612

R614

R623

R625

MODEL_OPT_2 0 1 0 1
LED_R/BUZZ
LED_B/LG_LOGO
POWER_DET

IR

NEC_ISP_Tx

NEC_TXD
NEC_ISP_Rx

POWER_ON/OFF2_2

NEC_RXD
OCD1A
S/T_SDA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 6 50

Copyright © 2011 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DUAL COMPONENT

D707,D708
D710,D711 1ST : 0DD184009AA 2ND : 0DSIH00028A
BODY_SHIELD
D713 1ST : T-BAT54_SUZHO, 2ND : 0DSON00138A
5V_HDMI_1 GND 5V_HDMI_4
BODY_SHIELD
HDMI_HPD_1 HDMI_HPD_4
20 20
VR706 R728 HP_DET VR708 R729
HP_DET 10V 1K
10V 1K R727
19 R737 19 OPT OPT
5V 0 C714 OPT OPT 5V 0 C717
0.1uF 18 0.1uF
18 VR703 GND R735 VR707 OPT 16V
OPT
17
GND R730
3.6K 10V
OPT
16V
OPT 17
3.6K
OPT
10V
OPT OPT * HDMI CEC
DDC_DATA OPT DDC_DATA
DDC_SDA_1 DDC_SDA_4
16 16
DDC_CLK DDC_CLK
DDC_SCL_1 15 DDC_SCL_4
15
NC
ARC
14 14
CE_REMOTE CE_REMOTE
CEC_REMOTE CEC_REMOTE
13 13 +3.3V_Normal +3.3V_HDMI
CK- CK-
CK-_HDMI1 12
CK-_HDMI4 +3.5V_ST
12 HDMI_ARC CK_GND
CK_GND ARC EAG62611201
L701
EAG62611201

11 11 BLM18PG121SN1D
CK+ CK+
10 R775 10 CK+_HDMI4
CK+_HDMI1
C730 150 D0-
D0- 0.1uF 9
9 D0-_HDMI1 D0-_HDMI4 C720
D0_GND R754 C718 C719
D0_GND 0.1uF

G
8 R776 8 27K 10uF 10uF
16V
D0+ 63.4 D0+
7 7 D0+_HDMI4
D0+_HDMI1
D1- D1- R741
6 6 D1-_HDMI4

D
B
S
D1-_HDMI1 D713 Q710 120K
D1_GND D1_GND BSS83
5 5 BAT54_SUZHO
D1+ D1+
4 4 D1+_HDMI4
D1+_HDMI1
D2- D2-
3 CEC_REMOTE HDMI_CEC
3 D2-_HDMI1 D2-_HDMI4
D2_GND D2_GND
2 2
D2+ D2+
1 1 D2+_HDMI4
D2+_HDMI1

JK703 RSD-105156-100
RSD-105156-100 JK704

HDMI1 HDMI4
+3.3V_HDMI

+5V_Normal +5V_Normal
5V_HDMI_1 5V_HDMI_2
A2

A1

A2

A1
BODY_SHIELD 5V_HDMI_2
C707 C706 C711 C713
HDMI_HPD_2 D707 D710 10uF 10uF 0.1uF 0.1uF
20 10V 10V 16V 16V HDMI1 HDMI S/W OUTPUT
C

HP_DET VR704 R736

D2-_HDMI1

D1+_HDMI1

D1-_HDMI1

D0+_HDMI1

D0-_HDMI1

CK+_HDMI1

CK-_HDMI1
D2+_HDMI1

HDMI_CLK-

HDMI_RX0-

HDMI_RX0+

HDMI_RX1-

HDMI_RX1+

HDMI_RX2-

HDMI_RX2+
HDMI_CLK+
10V 1K
19 R725 C701 C703 C712
5V 0 C715 OPT OPT
10uF 0.1uF 0.1uF
0.1uF R713 R715 R720 R723
18 VR701 OPT 10V 16V 16V
GND R740 16V 4.7K 4.7K 4.7K
3.6K 10V 4.7K
OPT OPT
17 OPT
DDC_DATA
DDC_SDA_2 DDC_SDA_1 DDC_SDA_2
16
DDC_CLK
15 DDC_SCL_2 DDC_SCL_1 DDC_SCL_2
NC
14
CE_REMOTE
CEC_REMOTE
13
CK-
CK-_HDMI2
12
CK_GND
EAG62611201

11
CK+ +5V_Normal
10 +5V_Normal
CK+_HDMI2 5V_HDMI_3 5V_HDMI_4
D0-
9 D0-_HDMI2
D0_GND
A2

A1

A2

A1

TPWR_CI2CA
D0+
7 D0+_HDMI2 D708 D711
D1-
C

[EP]GND

VCC33_3
6 D1-_HDMI2
D1_GND

R0X2P
R0X2N
R0X1P
R0X1N
R0X0P
R0X0N
R0XCP
R0XCN
5 R777 OPT R780 33

TXCN
TXCP
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
4.7K SCL1_3.3V
D1+ R714 R716 R721 R724
4 D1+_HDMI2 4.7K 4.7K
4.7K 4.7K
3
D2- OPT R781 33 SDA1_3.3V
D2-_HDMI2 DDC_SDA_4
D2_GND
DDC_SDA_3

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
2 DDC_SCL_4
D2+ R778
1 D2+_HDMI2 DDC_SCL_3 HDMI2 R1XCN 1 54 CSCL 33
SCL3_3.3V
CK-_HDMI2
R1XCP 2 53 CSDA
SDA3_3.3V
CK+_HDMI2 THERMAL
R1X0N 3 73 52 INT R779
33
JK701 D0-_HDMI2
R1X0P 4 51 CEC_D
RSD-105156-100
HDMI2 EDID Pull-up D0+_HDMI2
R1X1N CEC_A +5V_Normal
D1-_HDMI2
5 50
R1X1P 6 49 R4PWR5V R706
C710
D1+_HDMI2
R1X2N DSCL4 0
D2-_HDMI2
7 IC701 48 1uF
5V_HDMI_4
R1X2P DSDA4 10V
D2+_HDMI2
8 SII9287B 47
R717
VCC33_1 9 46 R3PWR5V 10

RSVD_1 10 45 CBUS_HPD3
HDMI_HPD_4 1/16W
HDMI3 R2XCN 11 44 DSCL3 C705 R711
5V_HDMI_3 CK-_HDMI3 DDC_SCL_4 1K 5V_HDMI_3
BODY_SHIELD 1uF
R2XCP 12 43 DSDA3 1%
HDMI_HPD_3
CK+_HDMI3 DDC_SDA_4 R718
20 R2X0N R2PWR5V 10
HP_DET VR705 R726
D0-_HDMI3
13 42
1K
19 R731 10V
OPT
R2X0P 14 41 CBUS_HPD2
5V 0 C716 OPT HDMI_HPD_3 1/16W
D0+_HDMI3
0.1uF R2X1N DSCL2 C702 R705
18
GND R739 VR702 OPT 16V D1-_HDMI3
15 40 1K
10V DDC_SCL_3 1uF
3.6K OPT R2X1P DSDA2 1%
17
DDC_DATA OPT OPT
D1+_HDMI3
16 39
DDC_SDA_3
DDC_SDA_3 R2X2N SBVCC
16
DDC_CLK 17 38
D2-_HDMI3
15 DDC_SCL_3 R2X2P 18 37 MICOM_VCC33
NC D2+_HDMI3
C708
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
14
CE_REMOTE 1uF
CEC_REMOTE
13
CK-
CK-_HDMI3
R3XCN
R3XCP
R3X0N
R3X0P
R3X1N
R3X1P
R3X2N
R3X2P
VCC33_2
RSVD_2
DSDA0
DSCL0
CBUS_HPD0
R0PWR5V
DSDA1
DSCL1
CBUS_HPD1
R1PWR5V
12
CK_GND
5V_HDMI_2
EAG62611201

11
CK+
10 R712
CK+_HDMI3 10
D0-
9 D0-_HDMI3
D0_GND
8 1/16W
C709 R707
D0+ 1K
7 D0+_HDMI3 1uF
1%
D1-
6 D1-_HDMI3
D1_GND 5V_HDMI_1
5
D1+ R708
4 D1+_HDMI3 10
D2-
3 D2-_HDMI3
D2_GND 1/16W
2 C704 R703
D2+ 1uF 1K
1 D2+_HDMI3 1%
DDC_SDA_1

DDC_SCL_1

DDC_SDA_2

DDC_SCL_2
HDMI_HPD_1

HDMI_HPD_2
D2+_HDMI4
CK-_HDMI4

CK+_HDMI4

D0-_HDMI4

D0+_HDMI4

D1-_HDMI4

D2-_HDMI4
D1+_HDMI4

JK702
RSD-105156-100

HDMI3
HDMI4

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 7 31

Copyright © 2011 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
RGB/ PC AUDIO/ SPDIF/ EARPHONE/ RS232C

DUAL COMPONENT

RGB PC D810
KDS184
A2
+5V_Normal
EARPHON JACK D804,D805,D806
D807,D808,D813
D814
1ST : EAH39491601, 2ND : EAH33945901
C
A1 D810 1ST : 0DD184009AA, 2ND : 0DSIH00028A
JK803
+3.3V_Normal KJA-PH-0-0177
+5V_Normal
Q801 1ST : 0TRIY80001A, 2ND : 0TR387500AA
GND 5
IC801
74F08D R822
R814 R815 R817 IC805 1ST : EAN61151201, 2ND : EAN61130001
IC802 2.7K L 4
2.7K 2.7K 10K HP_LOUT
D0A VCC AT24C02BN-SH-T
1 14

A0 VCC
DETECT 3
D0B D3B 1 8 HP_DET
DSUB_VSYNC 22 R801 2 13 1K R821
A1 WP
Q0 D3A
2 7
EDID_WP R 1
3 12 HP_ROUT
A2 SCL R848 22
DSUB_HSYNC 22 R802 3 6
RGB_DDC_SCL
R850 0 D1A
4 11
Q3 EAG61030001
GND SDA R847 22
4 5
OPT RGB_DDC_SDA OPT
R851 0 D1B D2B R852 0 R825 0
5 10
C809 C810 SPK_R+_HOTEL
OPT OPT
Q1 D2A R853 0 18pF 18pF OPT
6 9
50V 50V R826 0
OPT SPK_R-_HOTEL
GND Q2
7 8

R807 C807 D809


10K D804 22pF
50V 5.6V
OPT 30V
OPT

+3.3V_Normal

R808 C808
D811 EARPHONE AMP
D805 22pF 5.6V L803
10K
30V 50V OPT 120-ohm
OPT
BLM18PG121SN1D
LPF READEY
BLM15BD121SN1 (For H/P Noise Improvement)
L806 C822 C824
ESD_CERADIODE

10uF 0.1uF
10V 16V
D808-*1

DSUB_B+ R868 L804


ESD_COMMON 0 BG2012B080TF
5.6V

C830 D808 HP_LOUT


R812 30V
47pF C828
75 Close to the IC C821
50V 0.22uF
1uF
10V
10V

OUTL

SGND

VDD
+3.3V_Normal

EN
R837
BLM15BD121SN1 C825 100K
C816 16 15 14 13 2.2uF OPT
L807 1uF R842 OPT
ESD_CERADIODE

+3.3V_Normal INL- HPVDD 10V


10V 4.7K R843
1 12
0
D806-*1

DSUB_G+ HP_LOUT_N
ESD_COMMON C817
5.6V

C831 D806 R819 1uF C


R811 10K 10V INL+ CPP R844
47pF 30V 2 11
75 HP_LOUT_P Q801 B 1K
50V C818 IC804 C826 2SC3052 SIDE_HP_MUTE
1uF TPA6132A2 2.2uF
10V INR+ PGND 10V
DSUB_DET 3 10 E
1K R820 HP_ROUT_P
C819
1uF
ESD_COMMON 10V INR- CPN
4 EAN60724701 9
BLM15BD121SN1 HP_ROUT_N
D812
L808 5.6V D812-*1
ESD_CERADIODE

5.6V 5 6 7 8

4.7K
R827
D807-*1

DSUB_R+ ESD_CERADIODE

4.7K
R823

OUTR

G0

G1

HPVSS
ESD_COMMON
C832
5.6V

R813 D807
75 47pF 30V
50V
R869 L805
0 BG2012B080TF

OPT
R828
OPT
R824
HP_ROUT