wwnw.studywarehouse.com: Instruction Set The instruction set, also called instruction set architecture (ISA), is part of a computer that pertains to programming, which is basically machine language. The instruction set provides commands to the processer, to tel todo. The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt, and exception handling, and external 0. wha needs An example of an instruction set is the x86 instruction set, which is commen to find on computers today. Different computer processors can use almost the same instruction set while still having very different internal design. Both the Intel Pentium and AMD Athlon processors use nearly the same x86 instruction set. An instruction set can be built into the hardware of the processor, or it can be emulated in software, using an interpreter. The hardware design is more efficient and faster for running programs than the emulated software version. Examples of instruction set © ADD- Add two numbers together. © COMPARE - Compare numbers. © IN- Input information from a device, eg. keyboard. © JUMP - lump to designated RAM address. © JUMP IF - Conditional statement that jumps to a designated RAM address, © LOAD Load information from RAM to the CPU, = OUT-Output information to device, eg., monitor. © STORE - Store information te RAM. Instruction Set Architecture (ISA) ‘The Instruction Set Architecture (ISA) is the part of the processor thats visible to the programmer or compiler writer. ‘The ISA servesas the boundary between software and hardware. We will briefly describe the instruction sats found in many of the microprocessors used today. The |SA of a processor can be described using 5 categories: Operand Storage in the CPU Where are the operands kept ather than in memory? Number of explicit named operands How many operands are named in a typical instruction? Operand location Can any ALU instruction operand be located in memory? Or mustall operands be kept internally in the CPU? Operations What Operations are provided in the ISA. ‘Type and size of operands Whatis the type and size of each operand and how isit specified? Of all the above the most distinguishing factor is the first. The 3 most common types of ISAs are’ ‘Stack - The operands are implicitly on top of the stack. Accumulator - One operand is implicitly the accumulator. General Purpose Register (GPR) - All operands are explicitly mentioned; they are either registers or memory locations.www.studywarehouse.com Let's look at the assernbly code of C=A4B; in ell 3 architectures: ‘Stack [accurnulator spa PUSH A LOADA LOAD R1,A PUSH B Apo [aD 1,8 ‘ADD STORE C [STORE Ra,c POPC : - Not all processors can be neatly tagged into one of the above categories. The 18086 has many instructions that use implicit operands although it has a general register set. The 18051 is another example, it has 4 banks of GPRs but most instructions must have the A register as one of its operands. What are the advantages and disadvantages of each of these approaches? Stack Advantages: Simple Model of expression evaluation (reverse polish). Short instructions. Disadvantages: A stack can't be randomly accessed This makes it hard to generate efficient code. The stack itself is accessed every operation and becomes a hattleneck. Accumulator Advantages: Short instructions. Disadvantay The accumulator is only temporary storage so memory trafficis the highest for this approach. GPR Advantages: Makes code generation easy. Data can be stored for lang periads in registers. Disadvantages: All operands must be named leading to longer instructions Earlier G2Us were of the first 2 types butin the last 15 years all CPUs made are GPR processors. The 2 major reasons are that registersare faster than memory, the more data that can be keptinternally in the CPU the faster the program will run. The other reason is that registers are easier for 2 compiler to use, Reduced Instruction Set Computer (RISC) As we mentioned before most modern CPUs are of the GPR (General Purpose Register) type. A few examples of such CPUs are the IBM 360, DEC VAX, Intel 80x86 and Motorola 68xxx. But while these CPUS were clearly better than previous stack and accumulator based CPUs they were still lacking in several areas: 1. Instructions were of varying length from 1 byte to 6-8 bytes. This causes problems with the pre-fetching and pipelining of instructions.www.studywarehouse.com 2. ALU (Arithmetic Logical Unit} instructions could have operands that were memory locations. Because the number of cycles it takes to access memary varies sa does the whole instruction. This isn't gaad for compiler writers, pipelining and multol 3. Most ALUinstructions had only 2 operands where one of the operandsis also the destination. This means this operands destroyed during the operation or it must be saved before sornewhere. Thusin the early 80's the idea of RISC was introduced. The SPARC project was started at Berkeley and the MIPSproject at Stanford. RISC stands for Reduced instruction Set Computer. The |SAis composed of instructions thatall have exactly the same size, usually 32 bits, Thus they can be pre-tetched and pipelined successfully. All ALU instructions have 3 operands which are only registers. The only memory access is through explicit LOAD/STORE. instructions. Thus C= A+ Swill be assembled as: LOAD R1,A LOAD R2,B ADD R3,RI,R2 STORE C.R3 Although it takes 4 instructions we can reuse the veluesin the registers, ‘Why is this architecture called RISC? What is Reduced about it? The answers that to make all instructions the same length the number of bits that are used for the opcode isreduced, ‘Thus less instructions are provided. The instructions that were thrown out are the less important string and BCD (binary-caded decimal) operations. In fact, now that memory access!s restricted there aren't several kinds of MOV or ADD instructions. Thus the alder architecture is called CISC (Camplete Instruction Set Computer). RISC architectures are also called LOAD/STORE architectures. ‘The number of registersin RISCis usually 22 or mare. The first RISC CPU the MIPS 2000 has 32 GPRs as apposed t016 in the 60x architecture and @ in the 80x86 architecture. The only disadvantage of RISC isits code size. Usually more instructions are needed and there is @ waste in short instructions (POP, PUSH). So why are there still CISC CPUs being developed? Why is Intel spending time and money to manufacture the Pentium Il and the Pentium III? ‘The answer is simple, backward compatibility. The IBM compatible PC is the most common camputer in the world. Intel wanted @ CPU that would run all the applications that are in the hends of more than 100 million users. On the other hand, Motorola which builds the 68%xx series which was used in the Macintosh made the transition and together with 18M and Apple built the Power PC (PPC) a RISC CPU which is installed in the new Power Macs. As of now Intel and the PC manufacturers are making more money but with Microsoft playing in the RISC field as well (Windows NT runs con Compaq!s Alpha) and with the promise of Java the future of CISC isn't clear at all An important lesson that can be learnt heres that superior technology isa factorin the computer industry, but so are marketing and price as wall (ifnoz more) Microprocessor Design/Single Cycle Processors Single-cycle processors are what we have been studying so far: an instruction is fetched from memory, its executed, and the results are stored all ina single clack cycle. The benefits of single-cycle processors are that they tend to be the simplest in terms of hardwere requirements, and they are easy to design. Unfortunately, they tend to have poor data throughput, and require long clock cycles (sow clock rate) in order to perform all the necessary computations in time,