Exp. No.

:01
Date:
Design of CMOS Inverter

Aim:
To design CMOS Inverter and to do circuit simulation, perform Transfer Characteristics and
Transient Analysis, Layout Design using Mentor graphics.

Apparatus:
 Mentor Graphics Tool.
 Personal Computer.

Theory:
As you can see from Figure 1, a CMOS circuit is composed of two MOSFETs. The top FET
(MP) is a PMOS type device while the bottom FET (MN) is an NMOS type. The body effect
is not present in either device since the body of each device is directly connected to the
device’s source. Both gates are connected to the input line. The output line connects to the
drains of both FETs.

Take a look at the VTC in Figure 2. The curve represents the output voltage taken from node
3. You can easily see that the CMOS circuit functions as an inverter by noting that when
VIN is five volts, VOUT is zero, and vice versa. Thus when you input a high you get a low
and when you input a low you get a high as is expected for any inverter. You might be
wondering what happens in the middle, transition area of the curve. You might also be
curious as to what modes of operation the MOSFETs are in. We will look at these issues
next.

Fig 1.1: CMOS Inverter Fig 1.2: Basic Voltage Transfer Characteristic
Dc Analysis:

Figure 3 shows a more detailed VTC. Before we begin our analysis it is important to mention
three items.

The MOSFETS must be perfectly matched for optimum operation, that is, they must have the
same threshold voltage magnitude and conduction parameter.

The drain current (ID) through the NMOS device equals the drain current through the PMOS
device at all times. MOSFET gates have a high input impedance and we assume the circuit’s
output sees no significant loading.

VDD equals the voltage across the PMOS plus the voltage across the NMOS by KVL.

Figure 1.3: VTC with Input Signal

Region I

First we focus our attention on region I. In this case when we apply an input voltage
between 0 and VTN. The PMOS device on since a low voltage is being applied to it. The
NMOS is already negative enough and has no use for more free electrons so it refuses to
conduct and turns into a large resistor. Since the NMOS device is on vacation, there is no
current flow through either device. VDD is available at the Vo terminal since no current is
going through the PMOS device and thus no voltage is being dropped across it.

The PMOS device is forward biased (VSG > -VTP) and therefore on. This MOSFET is in
the linear region (VSD<=VSG+VTP=VDD-Vo+VTP).

The NMOS device is cut off since the input voltage is below VTN (Vi=VGS<VTN).

The power dissipation is zero.

Region II

Here we raise the input voltage above VTN. We find that the PMOS device remains in the
linear region since it still has adequate forward bias. The NMOS turns on and jumps
immediately into saturation since it still has a relatively large VDS across it.

The PMOS device is in the linear region (VSD<=VSG+VTP).

The NMOS device is in the saturation region (Vi=VDS>=VGS-VTN=Vo-VTN).

Current now flows through both devices. Power dissipation is no longer zero.

The maximum allowable input voltage at the low logic state (VIL) occurs in this region. VIL
is the value of Vi at the point where the slope of the VTC is -1. Put another way, VIL occurs
at (dVo/dVi)=-1.

Region III

In the middle of this region there exists a point where Vi=Vo. We label this point VM and
identify it as the gate threshold voltage. The voltage dropped across the NMOS device equals
the voltage dropped across the PMOS device when the input voltage is VM. For a very short
time, both devices see enough forward bias voltage to drive them to saturation.

The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vo+VTP).

The NMOS device is in the saturation region (VDS>=VGS-VTN=Vo-VTN).

Power dissipation reaches a peak in this region, namely at where VM=Vi=Vo.

Region IV

Region IV occurs between an input voltage slightly higher than VM but lower than VDD-
VTP. Now the NMOS device is conducting in the linear region, dropping a low voltage
across VDS. Since VDS is relatively low, the PMOS device must pick up the tab and drop
the rest of the voltage (VDD-VDS) across its VSD junction. This, in turn, drives the PMOS
into saturation. This region is effectively the reverse of region II

The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vo+VTP).

The NMOS device is forward biased (Vi=VGS > VTN) and therefore on. This MOSFET is
in the linear region (Vi=VDS<=VGS-VTN=Vo-VTN).

The minimum allowable input voltage at the logic high state (VIH) occurs in this
region. VIH occurs at the point where the slope of the VTC is –1 (dVo/dVi)=-1.
Region V

The NMOS wants to conduct but its drain current is severely limited due to the PMOS device
only letting through a tiny leakage current. The PMOS is out to lunch since it is seeing a
positive drive but it is already positive enough and has no use for more. This drain current let
through by the PMOS is too small to matter in most practical cases so we let ID=0. With this
information we can conclude that VDS=Vo=0 V for the NMOS since no current is going
through the device. We have, in effect, sent in VDD and found the inverter’s output to be
zero volts. For CMOS inverters, VOH=VDD. VOL is defined to be the output voltage of
the inverter at an input voltage of VOH. We have just proven that VOL=0.

The PMOS device is cut off when the input is at VDD (VSG=0 V).

The NMOS device is forward biased (Vi=VGS > VTN) and therefore on. This MOSFET is
in the linear region (Vi=VDS<=VGS-VTN).

The total power dissipation is zero just as in region I.

Procedure:
1. Open X manager displayed on Desktop. Then press X start .
2. Give session name and give host address as 172.168.0.35.
3. Give protocol as SSH and give user name as user40 and enter password as user123.
4. Give execution command as 3Xternn(LinuxType2).
5. Tick the save checkbox that present in window and then click Save Button and then
Run.
6. Then the new window will be opened that is server window.
7. Give commands as csh then click enter
8. Give command as source /home/software/cshrc/hep.cshrc and click enter button.
9. Now you have to make directory for your project , For this you need enter command
as mkdir projectname .
10. For view your directory enter cd projectname.
11. Last command you need to give to open pyxis schematic window is da_ic& and then
click Enter button.
12. In the pyxis schematic Enter File on the tool bar and then click schematric and give
filename.
13. After to design cmos inverter click Library and after select devicelibrary and select
pmos 4pin and nmos 4pin transistors.
14. For VDD and Ground you need to click on Generic Library and select Vdd and
Ground..
15. All these are appeared on pyxis schematic window.
16. Select Add port in and add portout for input and outputs then click ESC key.
17. For Renaming ports click on NET and press Q button then a window will be opened
then rename net.
18. You have to rename transistors also. For transistors also the procedure is same like
above step.
19. Click on Check/save in tool bar, Then a console window will be opened , if any
errors in your design are there it shows in that window.
20. Click add in tool bar and click Generate symbol and tick Replace Existingand then
click Activate Symbol and then click on Choose shape button and click on Buffer
and click OK.
21. After click on Add circle and place it to buffer.
22. Again click Check/save.
23. Close all the windows.
24. For Simulating your design Click on File ↵ New ↵ schematic.
25. Give file name as inv0304_sim and click ↵ (Enter button )and click OK.
26. Give right click on schematic and select instance and choose symbol and select
previous created file (project name) and click ok.
27. Give port in and port out for the circuit.
28. Rename the ports as in and out.
29. Go to Library and click on Source Library, select pattern and dc.
30. For dc you need to add ground and vdd.
31. For pattern add ground.
32. Click check/save and correct if there are any errors.
33. Click Simulation on schematic Library.
34. Then awindow will be opened in that click on New design configuration and give
name as sim.
35. Click Lib/Temp/Inc then click include files and click on browse button then after
click on Browse location map and click on $ADK ↵ Technologies ↵ ic ↵ models ↵
ami05.mod ↵ok and then click Apply.
36. After go to library and then go import library and Browse location map and click
on $ADK ↵ Technologies ↵ ic ↵ models ↵ ami05.mod ↵ok and then click Apply.
37. Click on Analysis button.
38. Disable OP tick and enable DC tick.
39. Click sweep type as source.
40. Click on Symbol and select voltage shown by software and give start as 0v and stop
as 5v and step as 0.01 and click Apply and Ok
41. Select Transient Tick and click start time as 0ns and stop time as 1000n and click
Apply and OK.
42. Select Input and output with Cntrl button and click outputs on Schematic library ,
then a new window will be opened.
43. Give analysis as DC and task as plot and click add button.
44. After click Trans and task as plot and click add button and Apply and Ok &run.
45. Click on view waves.
46. Click on ASCII Files in schematic library and click NetList and Save the net list.
Circuit WaveForms :

Fig 1.4 : Circuit Diagram of CMOS Inverter.

Fig 1.5: Schematic diagram of CMOS Inverter.

Fig 1.6: DC analysis.

Fig 1.7: Transient Analysis.

 Fig 1.9: Layout of cmos inverter.

Netlist:
* ELDO netlist generated with ICnet by 'user40' on Wed Jan 30 2019 at 15:47:42

.CONNECT GROUND 0

*
* Globals.
*
.global VDD GROUND

*
* Component pathname : /home/user40/18k61d680102/inverter0102
*
.subckt INVERTER0102 OUT IN

M2 OUT IN GROUND GROUND N L=0.35u W=1.4u M=1

 M1 OUT IN VDD VDD P L=0.35u W=1.4u M=1
.ends INVERTER0102

*
* MAIN CELL: Component pathname : /home/user40/18k61d680102/inv_sim
*
X_INVERTER01021 OUT IN INVERTER0102
V2 VDD GROUND DC 5V
V1 IN GROUND PATTERN 5 0 0 1n 1n 50n 00011011
*
.end

Result: Hence we designed CMOS Inverter and did circuit simulation, performed Transfer
Characteristics and Transient Analysis, Layout Design using Mentor graphics.
Exp. No.:02
Date:
Lambda Calculations for single MOS
Transistor Amplifier

Aim:
To perform Lambda based calculation for MOS Single transistor amplifierand to plot
transconductance graphs using Mentor graphics.

Apparatus:
 Mentor Graphics Tool.
 Personal Computer.

Theory:

So, let’s split the circuit in half and assume a virtual ground connected to the source of Q2.

Fig 2.1:single stage MOS amplifier

We can see that the circuit resembles the right-hand side of the drain-resistor version. As
stated in The Basic MOSFET Differential Pair, the magnitude of the differential gain of the
full drain-resistor diff pair is (gm × RD), and this means that the gain of one side of the
drain-resistor diff pair (AV,OS) is this same expression divided by two:
 AV,OS=gm×RD2AV,OS=gm×RD2

We can apply this same expression to the actively loaded pair, where the drain resistor is
now the small-signal output resistance of Q4. Don’t forget, though, that the diff pair
converts the output from differential to single-ended without loss of gain—in other words,
the factor-of-two reduction that occurs when we split the drain-resistor diff pair does not
apply to the active-load configuration.

Thus, we might conclude that the gain of the actively loaded differential pair (A V,AL) is the
following:

AV,AL=gm×ro4AV,AL=gm×ro4

But this would be wrong! It’s wrong because we are forgetting about the output resistance
of Q2. With the drain-resistor diff pair, it is more justifiable to ignore the output resistance
of Q2 because it is probably much larger than the drain resistor. As we saw with the
common-source amplifier discussed in the previous article, small-signal analysis places the
output resistance in parallel with the drain resistor.

If ro is much larger than RD, the parallel combination won’t be much different from RD. But
we have a whole new situation with the actively loaded circuit: r o of Q4 is likely to be quite
similar to ro of Q2, and thus we cannot ignore ro of Q2.

So we need a new circuit diagram:

Fig 2.2:Equivalent diagram

Now the overall output resistance is ro2||ro4, and we rightly conclude that the gain of the
actively loaded differential pair is the following:

AV,AL=gm×(ro4∥ro2)AV,AL=gm×(ro4∥ro2)

where gm refers to the transconductance of the amplifying transistors (Q1 and Q2), not that
of the current-mirror transistors (Q3 and Q4).

Measuring Lambda:
At this point, we want to predict the gain of our actively loaded diff pair—but we can’t,
because we need to know the value of ro4 and ro2.

For this we need to know lambda, because

ro=1λ×IDro=1λ×ID

I know what you’re thinking: Just look in the SPICE model!

Alas, it’s not always that simple. The MOSFET models we’re using in our simulations are
of the “BSIM3” variety, which means they are too sophisticated for the lambda-based
approach to channel-length modulation. In other words, you won’t find lambda in the
SPICE model because it has been replaced by other parameters that allow for a more
accurate simulation.

So, we have here a good opportunity to determine lambda empirically. How do we go

about that? Well, consider the following graph of drain current vs. drain-to-source voltage:

Fig 2.3: Threshold Graph

First, we apply a gate-to-source voltage that is high enough to bring the FET out of cutoff.
Then, holding VGSconstant, we increase the drain-to-source voltage. As VDS becomes high
enough to pinch off the channel, the FET enters saturation. If we ignore channel-length
modulation, the curve will be perfectly flat (as shown above), because increases in
VDS have no effect on drain current.

The following curve, in contrast, is not flat in the saturation region because it incorporates
channel-length modulation:

The gradual increase in saturation-region drain current corresponds to the additional

current flowing through the output resistance as the drain-to-source voltage increases. If we
extend this line back to the x-axis, we have lambda:

Fig 2.4: Drain To Source characteristics

As indicated in the plot, you can also measure the slope and convert this directly to ro.

Procedure:
1. Open X manager displayed on Desktop. Then press X start .
2. Give session name and give host address as 172.168.0.35.
3. Give protocol as SSH and give user name as user40 and enter password as user123.
4. Give execution command as 3Xternn(LinuxType2).
5. Tick the save checkbox that present in window and then click Save Button and then
Run.
6. Then the new window will be opened that is server window.
7. Give commands ascsh then click enter
8. Give command as source /home/software/cshrc/hep.cshrc and click enter button.
9. Now you have to make directory for your project , For this you need enter command
as mkdirprojectname .
10. For view your directory entercdprojectname.
11. Last command you need to give to open pyxis schematic window is da_ic& and then
click Enter button.
12. In the pyxis schematic Enter File on the tool bar and then click schematric and give
filename.
13. After to design cmos inverter click Library and after select devicelibrary and select
pmos 4pin and nmos 4pin transistors.
14. For VDD and Ground you need to click on Generic Library and select Vdd and
Ground..
15. All these are appeared on pyxis schematic window.
16. Select Add port in and add portout for input and outputs then click ESC key.
17. For Renaming ports click on NET and press Q button then a window will be opened
then rename net.
18. You have to rename transistors also. For transistors also the procedure is same like
above step.
19. Click on Check/save in tool bar, Then a console window will be opened , if any
errors in your design are there it shows in that window.
20. Click add in tool bar and click Generate symbol and tick Replace Existingand then
click Activate Symbol and then click on Choose shape button and click on Buffer
and click OK.
21. After click on Add circle and place it to buffer.
22. Again click Check/save.
23. Close all the windows.
24. For Simulating your design Click on File ↵New ↵schematic.
25. Give file name as inv0304_sim and click ↵ (Enter button )and click OK.
26. Give right click on schematic and select instance and choose symbol and select
previous created file (project name) and click ok.
27. Give port in and port out for the circuit.
28. Rename the ports as in and out.
29. Go to Library and click on Source Library, select pattern and dc.
30. For dc you need to add ground and vdd.
31. For pattern add ground.
32. Click check/save and correct if there are any errors.
33. Click Simulation on schematic Library.
34. Then awindow will be opened in that click on New design configuration and give
name as sim.
35. Click Lib/Temp/Inc then click include files and click on browse button then after
click on Browse location map and click on $ADK ↵Technologies
↵ic↵models↵ami05.mod ↵ok and then click Apply.
36. After go to library and then go import library and Browse location map and click
on $ADK ↵Technologies ↵ ic↵ models ↵ ami05.mod ↵ok and then click Apply.
37. Click on Analysis button.
38. Disable OP tick and enable DC tick.
39. Click sweep type as source.
40. Click on Symbol and select voltage shown by software and give start as 0v and stop
as 5v and step as 0.01 and click Apply and Ok
41. Select Transient Tick and click start time as 0ns and stop time as 1000n and click
Apply and OK.
42. Select Input and output with Cntrl button and click outputs on Schematic library ,
then a new window will be opened.
43. Give analysis as DC and task as plot and click add button.
44. After click Trans and task as plot and click add button and Apply and Ok &run.
45. Click on view waves.
46. Click on ASCII Files in schematic library and click NetListand Save the net list.
Circuit WaveForms :

Fig 2.5: Circuit Diagram of Single stage MOS transistor amplifier.

Fig 2.6: Schematic diagram of Single stage MOS transistor amplifier.

Fig 2.7: AC analysis.

Netlist:

* ELDO netlist generated with ICnet by 'user40' on Thu Mar 7 2019 at 16:03:51

.CONNECT GROUND 0

*
* Globals.
*
.global GROUND VDD

*
* Component pathname : /home/user40/18k61d680304/lambdab680304
*
.subcktLAMBDAB680304 OUT IN

C2 N$16 OUT 120000p

C1 IN N$15 120000p
R3 N$16 GROUND 0.15K NOISE=1
R2 VDD N$16 0.47K NOISE=1
R1 N$15 GROUND 100K NOISE=1
R5 VDD N$15 200K NOISE=1
M1 N$16 N$15 N$16 N$16 N L=0.35u W=1.4u M=1
.ends LAMBDAB680304

*
* MAIN CELL: Component pathname : /home/user40/18k61d680304/lambdab680304_sim
*
V3 IN GROUND DC 0V AC 1 0 SIN ( 1.5 15v 1Meg 0 0 )
 V1 VDD GROUND DC 5V
X_LAMBDAB6803041 OUT IN LAMBDAB680304
*
.end

Result:
Henceperformed Lambda based calculation for MOS Single transistor amplifier and
to plotted transconductance graphs using Mentor graphics.
Exp. No.:03
Date:
Simple Current Mirror and
Wilson Current Mirror

Aim:
To perform simple current mirror and Wilson current mirror Circuit, layout of the
current mirror circuits and to plot graphs using mentor graphics.

Apparatus:
 Mentor Graphics Tool.
 Personal Computer.

Theory:
Current mirror circuits generally consist two main transistor, although other devices such as
FETs can be used. Some current mirror circuits may use more than two transistors to enable
the level of performance to be improved.
The current mirror circuit gains its name because it copies or mirrors the current flowing in
one active device in another, keeping the output current constant regardless of loading.
The current being mirrored can be a constant current, or it can be a varying signal dependent
upon the requirement and hence the circuit.
Conceptually, an ideal current mirror is simply an ideal inverting current amplifier that
reverses the current direction as well or it is a current-controlled current source (CCCS). The
current mirror is used to provide bias currents and active loads to circuits.

Current mirror circuit:

The basic circuit of the transistor current mirror is shown in the diagram below. It comprises
two transistors, one of which has the base and collector connected and the other does not. The
base connections of both transistors are then linked, as are the emitters which are also taken
to ground.

Fig 3.1: Current mirror transistor circuit

In terms of the operation of the circuit, the base emitter junction of TR1 acts like a diode
because the collector and base are connected together.
The current into TRI is set externally by other components, and as a result there is a given
voltage built up across the base emitter junction of TR1. As the base emitter voltage on both
transistors is the same, the current in one transistor will exactly mirror that of the second,
assuming that both transistors are accurately matched. Therefore the current flowing into TR1
will be mirrored into TR2 and hence into the load R1.

Circuit limitations:
The two transistor current mirror circuit shown above is often quite adequate for most
applications. However it has some noticeable limitations under many circumstances.
 Current varies with change in output voltage: This effect occurs because the output
impedance is not infinite. This is because there is a slight variation of Vbe with the
collector voltage at a given current in TR2. Often the current may vary by about 25% the
output compliance range.
 Current matching dependent on transistor matching: The current mirroring is
dependent upon the matching of the transistors. Often the transistors need to be on the
same substrate if they are to accurately mirror the current.
To overcome some of these issues more advanced current mirror circuits cna be developed
and used.

Current mirror with emitter resistors:

One solution to the variation of current over the compliance range is to introduce a small
amount of resistance into the emitter of each transistor. Typically these resistors are chosen to
have a few tenths of a volt drop across them.

Fig 3.2: Current mirror transistor circuit with emitter resistors

For this circuit, both emitter resistors and transistors need to be matched. This is obviously
easy for the resistors where close tolerance resistors are easily available.

Wilson current mirror circuit:

Another variation of the basic current mirror circuit is referred to as the Wilson mirror or
Wilson current mirror.
Within the circuit, a third transistor is introduced. This transistor, shown as TR3 in the
diagram keeps the collector of TR1 at a voltage equivalent to two diode drops below the rail
voltage Vcc.
 Fig 3.3: Wilson current mirror transistor circuit

This overcomes the previous effect. Also the transistor without the short circuit collector base
connection becomes the programming terminal.

Current mirror circuits are very useful, especially within integrated circuits. The components
can easily be incorporated into the design for little cost. As such they enable balanced
currents to be supplied to circuits like differential pairs and the like and this ensures that their
operation is improved further. Current mirrors are not widely used outside IC technology in
view of the additional number of components required, but nevertheless the principles are the
same in both discrete form and when used within ICs.

Procedure:
1. Open X manager displayed on Desktop. Then press X start .
2. Give session name and give host address as 172.168.0.35.
3. Give protocol as SSH and give user name as user40 and enter password as user123.
4. Give execution command as 3Xternn(LinuxType2).
5. Tick the save checkbox that present in window and then click Save Button and then
Run.
6. Then the new window will be opened that is server window.
7. Give commands ascsh then click enter
8. Give command as source /home/software/cshrc/hep.cshrc and click enter button.
9. Now you have to make directory for your project , For this you need enter command
as mkdirprojectname .
10. For view your directory entercdprojectname.
11. Last command you need to give to open pyxis schematic window is da_ic& and then
click Enter button.
12. In the pyxis schematic Enter File on the tool bar and then click schematric and give
filename.
13. After to design cmos inverter click Library and after select devicelibrary and select
pmos 4pin and nmos 4pin transistors.
14. For VDD and Ground you need to click on Generic Library and select Vdd and
Ground..
15. All these are appeared on pyxis schematic window.
16. Select Add port in and add portout for input and outputs then click ESC key.
17. For Renaming ports click on NET and press Q button then a window will be opened
then rename net.
18. You have to rename transistors also. For transistors also the procedure is same like
above step.
19. Click on Check/save in tool bar, Then a console window will be opened , if any
errors in your design are there it shows in that window.
20. Click add in tool bar and click Generate symbol and tick Replace Existingand then
click Activate Symbol and then click on Choose shape button and click on Buffer
and click OK.
21. After click on Add circle and place it to buffer.
22. Again click Check/save.
23. Close all the windows.
24. For Simulating your design Click on File ↵New ↵schematic.
25. Give file name as inv0304_sim and click ↵ (Enter button )and click OK.
26. Give right click on schematic and select instance and choose symbol and select
previous created file (project name) and click ok.
27. Give port in and port out for the circuit.
28. Rename the ports as in and out.
29. Go to Library and click on Source Library, select pattern and dc.
30. For dc you need to add ground and vdd.
31. For pattern add ground.
32. Click check/save and correct if there are any errors.
33. Click Simulation on schematic Library.
34. Then awindow will be opened in that click on New design configuration and give
name as sim.
35. Click Lib/Temp/Inc then click include files and click on browse button then after
click on Browse location map and click on $ADK ↵Technologies
↵ic↵models↵ami05.mod ↵ok and then click Apply.
36. After go to library and then go import library and Browse location map and click
on $ADK ↵Technologies ↵ ic↵ models ↵ ami05.mod ↵ok and then click Apply.
37. Click on Analysis button.
38. Disable OP tick and enable DC tick.
39. Click sweep type as source.
40. Click on Symbol and select voltage shown by software and give start as 0v and stop
as 5v and step as 0.01 and click Apply and Ok
41. Select Transient Tick and click start time as 0ns and stop time as 1000n and click
Apply and OK.
42. Select Input and output with Cntrl button and click outputs on Schematic library ,
then a new window will be opened.
43. Give analysis as DC and task as plot and click add button.
44. After click Trans and task as plot and click add button and Apply and Ok &run.
45. Click on view waves.
46. Click on ASCII Files in schematic library and click NetListand Save the net list.
Circuit WaveForms :

Fig 3.4: Circuit Diagram of Simple Current Mirror.

Fig 3.5: Schematic diagram of Simple Current Mirror.

Fig 3.6: DC analysis.

Fig 3.7: AC analysis.

Fig 3.8: Circuit Diagram of WILSON Current Mirror.

Fig 3.9: Schematic diagram of WILSON Current Mirror.

Fig 3.10: DC analysis.

Fig 3.11: AC analysis.

Fig 3.12: Layout for Simple Current Mirror

Netlist:

Normal Current Mirror :

* ELDO netlist generated with ICnet by 'user40' on Wed Mar 20 2019 at 15:56:35
.CONNECT GROUND 0
*
* Globals.
*
.global VDD GROUND

*
* Component pathname : /home/user40/18k61d680304/cmirr
*
.subckt CMIRR OUT IN

R2 VDD IN 1K NOISE=1
R1 VDD OUT 1K NOISE=1
M2 OUT IN GROUND GROUND N L=0.35u W=1.4u M=1
M1 IN IN GROUND GROUND N L=0.35u W=1.4u M=1
.ends CMIRR

*
* MAIN CELL: Component pathname : /home/user40/18k61d680304/cmirr_sim
*
 I1 IN GROUND PATTERN 1mA 0 0 1n 1n 50n 00011011
I2 VDD GROUND DC 1mA
X_CMIRR1 OUT IN CMIRR
*
.end

Wilson Current Mirror:

* ELDO netlist generated with ICnet by 'user40' on Fri Apr 12 2019 at 10:42:24

.CONNECT GROUND 0

*
* Globals.
*
.global VDD GROUND

*
* Component pathname : /home/user40/18k61d680304/wilsoncmirr
*
.subckt WILSONCMIRR OUT IN

R4 VDD OUT 0.47K NOISE=1

R3 VDD IN 0.5K NOISE=1
R2 N$12 GROUND 0.1K NOISE=1
R1 N$10 GROUND 0.1K NOISE=1
M4 N$5 N$5 N$12 N$12 N L=0.35u W=1.4u M=1
M3 N$1 N$5 N$10 N$10 N L=0.35u W=1.4u M=1
M2 OUT IN N$5 N$5 N L=0.35u W=1.4u M=1
M1 IN IN N$1 N$1 N L=0.35u W=1.4u M=1
.ends WILSONCMIRR

*
* MAIN CELL: Component pathname : /home/user40/18k61d680304/wilsoncmirr_SIM
*
I2 VDD GROUND DC 1mA
I1 IN GROUND PATTERN 1mA 0 0 1n 1n 50n 00011011
X_WILSONCMIRR1 OUT IN WILSONCMIRR
*
.end

Result:
Hence performed simple current mirror and Wilson current mirror Circuit, layout of
the current mirror circuits and plotted graphs using mentor graphics.
Exp. No.:04
Date:
Current Sinks

Aim:
To perform simple current sink Circuit, layout of the current sink circuits and to
plot graphs using mentor graphics.

Apparatus:
 Mentor Graphics Tool.
 Personal Computer.

Theory:
Current sources and sinks are analysis formalisms which distinguish points, areas, or
volumes through which current enters or exits a system. While current sources or sinks are
abstract elements used for analysis, generally they have physical counterparts in real-world
applications; e.g. the anode or cathode in a battery. In all cases, each of the opposing terms
(source or sink) may refer to the same object, depending on the perspective of the observer
and the sign convention being used; there is no intrinsic difference between a source and a
sink.
In some cases, the term current source refers to a boundary where charge flows from
locations where it is not measured to locations where it is measured. In a similar fashion, a
current sink may refer to the boundary where charge flows from locations where it is
measured to locations where it is not measured. By analogy to the flow of water, a current
source would be like a mountain spring - water flows from its source (a hidden location
underground) to the surface where it is easily observed. Using the same analogy, a current
sink would be like water flowing down a drain - water travels from where it is observed to
where it is not observed.

Fig 4.1: Current sinks

Shown at right is a general two-compartment model to help illustrate the definition of current
sources or sinks. In this two-compartment model, the compartments are separated by a semi-
conductive barrier (gray). An observer, symbolized by the eye, can "see" only one
compartment at a time. Red arrows indicate the direction of flow of positive charges, while
black arrows indicate the direction of flow of negative charges. The pink and green
backgrounds are meant to symbolize different configurations, configuration 1 when charges
are flowing in one direction and configuration 2 when they are flowing in the opposite
direction. The difference between the left and right panels is simply the location of the "eye".
A source or a sink is defined by which compartment is viewable by the observer.

 A source is:
o A flow of positive charges from the "invisible" to the "visible" compartment (i.e.
toward the eye), or…
o A flow of negative charges from the "visible" to the "invisible" (away from the eye).
 A sink is:
o A flow of positive charges "away from the eye", or…
o A flow of negative charges "toward the eye".

In biology, the schematic barrier in the figure could represent a cell membrane, and as a
result, the two compartments could represent the inside and the outside of the cell. Generally
speaking the point of observation would be outside the cell. Thus the cell would be termed a
sink with respect to any flow of positive charges into it, and the cell would act as a source for
any positive charges flowing out of it. Note that when considering the flow of negative
charges, the definitions are reversed.

Procedure:
1. Open X manager displayed on Desktop. Then press X start .
2. Give session name and give host address as 172.168.0.35.
3. Give protocol as SSH and give user name as user40 and enter password as user123.
4. Give execution command as 3Xternn(LinuxType2).
5. Tick the save checkbox that present in window and then click Save Button and then
Run.
6. Then the new window will be opened that is server window.
7. Give commands ascsh then click enter
8. Give command as source /home/software/cshrc/hep.cshrc and click enter button.
9. Now you have to make directory for your project , For this you need enter command
as mkdirprojectname .
10. For view your directory entercd projectname.
11. Last command you need to give to open pyxis schematic window is da_ic& and then
click Enter button.
12. In the pyxis schematic Enter File on the tool bar and then click schematric and give
filename.
13. After to design cmos inverter click Library and after select devicelibrary and select
pmos 4pin and nmos 4pin transistors.
14. For VDD and Ground you need to click on Generic Library and select Vdd and
Ground..
15. All these are appeared on pyxis schematic window.
16. Select Add port in and add portout for input and outputs then click ESC key.
17. For Renaming ports click on NET and press Q button then a window will be opened
then rename net.
18. You have to rename transistors also. For transistors also the procedure is same like
above step.
19. Click on Check/save in tool bar, Then a console window will be opened , if any
errors in your design are there it shows in that window.
20. Click add in tool bar and click Generate symbol and tick Replace Existingand then
click Activate Symbol and then click on Choose shape button and click on Buffer
and click OK.
21. After click on Add circle and place it to buffer.
22. Again click Check/save.
23. Close all the windows.
24. For Simulating your design Click on File ↵New ↵schematic.
25. Give file name as inv0304_sim and click ↵ (Enter button )and click OK.
26. Give right click on schematic and select instance and choose symbol and select
previous created file (project name) and click ok.
27. Give port in and port out for the circuit.
28. Rename the ports as in and out.
29. Go to Library and click on Source Library, select pattern and dc.
30. For dc you need to add ground and vdd.
31. For pattern add ground.
32. Click check/save and correct if there are any errors.
33. Click Simulation on schematic Library.
34. Then awindow will be opened in that click on New design configuration and give
name as sim.
35. Click Lib/Temp/Inc then click include files and click on browse button then after
click on Browse location map and click on $ADK ↵Technologies ↵ic↵models
↵ami05.mod ↵ok and then click Apply.
36. After go to library and then go import library and Browse location map and click
on $ADK ↵ Technologies ↵ ic↵ models ↵ ami05.mod ↵ok and then click Apply.
37. Click on Analysis button.
38. Disable OP tick and enable DC tick.
39. Click sweep type as source.
40. Click on Symbol and select voltage shown by software and give start as 0v and stop
as 5v and step as 0.01 and click Apply and Ok
41. Select Transient Tick and click start time as 0ns and stop time as 1000n and click
Apply and OK.
42. Select Input and output with Cntrl button and click outputs on Schematic library ,
then a new window will be opened.
43. Give analysis as DC and task as plot and click add button.
44. After click Trans and task as plot and click add button and Apply and Ok &run.
45. Click on view waves.
46. Click on ASCII Files in schematic library and click NetListand Save the net list.
Circuit WaveForms :

Fig 4.2 : Circuit Diagram of Simple Current sink.

Fig 4.3: Schematic diagram of Simple Current Sink.

Fig 4.4: DC analysis.

Fig 4.5: AC analysis.

Fig 4.6: Layout for Simple Current Sink

Netlist:

Normal Current Sink :

* ELDO netlist generated with ICnet by 'user40' on Wed Mar 20 2019 at 15:56:35
.CONNECT GROUND 0
*
* Globals.
*
.global VDD GROUND

*
* Component pathname : /home/user40/18k61d680304/cmirr
*
.subckt CMIRR OUT IN

R2 VDD IN 1K NOISE=1
R1 VDD OUT 1K NOISE=1
M2 OUT IN GROUND GROUND N L=0.35u W=1.4u M=1
M1 IN IN GROUND GROUND N L=0.35u W=1.4u M=1
.ends CMIRR

*
* MAIN CELL: Component pathname : /home/user40/18k61d680304/cmirr_sim
*
 I1 IN GROUND PATTERN 1mA 0 0 1n 1n 50n 00011011
I2 VDD GROUND DC 1mA
X_CMIRR1 OUT IN CMIRR
*
.end

Result:
Hence performed simple current sink Circuit, layout of the current sink circuit and
plotted graphs using mentor graphics.
Exp.No.:05
Date:
Design of Differential Amplifier

Aim:
To perform design of differential amplifierand to plot graphs and to design layout
usingMentor graphics.

Apparatus:
 Mentor Graphics Tool.
 Personal Computer.

Theory:

Introductory studies of active circuits generally devote a significant amount of time to

standard single-ended amplifier configurations—e.g., common-source, common-gate,
emitter-follower. This is certainly a worthy endeavor in the context of becoming familiar
with transistor operation, small-signal analysis, and amplifier characteristics. But
the practical value of single-ended amplifier configurations is a different story—the fact is,
differential amplifiers dominate modern analog ICs. There are a few reasons for this:

 Differential amplifiers apply gain not to one input signal but to the difference between
two input signals. This means that a differential amplifier naturally eliminates noise or
interference that is present in both input signals.
 Differential amplification also suppresses common-mode signals—in other words, a
DC offset that is present in both input signals will be removed, and the gain will be
applied only to the signal of interest (assuming, of course, that the signal of interest is
not present in both inputs). This is particularly advantageous in the context of IC
design because it eliminates the need for bulky DC-blocking capacitors.
 The subtraction that occurs in a differential pair makes it easy to incorporate the
circuit into a negative-feedback amplifier, and if you’ve read the Negative Feedback
series, you know that negative feedback is about the best thing that could ever happen
to an amplifier circuit.
It is only sensible to expect these benefits to be accompanied by significant disadvantages,
but the nature of IC fabrication has rendered the differential configuration almost wholly
beneficial. Two concerns are 1) higher component count and 2) the importance of
symmetrical component characteristics. You can forget about number 1 because the cost of
adding a few more transistors to an IC is negligible. As for number 2, IC technology
happens to be very good at achieving consistency among the components within a chip
(this consistency is referred to as “matching”).
In this article, we will explore the basic MOSFET differential-amplifier configuration by
means of conceptual discussion and simulations (i.e., not too much math or complicated
circuit analysis). Because this topic is relevant primarily to IC implementation, we will use
an NMOS model that is specific to 0.35 µm CMOS technology;

A Pair of MOSFETs
This is the circuit:

Fig 5.1: Circiut diagram of Differential amplifier

Note the following:

 In real life, the current-source symbol would be replaced by a circuit that generates a
constant current. However, we want to keep things nice and simple for this
introductory analysis, so in our simulations we’ll use an ideal current source instead
of a constant-current circuit.
 An actual IC implementation of this circuit would replace the resistors with a current
mirror functioning as an “active load.” However, if our goal is to understand the
functionality of the differential pair, I think we should start with the resistor version.
 The differential pair is all about balance. Thus, for optimal performance the resistors
and MOSFETs must be matched. This means that the channel dimensions of both
FETs must be the same and that R1 must equal R2. The resistance value chosen for the
two resistors will be referred to as RD (for drain resistance).
DC Analysis:
Let’s determine the biasing conditions of this circuit when both inputs are grounded.

Fig 5.2: Dc analysis

The sum of the two drain currents I D1 and ID2 must equal IBIAS. We also know that the two
drain currents are equal because, in this idealized analysis, both halves of the circuit are
identical. Thus,

ID1=ID2=IBIAS2ID1=ID2=IBIAS2

Let’s assume for the moment that the transistors are in saturation. The equation for
saturation-mode drain current is the following:

ID=12μnCoxWL(VGS−VTH)2ID=12μnCoxWL(VGS−VTH)2

(We will ignore channel-length modulation throughout this article.) The drain current is
already established (by the current source) and the gates are tied to the ground node; this
means that the source voltage will settle on whatever value creates a gate-to-source voltage
(VGS) corresponding to a drain current of IBIAS/2. We’ll let the simulation figure this out for
us. The output voltages are easier: Calculate the voltage drop across the resistor as (I BIAS/2)
× RD, then subtract this voltage drop from the positive supply. Here is an example:

The output voltages are as expected. The source voltage seems reasonable considering that
the threshold voltage (VTH) for this SPICE model is about 0.5 V; the simulation is telling us
that the VGS corresponding to a drain current of 250 µA is about 0 V – (–725 mV) = 725
mV, which is about 225 mV above VTH.
Let’s go back to our assumption about the transistors being in saturation (aka “active
mode”). A MOSFET amplifier needs to remain in the saturation portion of its transfer
characteristic, because the gain is higher and more stable in the saturation region compared
to the triode region. To ensure saturation, the drain voltage must always be higher than the
gate voltage minus the threshold voltage:

VDS≥VGS−VTH ⇒ VGD≤VTHVDS≥VGS−VTH ⇒ VGD≤VTH

<v_{th}\]<v_{th}\]< p="" style="box-sizing: border-box;"> </v_{th}\]<v_{th}\]<>

In this example, the drain voltage (aka VOUT) is fixed at 2.05 V. This means that we have a
restriction on VIN: the common-mode input voltage cannot exceed 2.05 V + 0.5 V = 2.55
V, because when the input voltage reaches VTH volts above the drain voltage, the MOSFET
enters the triode region.

Procedure:
1. Open X manager displayed on Desktop. Then press X start .
2. Give session name and give host address as 172.168.0.35.
3. Give protocol as SSH and give user name as user40 and enter password as user123.
4. Give execution command as 3Xternn(LinuxType2).
5. Tick the save checkbox that present in window and then click Save Button and then
Run.
6. Then the new window will be opened that is server window.
7. Give commands ascsh then click enter
8. Give command as source /home/software/cshrc/hep.cshrc and click enter button.
9. Now you have to make directory for your project , For this you need enter command
as mkdirprojectname .
10. For view your directory entercdprojectname.
11. Last command you need to give to open pyxis schematic window is da_ic& and then
click Enter button.
12. In the pyxis schematic Enter File on the tool bar and then click schematric and give
filename.
13. After to design cmos inverter click Library and after select devicelibrary and select
pmos 4pin and nmos 4pin transistors.
14. For VDD and Ground you need to click on Generic Library and select Vdd and
Ground..
15. All these are appeared on pyxis schematic window.
16. Select Add port in and add portout for input and outputs then click ESC key.
17. For Renaming ports click on NET and press Q button then a window will be opened
then rename net.

18. You have to rename transistors also. For transistors also the procedure is same like
above step.
19. Click on Check/save in tool bar, Then a console window will be opened , if any
errors in your design are there it shows in that window.
20. Click add in tool bar and click Generate symbol and tick Replace Existingand then
click Activate Symbol and then click on Choose shape button and click on Buffer
and click OK.
21. After click on Add circle and place it to buffer.
22. Again click Check/save.
23. Close all the windows.
24. For Simulating your design Click on File ↵New ↵schematic.
25. Give file name as inv0304_sim and click ↵ (Enter button )and click OK.
26. Give right click on schematic and select instance and choose symbol and select
previous created file (project name) and click ok.
27. Give port in and port out for the circuit.
28. Rename the ports as in and out.
29. Go to Library and click on Source Library, select pattern and dc.
30. For dc you need to add ground and vdd.
31. For pattern add ground.
32. Click check/save and correct if there are any errors.
33. Click Simulation on schematic Library.
34. Then awindow will be opened in that click on New design configuration and give
name as sim.
35. Click Lib/Temp/Inc then click include files and click on browse button then after
click on Browse location map and click on $ADK ↵Technologies
↵ic↵models↵ami05.mod ↵ok and then click Apply.
36. After go to library and then go import library and Browse location map and click
on $ADK ↵Technologies ↵ ic↵ models ↵ ami05.mod ↵ok and then click Apply.
37. Click on Analysis button.
38. Disable OP tick and enable DC tick.
39. Click sweep type as source.
40. Click on Symbol and select voltage shown by software and give start as 0v and stop
as 5v and step as 0.01 and click Apply and Ok
41. Select Transient Tick and click start time as 0ns and stop time as 1000n and click
Apply and OK.
42. Select Input and output with Cntrl button and click outputs on Schematic library ,
then a new window will be opened.
43. Give analysis as DC and task as plot and click add button.
44. After click Trans and task as plot and click add button and Apply and Ok &run.
45. Click on view waves.
46. Click on ASCII Files in schematic library and click NetListand Save the net list.
Circuit WaveForms :

Fig 5.3: Circuit Diagram of Differential amplifier.

Fig 5.4: Schematic diagram of Differential amplifier.

Fig 5.5: Transient analysis.
 Fig 5.6: Ac analysis.

Fig 5.7: Layout for differential amplifier.

Netlist:

* ELDO netlist generated with ICnet by 'user40' on Wed Mar 13 2019 at 16:55:14

.CONNECT GROUND 0

*
* Globals.
*
.global GROUND VDD VSS

*
* Component pathname : /home/user40/18k61d680304/diffamp
*
.subcktDIFFAMP VOUT IREF VIN1 VIN2

M1 N$17 VIN1 IREF IREF N L=0.35u W=35u M=1

M4 N$17 N$17 VDD VDD P L=0.35u W=70u M=1
M2 VOUT VIN2 IREF IREF N L=0.35u W=35u M=1
M3 VOUT N$17 VDD VDD P L=0.35u W=70u M=1
.ends DIFFAMP

*
* MAIN CELL: Component pathname : /home/user40/18k61d680304/diffamp_sim
*
V1 VI2 N$12 DC 1V
I1 N$5 VSS DC 0.8mA
V6 N$12 GROUND AC 1 SIN ( 0 1nv 100k 0 0 0 )
V5 N$27 GROUND SIN ( 0 3mv 100k 0 0 0 )
V3 VSS GROUND DC 3.3V
V4 VDD GROUND DC 3.3V
V2 VI1 N$27 DC 1V
X_DIFFAMP1 VO N$5 VI1 VI2 DIFFAMP
*
.end

Result:
Henceperformed design of differential amplifierand plotted graphs and designed
layout using Mentor graphics