8/2/2018 Verilog for JK Flip-Flop – ElectroDitzy

ElectroDitzy

Verilog for JK Flip-Flop

Module:
module jk_ff_(J,K,En,R,P,clk,Q,Qbar);
input J,K,En,R,P,clk;
output reg Q,Qbar;

always@(posedge clk or En or R) //check clock’s positive edge or change in En or change in R.

begin
if (!En) // Top priority if En=0 output is ambiguous
begin
Q = 1’bX ;
Qbar = 1’bX ;
end
else if (!R) //if R=0 Q=0,Qbar=1. This Reset/Clear is Asynchronous.
begin
Q <= 1’b0 ;
Qbar <= 1’b1 ;
end
else if (!P) //if P=0 Q=1,Qbar=0. This Preset/Set is Synchronous
begin
Q <= 1’b1 ;
Qbar <= 1’b0 ;
end
else if (J == 1’b0 && K == 1’b0) // No change
begin
Q <= Q ;
Qbar <= Qbar ;
end
else if (J == 1’b0 && K == 1’b1) // Q=J and Qbar=K
begin
Q <= 1’b0 ;
Qbar <= 1’b1 ;
end
else if (J == 1’b1 && K == 1’b0) // Q=J and Qbar=K
begin
Q <= 1’b1 ;
Qbar <= 1’b0 ;
end
https://electroditzy.wordpress.com/2014/02/08/verilog-code-for-jk-flipflop-with-asychronous-resetclear-synchronous-presetset-and-enable/ 1/3
8/2/2018 Verilog for JK Flip-Flop – ElectroDitzy

else if (J == 1’b1 && K == 1’b1) // Toggle

begin
Q <= Qbar ;
Qbar <= Q ;
end

end

endmodule

Test Bench:

module testing_jk_ff;
reg i1,i2,Enable,clock,reset,preset;
wire q,qcomp;

jk_ff_ tb(.J(i1),.K(i2),.En(Enable),.R(reset),.P(preset),.clk(clock),.Q(q),.Qbar(qcomp));

initial
begin
clock = 0;
forever begin
#5 clock = ~clock;
end
end
initial
begin

Enable = 1’b1; i1 = 1’b0; i2 = 1’b1; reset = 1’b1; preset =1’b1;

#2 $monitor ($time,”R=%b P=%b E=%b J=%b K=%b Q=%b Qbar=%b “,reset,preset,Enable,i1,i2,q,qcomp);
Enable = 1’b1; i1 = 1’b0; i2 = 1’b1; reset = 1’b1; preset =1’b1;
#2 $monitor ($time,”R=%b P=%b E=%b J=%b K=%b Q=%b Qbar=%b “,reset,preset,Enable,i1,i2,q,qcomp);
Enable = 1’b1; i1 = 1’b1; i2 = 1’b0; reset = 1’b1; preset =1’b1;
#10 $monitor ($time,”R=%b P=%b E=%b J=%b K=%b Q=%b Qbar=%b
“,reset,preset,Enable,i1,i2,q,qcomp);
Enable = 1’b1; i1 = 1’b1; i2 = 1’b1; reset = 1’b1; preset =1’b1;
.
.//covering all the possible inputs
.
.
Enable = 1’b0; i1 = 1’b1; i2 = 1’b0; reset = 1’b1; preset =1’b0;
#1 $monitor (“R=%b P=%b E=%b J=%b K=%b Q=%b Qbar=%b “,reset,preset,Enable,i1,i2,q,qcomp);
Enable = 1’b0; i1 = 1’b1; i2 = 1’b1; reset = 1’b1; preset =1’b0;
#1 $monitor (“R=%b P=%b E=%b J=%b K=%b Q=%b Qbar=%b “,reset,preset,Enable,i1,i2,q,qcomp);

end
endmodule

https://electroditzy.wordpress.com/2014/02/08/verilog-code-for-jk-flipflop-with-asychronous-resetclear-synchronous-presetset-and-enable/ 2/3
8/2/2018 Verilog for JK Flip-Flop – ElectroDitzy

FEBRUARY 8, 2014 BY SOME BODY VERILOG, JK FLIPFLOP, RESET, CLEAR, ASYCHRONOUS,

PRESET, SET, SYNCHRONOUS, TESTBENCH, ENABLE

BLOG AT WORDPRESS.COM.

https://electroditzy.wordpress.com/2014/02/08/verilog-code-for-jk-flipflop-with-asychronous-resetclear-synchronous-presetset-and-enable/ 3/3