Summary of Commodity Hardware Today

Different Ram Types

Dynamic RAM (DRAM) and Static RAM(SRAM) are commonly used. SRAMs are more
expensive than DRAMs. Machines don't use a single type of RAM because of cost.

Static Ram

These use transistors. Their state is binary. The states are stable if power is supplied. No refresh
cycles are needed. Data can be immediately read after setting the necessary lines. For power
efficiency speed of SRAM can be sacrificed. Easy to use because of the simple interface.

Dynamic Ram

These have a simple design which consists of a single transistor and a capacitor. The state is stored
in the capacitor. Reading and writing take time as capacitors need time to charge and discharge.
Reading the cell takes drains the charge. Therefore recharging must be done after each read
operation. Recharging introduces a delay. Stored charge dissipates fast and this dissipation is called
leakage. Refresh is needed because of leakage. In most RAMs today refresh time is 64ms. RAM
cannot be used at the refreshing time. Since the stored charge is very small the output from a cell
must be amplified to detect the levels properly. Because of the above-mentioned delays, DRAM
speed is limited. For commodity systems, DRAM is used over SRAM for main memory because of
cost.

DRAM Access

When a program requests a memory location using a virtual address provided by the OS, the
processor converts it into a physical address and the memory controller chooses the respective
memory chip. Memory cells need to be individually selected to be used. Memory cells are arranged
as a 2d array, with each individual cell indexed by a row number and a column number. The address
is encoded and also multiplexed to select row and column to reduce the number of wires. And the
number of wires depend on the hardware. Synchronous DRAM (SDRAM) and Double Data Rate
DRAM (DDR) are the technologies used currently. SDRAM works according to a clock which is
provided by the memory controller. The clock determines the speed of FSB. Today SDRAM uses 64
bits for a single data transfer. Hardware and software pre-fetching has to be used to improve access
performance especially when non-sequential memory access is needed.

Reading Access Protocol

At the start of a read cycle, the memory controller sets the row address in the address bus. The RAS
is set to notify the provided address is a row and the chip starts latching the row which was
addressed. The column address is set on the address bus and (CAS) is set after the RAS-to-CAS
delay (tRCD) to notify the address is for a column. The chip takes time ready for data transportation
and this time is called CAS latency(CL) and it depends on the quality of controller, motherboard
and DRAM module. Since transferring only one word is a waste the number of words to transfer
can be specified to the DRAM module by the controller.

Pre-charge

Before a new row selection can be made the latched row must be disabled and the new row must be
precharged. This precharge cause a delay. Precharge command issuing must wait until the transfer is
done.T he row can be selected after tRP(Row precharge time) cycles from when the precharge
command was issued.The programmer has to do his/her part to reduce the time between memory
transfers. SDRAM module needs time after a RAS signal before it can precharge another row
(denoted as tRAS).

DRAM Types

SDR(Single Data Rate) SDRAM

The memory cell and the data transfer frequencies are the same. To increase throughput, the
frequency must be increased. But this increases energy consumption. SDR DRAMS were known by
their frequency.

DDR (Double Data Rate) SDRAM

DDR SDRAM improves throughput without increasing frequencies. DDR 1 doubles the rate of
transmission by transferring data in both the falling and rising edges of the clock. To achieve this,
an IO buffer is used. In each cycle, the cell array sends two bits to the buffer.This is called a double-
pumped bus. DDR1s were known by the transfer rates a module can maintain. DDR 2 also doubles
the bus frequency. By giving I/O buffer 4 bits per cycle, the frequency of the cells is kept the same
as DDR1. DDR 3 uses less voltage than DDR 2. The bus runs at a 4f frequency where f is the
frequency of cell array. DDR 4 has been around for a while and DDR 5 is expected to be available
in 2019. DDR modules are described using a special notation: w-x-y-z-T. Where w = CAS Latency
(CL) , x = RAS-to-CAS delay (tRCD), y = RAS Precharge (tRP), z = Active to Precharge delay (tRAS)
, T = Command Rate

Problems of DDR

The increased bus frequency of DDR makes is harder to make data busses parallel. If modules are
chained the signals get more distorted at each module. DDR2 spec permits 2 modules per bus and
DDR3 spec permits 1 per bus. Because of this, commodity motherboards are constrained to use less
than 5 DDR 2 or 3 modules.

Other DRAM Technologies

For large server machines, Intel uses Fully Buffered DRAM. FB DRAM uses DDR 2 modules with
a memory controller connected. FB-DRAM uses a serial bus. This allows more modules/channels
and reduces costs. There are also drawbacks of FBDRAM such as Multiple DIMMs can causing
delays at each node in the chain and the high energy cosumption of the chip driving the serial. FB-
DRAM is faster than DDR2 and DDR3 with the same memory and frequency.

DMA(Direct Memory Addressing)

• Devices other than the CPU must also to access memory.

• DMA can be used for this purpose to access memory without tunneling data through the CPU.
• DMA can cause CPU to slow down as the competition for FSB is high.
• One way to reduce this is by using memory on nodes which are not affected by DMA traffic.

References:

Drepper, U. (2007, November 21). What Every Programmer Should Know About Memory.
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