A Study of Recent Advances in Cache Memories
M. Tariq Banday
Department of Electronics & Inst. Technology
University of Kashmir, Srinagar, India
E-mail: sgrmtb@yahoo.com
Abstract—Registers within a processor, cache within, on, or
outside the processor, and virtual memory on the disk drive
builds memory hierarchy in modern computer systems. The
principle of locality of reference makes this memory hierarchy
work efficiently. In recent years, cache organizations and designs
have witnessed several advances that have not only improved
their performance such as hit rates, speed, latency, energy
consumption, etc. but various new designs and organizations for
chip multi-processors such as multilevel caches, Non-Uniform
Cache Access (NUCA), hybrid caches, etc. have also emerged.
This paper presents a study of current competing processors in
terms of various factors determining performance and
throughput of cache organization and design. To evaluate their
performance and viability, it reviews recent cache trends that
include hybrid cache memory, non-uniform cache architecture,
energy efficient replacement algorithms, cache memory
programming, software defined caches and emerging techniques
for making cache reliable against soft errors. It discusses the pros
and cons of emerging cache architectures and designs.
Keywords – Cache Memory; Cache Design; Hybrid Cache
Memory; Cache Performance; Memory Programming; Software
Defined Cache
I. INTRODUCTION
To reduce memory access time, it is desired to have
memory with least access time that never exhausts. An efficient
and economical method to achieve this is through a few levels
of memory constituting memory hierarchy. Levels close to the
processor are fast, smaller in capacity and expensive in
comparision to those away from it. The memory hierarchy
works in a way that the low capacity, more expensive and
faster memories are supplemented by high capacity, cheaper
and slower memories. The principal of locality of reference is
the key to the success of this organization because as one
moves down the memory hierarchy, frequency of access
decreases.
Memory access has temporal and local characteristics. The
processor often makes accesses to instructions and data (loci of
reference) from locations that might already be in use or are
near the current address. The temporal locality is due to the use
of loops, which reuse data and instructions. A program for
short duration distributes memory references non-uniformly
throughout its address space, which remain same for long
duration. The local characteristics is because the address space
is divided into small sized segments. Cache memories are used
to keep data and instructions from portions of memory that are
currently accessed by the processor close to it. Cache memories
deliver data at much faster speed to the processor as compared
to the main memory.
978-1-4799-6629-5/14/$31.00 2014
c IEEE
Munis Khan
School of Electronics and Communication Engineering
SMVD University, Katra, India
E-mail: munis819@hotmail.com
II. CACHE DESIGN STRATEGY
The processor has three main units, namely, instruction
unit, execution unit, and storage unit. Instruction fetch and
decode is performed by the instruction unit. The execution unit
is responsible for logical and arithmetic operations and
executing an instruction. The storage unit establishes an
interface through a temporary store between the other two
units. The major components of the storage unit are: cache
memory, translator, and Translation Look-aside Buffer (TLB).
An Address Space Identifier Table (ASIT), a Buffer
Invalidation Address Stack (BIAS) and write through buffers
may also be present in the storage unit.
Technology has permitted fabrication of chips containing
over two million transistors, of which only some portion is
required to build a powerful processor. To reduce inter-chip
data transfers which could lead to higher memory access time,
on-chip memory is placed in the processor. Table 1 shows
specifications and cache design strategy of a few recent
processors produced by Intel and AMD.
The cache organization is determined by the mapping
technique. A mapping technique maps larger number of main
memory block into fewer lines of cache and the tag bits within
each cache line determine which mapped block of main
memory is currently present in a particular cache line. Out of
the three possible approaches i.e. direct, associative and set
associative, set associative caches are considered best due to
their better hit rate and less access time. However, it has been
reported that beyond a certain point, increasing cache size has
more of an impact than increasing associativity.
Replacement algorithm plays a vital role in the design of
cache memory because it makes the decision to select a line of
cache is to be replaced with the desired block of main memory.
Least Frequently Used (LFU), First in First Out (FIFO) and
Least Recently Used (LRU) are algorithms which may be used
for making such decisions. LRU is the most effective algorithm
because besides its easy implementation, more recently used
words are more likely to be referenced again.
Write Caching, Write Back and Write Through are the
write policies that decide how consistency is maintained
between cache lines and their corresponding blocks in main
memory. Considerable traffic is generated in case of write
through policy and in write back policy single bit error of any
type cannot be tolerated unless ECC (Error Correcting Code) is
provided. Write caching is a combination of write through and
write back caching in which a small fully-associative cache is
placed behind a write through cache.
398
 TABLE 1. SPECIFICATIONS OF AMD AND INTEL PROCESSORS

Design Power
Replacement
Algorithm &
Architecture

Write Policy
Clock Speed

Data Width

Number of
Bus Speed

Multiplier
Processor

Mapping,
L2 Cache

L3 Cache
LI Cache

Thermal
Threads

(K/MB)

(Watts)
Caches
Micro-
Clock

Cores
MHZ

(MB)
(bits)

(KB)
AMD Processors
Opteron 3200 I: 12x64
2500 X K 10 64 12 12 12x512 2x6 NPA 3 140
6180 MHZ D: 12x64
Phenom 533* I: 4x64 2
2600 13 K 10 64 4 4 4x512 NPA 3 140
X4 9950 MHZ D: 4x64 shared
Athelon 4100 Pile- I: 2x64
3800 X 64 4 4 2x2MB Nil NPA 2 100
X4 760 MHZ driver D: 2x16
A 10 4400 Pile- I: 2x64
4100 X 64 4 4 2x2MB Nil NPA 2 100
6800K MHZ driver D: 4x16
Legends: I-Instruction Cache; D-Data Cache; *: 533 MHz Memory controller; One 2000 MHz 16-bit Hyper Transport link.
Intel Processors
Core i3 5 GT/s Sandy I: 2x32 3
2500 25 64 2 4 2x256 NPA 3 35
2100T DMI Bridge D: 2x32 shared
Core i5 2.5 GT/s I: 4x32 8
2800 21 Nehalem 64 4 4 4x256 NPA 3 95
760 DMI D: 4x32 shared
Core i7 2.5 GT/s I: 4x32 8
2933 22 Nehalem 64 4 8 4x256 NPA 3 95
875K DMI D: 4x32 shared
Core i7 6.4 GT/s I: 6x32
3467 26 Westmere# 64 6 12 6x256 12 shared NPA 3 130
990x* DMI D: 6x32
Legends: I-Instruction Cache; D-Data Cache; #: Nehalem (Westmere); *: Extreme Edition; NPA: Not Publically Available.

More often L1 cache consists of L1 data cache and L1 been conducted to design efficient hybrid cache memory
instruction cache. Due to the ability of balancing load between systems with non-volatile memory.
fetched instructions and data, the unified cache exhibits a TABLE 2. COMPARISON OF VARIOUS MEMORY TECHNOLOGIES
higher hit rate as compared to split cache. On the other hand
split cache design eliminates the problem of contention Feature SRAM eDRAM MRAM PRAM
between the fetch/decode and execution units. This contention Density Low High High Very High
can degrades performance by interfering with efficient use of Speed Very Fast Fast
Fast Read Slow Read
instruction pipeline. Unfortunately, many implementation Slow Write Very Slow Write
Dynamic Low Read Medium Read
details of processors such as mapping function, replacement Power
Low Medium
High Write High Write
algorithm and write policy are not publicly available. In Leak Power High Medium Low Low
general AMD processors and x86 processors from Intel employ Non-volatile No No Yes Yes
direct-mapped L1 cache, and L2 cache is usually between 2 to
4 way set associative mapped. The L3 and higher caches could Wu et al [1] evaluated several possibilities to accommodate
be between 16-way to 64-way set associative. Most of them on-chip cache hierarchies based on Hybrid Cache Architecture
use least recently used replacement policy, without much (HCA). The study evaluated Level Hybrid Cache Architecture
variation and a write-back cache. (LHCA) and Region based HCA (RHCA). The LHCA (inter
cache level) used desperate memory technology to make levels
III. HYBRID CACHE MEMORY BASED ON SRAM-MRAM in a cache hierarchy and provided 7% geometric mean IPC
(intruction per cycle) improvement over baseline cache while
Magnetic Random Access Memory (MRAM) and phase
as RHCA (intra cache level) partitioned a single level cache
change Random Access Memory (PRAM) that are non-volatile
into multiple regions and provided an improvement of 12%
and energy efficient thus making them suitable for future
IPC over baseline cache under same area constraints. To
computing. However, they suffer from drawbacks because of
alleviate the performance degradation caused by long access
limited endurance and long write latency. To overcome these
latency of MRAM with small SRAM cache, a way partitioned
issues, a hybrid cache memory system consisting of both
hybrid cache memory system constructed with SRAM and
volatile and non-volatile memory is actively investigated.
MRAM was proposed by Lee et al [2]. The SRAM tecnology
Notable features of SRAM, embedded Dynamic RAM was used to built level 1 cache where as level 2 caches were
(eDRAM), MMRAM and PRAM are presented in table 2. It is manufactured using S, D and MRAM technologies. Using
evident that different cache technologies excel in one field but various benchmark programmes it was found that there is a
fall behind in others. Consequently, a cache designed by significant reduction in the average memory access time
employing different technologies may outperform its (AMAT) and power consumption for hybrid caches in
counterparts. As the capacity of cache becomes larger, more comparision to homogenous SRAM architecture.
sophisticated hybrid memory system architecture and operation
The energy efficiency and performance cannot be
mechanism can deliver superior performance and energy
improved simply by adopting MRAM as L2 or L3 memory in
efficiency than the conventional cache memory system with
the conventional memory hierarchy and the best cache
only SRAM and/or MRAM. Limited studies [1], [2], [3] have

2014 International Conference on Contemporary Computing and Informatics (IC3I) 399

organization depends on the capacity of L2 cache system [3].
When capacity of L2 is less than 2MB, the L2 cache system
with SRAM delivers best performance and ED product.
MRAM shows best energy efficiency and ED product with the
L2 cache capacity from 2MB to 4MB. The simplified way
partitioned hybrid cache memory system provides best ED
product when L2 cache capacity is over 4MB. The adoption of
non-volatile memory like MRAM in the cache memory system
is accelerating due to the increase in cache capacity of current
systems. Various issues that need further investigation include
the study of cache memories based on SRAM-MRAM
represented cache performance in context of single-threaded
execution, improving thermal reliability and endurance.
IV. NON-UNIFORM CACHE ACCESS
In a larger cache, the processor is able to access data close
to it much more quickly as compared to the data far from it.
The wire delays caused due to data residing far away from
processor is addressed through Non-Uniform Cache Access
(NUCA). It uses a switched network to allow data to migrate to
different cache regions based on their frequency of access.
Figure 1 adopted from Kim et al [4] shows different L2 cache
architectures. Figure 1(a) shows uniform cache architecture
also called traditional cache. The performance of this
architecture is poor when the cache size is over 4MB because
of internal wire delays and limited ports. Figure 1(b) shows
ML-UCA, a multi-level (L2 and L3) cache. To support
multiple parallel access, in it both levels of cache are
aggressively banked. In this design, extra space is consumed
because inclusion is enforced. To overcome this, a cache
supporting non-uniform access as shown in figure 1 (c) was
proposed. In this, placement of data in more than one bank is
avoided by statically determining banks. This type of cache is
called S-NUCA-1.

Fig. 1. Architectures of Level-2 Caches, adapted from [4]

An extensive study, first of its kind to compare the
performance of each of the above discussed cache schemes
with a set of 16 benchmarks were carried out by Kim et al [5].
Figure 2 shows the comparative evaluation of 16 MB/50nm
IPC obtained from UCA, S-NUCA-1, ML-UCA, S-NUCA-2,
DN-best (best D-NUCA policy), and an ideal D-NUCA upper
bound. When the delay to route across a cache is significant,
the performance can be improved considerably by partitioning
the cache into more banks. However, the problem of significant
area overhead present in S-NUCA-1 for larger number of
banks can restrict partitioning of banks. This problem is
addressed by S-NUCA-2 cache architecture shown in figure 1
(d). A 2D switched network is used in static NUCA instead of
private per-bank channels. Dynamic NUCA (D-NUCA)
scheme improves cache performance over S-NUCA as it
adaptively places data close to the requesting core [4]. It
involve a combination of placement, migration, and replication
strategies. Placement and migration dynamically, places data
close to cores that use it, reducing access latency. Replication
makes multiple copies of frequently used lines, reducing
latency for widely read-shared lines (e.g., hot code), at the
expense of some capacity loss, as depicted in figure 1 (e).

1.4 1.4 1.4 1.4 1.4 1.4

1.2 1.2 1.2 1.2 1.2 1.2
1 1 1 1 1 1
0.8 0.8 0.8 0.8 0.8 0.8
0.6 0.6 0.6 0.6 0.6 0.6
0.4 0.4 0.4 0.4 0.4 0.4
0.2 0.2 0.2 0.2 0.2 0.2
0 0 0 0 0 0
256.bzip2 176.gcc 197.parser 300.twolf 179.art 181.mcf
Fig. 2: IPC, 16MB Cache Performance

It was found that DN-best outperformed on all benchmarks
except mgrid, gcc and bt. DN-best offers more stable
performance. The IPC result of DN-best was found only 16 %
worse. It signifies that performance of DN-best is close to ideal
and is unlikely to benefit from better migration policies or
compiler support. The flexibility and scalability of NUCA
memory systems will benefit emerging chip multiprocessor
(CMP) architectures because NUCA memory system provides
relatively faster cache access as compared to UCA only when
cache size exceeds some limit. Therefore, cache access
techniques can be modified to work faster at lower levels (L1)
that have smaller sizes.
V. ENERGY EFFICIENT REPLACEMENT ALGORITHM
Storage systems consume a significant energy in data
centers raising energy consumption concerns and requirement

400 2014 International Conference on Contemporary Computing and Informatics (IC3I)

for power management schemes for disks [6]. PA-LRU (power
aware replacement algorithm) [7] was proposed to selectively
keep away active blocks from “inactive” disks for longer
period in the storage cache in order to extend idle period
lengths of these disks. It was found that this reduced the energy
consumed by the disks significantly due to their ability to stay
in low power modes for long periods and spin up and down
only a few times. However, it required cumbersome tuning for
each workload in PA-LRU. To make tuning simple, Zhu et al
[8] proposed PB-LRU (partition based LRU). PB-LRU, using
replacement algorithm divides cache into separate partitions,
which are managed separately. New design of energy efficient
replacement algorithms for cache memories for single disks
and modification of existing ones to work with multispeed
disks are highly desired.
VI. REPLACEMENT ALGORITHM FOR FLASH MEMORY
Since the inception of mobile embedded systems, the use
of flash memories has became more and more evident due to
their small and lightweight form factor and low power
consumption. For disk based storage systems, the number of
memory hits is the only concern in most of the operating
systems. Replacement algorithm for flash memories should
also consider replacement cost caused by selecting dirty
victims besides hit count. A Clean-First LRU (CFLRU)
replacement policy was proposed by Park et al [9] in which the
LRU is split into working region and the clean-first region. It
evicts clean pages preferentially in the clean first region. When
evaluated in a file system based buffer cache using block
access, a 28.4% reduction in average replacement cost for swap
system and 26.2% reduction in buffer cache in comparison to
LRU was found. A serious problem may arise in situations
where illegal shutdowns occur because CFLRU and LRU
algorithms retain dirty pages in the SDRAM cache. Therefore,
it has been suggested to make use of CFLRU algorithm with
journaling file system. Future algorithms need to be
incorporated for better performance of replacement algorithm
in flash memories.
VII. ADAPTIVE MULTI-LEVEL CACHE HIERARCHY
In order to minimize latency time and optimize the
performance, efficient cache hierarchy is necessary. Different
architectures implement different cache topologies. A cache
topology for a 16 core CMP in which each of Y number of L2
slice is shared by X cores and their L1 caches, each of Z
number of L3 slice is shared by Y number of L2 slices is
represented as (X:Y:Z). In order to have highest throughput,
the best configuration varies with time during the execution of
the workload [10]. In order to deal with diverse range of
applications, “One cache-topology-fits-all” philosophy is
inadequate. To cater this requirement, Shekhar et al [10],
proposed a reconfigurable adaptive multi-level cache hierarchy
called MorphCache. It permits different cache topologies to co-
exist together with the same architecture by dynamically tuning
a multi-level cache topology in a CMP. The average
throughput and harmonic mean of multithreaded and multi-
programmed workloads when evaluated on a 16 core CMP
significantly improved using MorphCache. Although beyond
16 cores the reconfigurable MorphCache does not work
properly, it shows good results with processors having lesser
2014 International Conference on Contemporary Computing and Informatics (IC3I)
cores. Therefore, dynamic cache architectures need to be
implemented to carter to the needs of multi core processors
having more than 16 cores.
VIII. MEMORY HIERARCHY PROGRAMMING
Owing to the increase in the number of parallel processing
units and the concerns for efficient utilization of memory
bandwidth, the need to develop new programming abstractions
for memory management in both stream architectures and
multi-core processors have gained focus. To facilitate program
correctness and performance, explicit memory management is
required to transfer data between memories on the chip and off
the chip. Fatahalian et al [11] proposed Sequoia, a
programming model that places a programmer in explicit
control of the movement and placement of data at all levels of
memory hierarchy through first class language mechanism. The
Sequoia provides limited set of abstractions by taking a
practical approach to portable parallel programming that can be
implemented efficiently. Sequoia requires hierarchical
organization in programs that encourage hierarchy-aware,
parallel divide-and-conquer programs. Each function is called
in a chain to accept arguments by a space limited procedure,
thus occupying comparatively less storage than those of the
calling functions. Sequoia is in under development, but has a
great scope for the future memory hierarchies.
IX. SCALABLE SOFTWARE-DEFINED CACHES
Shared last-level caches, widely used in chip-
multiprocessors (CMPs) face two fundamental limitations:
firstly, the latency and energy of shared caches degrade as the
system scales up and secondly, when multiple workloads share
the CMP, they suffer from interference in shared cache
accesses. Unfortunately, prior research addressing one issue
either ignores or worsens the other: Ideally, a cache should
both store data close to where it is used and at the same time
allow its capacity to be partitioned, enabling software to
provide isolation, prioritize competing applications, and
increase cache utilization. NUCA techniques reduce access
latency but are prone to hotspots and interference. The cache
partitioning techniques only provide isolation but do not reduce
access latency. Nathan et al [12] proposed Jigsaw, a technique
that jointly addresses the scalability and interference problems
of shared caches. Jigsaw implements efficient hardware
support for shared cache management, monitoring, and
adaptation. The resource-management algorithms develop a
system-level runtime that leverages Jigsaw to both maximize
cache utilization and place data close to where it is used.
Jigsaw lets software combine multiple bank partitions into a
logical, software-defined cache, which is called a share. By
mapping data to shares, and configuring the locations and sizes
of the individual bank partitions that compose each share.
Software has full control over both where data is placed in the
cache and the capacity allocated to it. Jigsaw efficiently
supports reconfiguring shares dynamically and moving data
across shares and implements monitoring hardware to let
software find the optimal share configuration efficiently.
An evaluation of Jigsaw using extensive simulations of 16
and 64-core tiled CMPs proved that it improves cache
performance by up to 2.2x (18% avg) over a conventional
shared cache, and significantly outperforms state-of-the-art
401
NUCA and partitioning techniques. Table 3 compares Jigsaw
with competing cache partitioning techniques in terms of their
capacity, latency, control, isolation, and directory. It is evident
that jigsaw outperforms all cache partitioning schemes.
TABLE 3. COMPARISON OF CACHE PARTITIONING SCHEMES
Capacity Directory-
Scheme Capacity Latency Isolation
Control
Jigsaw High Low Yes Yes
Private Caches Low Low No Yes
Shared Caches High High Yes No
Partioned
High High Yes Yes
Shared Caches
Private-Based
Intermediate Low Yes No
D-NUCA
Shared-Based
Intermediate Low No No
D-NUCA
X. CACHE RELIABILITY AGAINST SOFT ERRORS
The susceptibility of on-chip caches to soft errors is
increasing rapidly as microprocessors are continuously scaled
down and because of energetic particle strikes such as alpha
particles and high-energy neutrons from decaying radioactive
impurities in interconnecting materials and packaging [13]. In
order to protect information integrity various coding schemes
[14] are used in register files, latches, and on-chip caches for
reliable computing. These schemes provide different degrees of
reliability at different energy, hardware, and performance costs.
Wang et al [15] conducted a comprehensive studies and
characterization on the reliability behavior of cache memories
including soft errors. The study proposed a framework for the
development of new lifetime models for tag arrays and data
residing in both instruction and data cache. These models
facilitated characterization of cache vulnerability. The
proposed lifetime model classifies phases for each data item
into vulnerable and non-vulnerable phases. This classification
is based on their previous and current activity. An error may
propagate to level 2 cache or the processor through dirty line
write back or load operations. Temporal Vulnerability Factor
(TVF) was proposed as a measure of cache vulnerability. It is
percentage of data items present in vulnerable phases and is
indicative of cache reliability. During the study, major
contributors to vulnerable phases were identified in both
instruction and data caches and cache reliability schemes for
these phases were proposed. These include: Dead-Time-Based
Early Write-Back (DTEWB), Multiple Dirty Bits (MDB),
Clean Cache-Line Invalidation (CCI), Narrow-Width Value
Compression (NWVC), Cache-line Scrubbing (CS) Combined
and CS-CCI. Two main vulnerable phases are WPL and
FWPL. WPL (write-replace) is the life time phase between the
last write and the replacement without any read in between.
FWPL is the lifetime phase between first write and the
replacement of a dirty cache line. While reducing the WPL and
FWPL vulnerable phases of data and tag arrays in the write
back data cache, the energy consumption of L2 caches
increases in DTEWB. Reducing the vulnerable phases (mainly
WPL) of the data array in the data cache by preventing writing
back clean data items to the L2 cache may incur overhead of
additional dirty tag bits to reduce TVF in MBD scheme.
Reducing the RR and RH vulnerable phases of the data and tag
arrays in both data and instruction caches in CCI scheme may
result in performance loss when the invalidated cache-lines are
402 2014 International Conference on Contemporary Computing and Informatics (IC3I)
accessed lately by the CPU. In order to mask leading zero’s
additional narrow tag bits are needed in case of NWVC scheme
to reduce all vulnerable phases by exploiting the narrow width
values in the data array in the data cache. To reduce the RR and
RH vulnerable phases of the data and tag arrays in both the
data and instruction caches, the scrubbing scheme dramatically
increases the accesses to the L2 cache. It results in performance
less
Yes
loss in instruction cache. By combining the DTEWB, MDB,
No CCI and NWVC schemes, there is a minor performance loss
Yes and energy overheads. By combining the CS and CCI schemes,
Yes there is minor performance loss and a moderate energy increase
in the L2 cache.
No
XI. DISCUSSIONS
Yes
The innovations in micro-architecture facilitated by
semiconductor technology has improved the performance of
processors in many-folds, however, there has not been equal
performance improvements in memory. The floating-point
arithmetic capability of microprocessors have increased
significantly due to their high level integration and superscalar
architectural designs, but comparable increase in memory
speed has not been achieved. Consequently, to reduce memory
access time cache memories were used. In order to reduce
average bandwidth and memory latency, cache memories have
been used since a long time. Many memory intensive
commercial workloads can be effectively organized by limiting
the on-chip cache resources.
This paper presented some of the recent advances made in
cache memory to address latency, energy consumption and
improve access time of memory management unit. MAID
replacement algorithm [6] employs use of cache drives to
reduce the spin-up of data drives to conserves energy. It makes
cluster of networked servers to dynamically reconfigure or
shrink cache to operate it with a few nodes under light load.
Soft errors as discussed earlier pose a serious threat and various
schemes are proposed to prevent the integrity of information. A
fast soft error estimation approach was proposed by Ebrahimi
et al [17], called CLASS. It was developed in order to have the
capability to handle both regular and irregular structures. For
high-end embedded systems, the Chip multiprocessors (CMPs)
have emerged as a dominant architectural alternative. In Chip
multiprocessors, either all processors may share same L2 cache
or each processor may possess its own L2 private cache.
To use on-chip cache memories more efficiently with chip
microprocessors, many on-chip cache organizations have been
proposed. These include CMP-SNUCA [18], CMP-NuRAPID
[20], Victim Replication [19], and CMP-CC [21]. NUCA
technique is applied to CMPs architecture in CMP-SNUCA
scheme. In order to reduce wire delays, these on-chip cache
organizations migrate blocks close to the requestor. In another
similar technique [22], this is achieved by selectively writing
back L2 victims to a peer L2 cache. Recently proposed hybrid
caches address placement requirement of only a subset of data,
require complex lookups and coherence mechanisms to
increase latency and fail to scale to high core counts, however,
in comparison to conventional design they offer lower latency
[24].
To improve application performance on current
microprocessors, memory subsystem plays a vital role [23].
The flexibility and scalability of NUCA memory systems is
likely to benefit emerging chip multiprocessors (CMPs).
Hardavellas et al [24] found that most applications have few
distinct classes of accesses (instructions, private data, read
shared, and write shared data), and proposed Reactive NUCA
(R-NUCA), which specializes placement and replication
policies for each class of accesses on a per-page basis, and
significantly outperforms NUCA schemes without access
differentiation. RNUCA support intelligent migration,
placement and replication for the on-chip last level cache and
does not need any explicit coherence mechanism. For
scientific, server and multi-programmed workloads, the cache
performance is improved if designed using RNUCA. Sequoia
focuses on regular applications; however, support for irregular
computations on machines with multi-level memory
hierarchies through programming constructs and features such
as spawn and call-up has been designed by Bauer et al. [25].
Capacity of cache memory can be increased by
compression of data/instructions residing inside the cache,
thereby increasing its efficiency by reducing long off-chip
misses. However, it is likely that compressing cache would
increase the cache-hit time because of additional overhead
involved in decompressing data/instructions. Therefore, it may
improve or deteriorate the overall system. CacheRAID [26] is
an adaptive write cache policy that works on an energy-
efficient RAID storage architecture to balance the cost and the
performance. In comparison to RAID 0 and RAID 5, it
consumes only 30-40% power and is efficient to RAID 5 by
5%.
The hardware design of flash memory based SSD [16] have
revolutionized secondary storage systems because SSD is
much faster and its performance in random data access is
superb. The cache organization implemented to support the
basic main memory system can no longer be used to support
the modern SSD based main memory. Although the Smart
Response Technology (SRT) introduced by Intel for their Z68
chipset, which allows a SATA solid-state drive (SSD) to
function as cache for a (conventional, magnetic) hard disk
drive helped to access the data faster but a better cache
organization needs to be implemented on processors to
compensate for the slower speed of main memory.
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