HOMELAB PROJECT

Nostalgic LED Clock

74xx around the clock

By Michael Gaus
and Miguel Köhnlein (Germany)

In this project, an analogue wall clock (train station clock) is fitted with 60 LEDs that light up to simulate the
movement of a seconds hand around the clock face. To keep to the spirit of this project you should try hard
and resist the temptation to use a microcontroller; just rely on good-ol’ 74xx TTL logic to build a stand-alone
clock. For those with less willpower the circle of LEDs can be microcontroller or PC controlled, this allows you
to be a bit more creative with lighting sequences and special effects.

90 September & October 2018 www.elektormagazine.com

The clock can be configured for one of
two modes of operation using jumpers.
In mode 1 using only 74xx chips, all
the LEDs light up after switch on. At 1
second intervals one LED after another is
switched off, after a minute all LEDs are
off. In the following minute, the LEDs are
switched on again one after another at
intervals of one second, until all the LEDs
are lit up. This effect is achieved by using
an inverter in the shift register’s feed-
back path. For authenticity we’ve used
a 4060 binary counter chip to provide
the clock signal.
Mode 2 is a nod to modern times: all
60 LEDs can be controlled by an external
microcontroller or PC to generate any
desired lighting patterns. The chain of
74164 shift registers receives the CLK
and DATA signals from the external con-
troller via connector J1. Jumpers JP1 and
JP2 must link pins 2-3 and JP3 can be
left open in this mode.
Old friends, reunited
The 74 series of logic IC‘s aren’t used
much these days so let’s take a closer
look at the 74LS164 shift register we
will be using in this design. As a quick
reminder (or as an introduction to bud-
ding engineers) the chip was launched
back the early 1970s. Inside the IC (Fig-
ure 1) are eight flip-flops with common
clock and reset lines. The flip-flops are
cascaded: Each data input is connected
to the Q output of the previous flip-flop.
The inverted output signal of each flip-
flop connects to a pin to the outside.
Altogether, the user has eight data out-
puts QA through QH in parallel. The data
input of the first flip-flop is the serial data
input to the system. There are actually
two serial inputs A and B which drive a
NAND gate, these two inputs are con-
nected together in our circuit.
At each rising edge at the clock input
CLK, the logic state of each flip flop is
moved or shifted one position right to the
next flip flop in the chain towards QH.
At the same time, the state of the input
signal is loaded into the first flip-flop with
its output at QA. The shift register truth
table in Figure 1 also shows when a logic
low level is put on the CLEAR input all
the flip flops are cleared and their out-
puts go low.
The internal circuitry of the 74LS164
suggests you can cascade multiple shift
register ICs to give more than one eight-
bit wide output. All that’s necessary is
to connect the last output QH to the A
Figure 1. The 74LS164 block diagram and truth table. Courtesy Texas Instruments TTL data book
circa 1974.
/ B input of the next 74LS164. The CLK
and CLEAR  inputs are then connected
together and used synchronously.
As the circuit diagram in Figure 2 shows
we have used a total of eight 74LS164s
in series for the LED clock. This effecti-
vely builds one large shift register with a
64-bit wide output. Eight LEDs are con-
nected to each 74LS164 except for the
last shift register, which only drives four
LEDs. Each LED is connected to +5 V via
a 1-kΩ series resistor so that they light
up when the corresponding flip flop out-
put goes low. The shift register is driven
by a 1-Hz clock signal generated by the
counter chip.
A Binary counter generates the
clock
Let‘s first look at the clock working in
stand-alone „normal mode“ or mode 1.
All three jumper positions link pins 1 and
2. A reset network, consisting of R65 and
C6, provides a reset pulse at switch on to
ensure all the shift registers are cleared.
Pushbutton S1 provides a manual reset.
In this initial state, all the shift register
outputs are low (i.e. all LEDs are lit). The
last output for LED 60 is fed back to the
input of the first 74LS164 via the 7404
inverter (IC9A) and jumper position JP1.
The A / B input of IC1 is therefore at a
logic high. At the next rising clock edge,
this high level is shifted to the output QA,
so that the LED goes out. This logic level
is now at the input to the next flip flop,
which will change state when the next
clock edge arrives. The change of state
propagates along the shift register with
www.elektormagazine.com
each clock pulse. At the 60th clock edge,
even though the output of LED60 goes
high and the last LED goes off, the level
at the A / B input of IC1 now becomes
low, so that for the next 60 seconds the
low level is sent down the shift register
chain to switch on each LED in turn.
Clock pulses are generated by the
14-st age binar y counter IC10 (a
74HC4060). Although this chip performs
a completely different function, inter-
nally (Figure 3) it’s also made up of
flip flops like the shift register chip. The
74HC4060 uses a chain of toggle-type
flip-flops, these have their data input
connected to the flip flop output /Q .
Each flip-flop changes state at every
falling edge of the CLK input the output
signal is therefore a waveform half the
frequency of the CLK signal. Each flip
flop in the chain provides this divide-by-
two function so that at the 14th flip-flop
a signal with the frequency of 1/214 of
the clock signal appears.
The 74HC4060 binary counter has fea-
tured in many digital clock schematics
over the years where it is used to pro-
vide the 1 second reference timebase.
It just needs a 32,768 Hz clock crystal
connected at its clock input so that at
Q13 a frequency of ... no, alas not 1 Hz,
but 32768/214 = 2 Hz is output. The sig-
nal needs to be further divided by 2 to
give a 1 Hz signal, a 7474 D-type flip-
flop (IC11A) does this job. It has its Q
output connected to its D input to form a
toggle flip flop. Via jumper JP2 the resul-
ting 1-Hz signal is fed to the shift register
clock inputs.
September & October 2018 91
Modern times generate the clock signal and remem- as High, levels below 0.8 V as Low.
Maybe you’re getting a bit tired of all ber that the DATA signal level must be The supply voltage is generated by a
this nostalgia, you can of course opt for set and stable before the positive edge 7805 linear regulator. The input voltage
mode 2 and control the LED clock using of the CLK signal is supplied. The video VIN must be at least 8 V for this regu-
a real state-of-the-art microcontroller (or [2] shows some possible lighting and dis- lator, but don’t go much higher than
PC). First disconnect the clock signal by play effects, which can be achieved using 15 V otherwise power dissipation in the
removing the two links between pins 1 external control. regulator becomes excessive. It may be
and 2 on both JP1 and JP2 and placing necessary to fit a small heatsink to IC12
them between pins 2 and 3. This discon- Power and assembly if this is the case.
nects the on-board clock generator and The 74LS family of ICs is quite deman- The clock face has 60 holes drilled at the
also the feedback path to the first shift ding when it comes to supply voltage and seconds positions. Make sure the drill size
register. You can also (but don’t need signal levels. The power supply should is the same at the LED body diameter so
to) remove jumper JP3 if you want the be in the range 4.75 to 5.25 V. Under that the collar at the base of the plastic
circuit to be reset by a signal from the no circumstances may the signal level lens stops the LED from falling through.
microcontroller. exceed the supply voltage! This must They can then be fixed in position using
In mode 2, all 60 LEDs are externally be taken into account especially when two-part adhesive (Figure 4). Each LED
controlled. The signals CLK and DATA external control signals, for example from cathode is connected to a shift register
(and optionally also CLEAR) are sup- a PC are interfaced, this is also relevant output using enamelled copper wire. The
plied to the shift register via connec- when interfacing microcontrollers that series resistors are soldered directly to
tor J1. When you write the program for are not operated at 5 V. Signal levels each LED anode and to the inner ring
the controller, set a timer interrupt to above 2 V are detected by the LS logic of copper wire connected to +5 V. The

+5V
R49
R50
R51
R52
R53
R54
R55
R56

R57
R58
R59
R60
R10
R11
R12
R13
R14
R15
R16
R1
R2
R3
R4
R5
R6
R7
R8

R9

R17...R48 = 1k
1k
1k
1k
1k
1k
1k
1k
1k

1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k

1k
1k
1k
1k
1k
1k
1k
1k

LED49
LED50
LED51
LED52
LED53
LED54
LED55
LED56

LED57
LED58
LED59
LED60
LED10
LED11
LED12
LED13
LED14
LED15
LED16
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8

LED9

LED17...LED48

All LEDS low-current

3 4 5 6 10 11 12 13 3 4 5 6 10 11 12 13 3 4 5 6 10 11 12 13 3 4 5 6 10 11 12 13
QG

QG

QG

QG
QA
QB
QC
QD

QH

QA
QB
QC
QD

QH

QA
QB
QC
QD

QH

QA
QB
QC
QD

QH
QE

QE

QE

QE
QF

QF

QF

QF
+5V
IC1 IC2 IC7 IC8
74LS164 74LS164 74LS164 74LS164
R65
CLK
CLR

CLK
CLR

CLK
CLR

CLK
CLR
A
B

A
B

A
B

A
B
10k

1 2 8 9 1 2 8 9 1 2 8 9 1 2 8 9

JP3 IC3...IC6 = 74LS164

2
1

IC9.A
C6 JP1
1 2 1
1
100n 2
3 74LS04 +5V
IC12
D1 7805 +5V +5V 14 C7 14 C14
IC2...IC7
C17 IC1 IC8
1N4004 100n
C8...C13
100n
7 7
C5 C3 C4 100n

470u 16
100n 100n C1 +5V
7 VDD 11
Q3 PI
5
Q4 10p
4 R61 14 C15
Q5 IC10 X1
J1 JP2 +5V 6 IC9
Q6
15M

VIN
1 1 100n
14 3 5 7 9 11 13
2 2 Q7 32.768kHz
DATA 13 9
3 3 4 1 Q8 PO R62 C2
CLK 15 10
4 PRE CLR Q9 PO 330k +5V
CLEAR 5 2 1
5 Q D Q11 10p
N.C.
IC11.A 2 74HC4060
6 R64 R63 Q12
GND S1 6 3 3 12 14 10 11 12 13 C16
Q CLK Q13 RST
IC11
10k

10k

GND
8 7 100n
RESET 74LS74

160625 - 11

Figure 2. The 74xx TTL clock circuit diagram.

92 September & October 2018 www.elektormagazine.com

 shift register ICs are mounted on small
squares of perf board and distributed
around the clock perimeter, this helps
reduce wire lengths to the LEDs. Only
wires carrying the DATA and CLK sig-
nal need to run all the way ‘around the
clock’.
(160625 || 180419)

Figure. 3. Internal block diagram of the 74HC4060 binary counter (from a recent Philips
Semiconductors datasheet).

@ www.elektor.com
Web Links ªNew Precise Nixie Clock
Project in Elektor 5/2016:
[1] Video 1: www.youtube.com/watch?v=LTaV84mTj2w
www.elektormagazine.com/150189
[2] Video 2: www.youtube.com/watch?v=UEWgwRypzHk

Figure. 4. Wiring the 60 LEDs to the shift registers.

www.elektormagazine.com September & October 2018 93