This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Bidirectional Three-Phase DC-AC Converter
with Embedded DC-DC Converter and
Carrier-Based PWM Strategy for Wide
Voltage Range Applications
Jiangfeng Wang, Student Member, IEEE, Hongfei Wu, Senior Member, IEEE,
Tianyu Yang, Li Zhang, Member, IEEE and Yan Xing, Member, IEEE

Abstract—A bidirectional three-phase DC-AC converter
with embedded DC-DC converter for bidirectional storage
interface is proposed in this paper. With the help of the
embedded DC-DC converter, the voltage of storage battery
can vary in a wide range. To minimize the power rating and
power losses of the embedded DC-DC converter, a simple
carrier-based PWM strategy with zero-sequence injection
is proposed. By adopting the proposed PWM strategy, only
a small ratio of total power needs to be processed by the
embedded DC-DC converter while most of the power is
only processed by the three-phase DC-AC stage within
single conversion stage. As a result, quasi single-stage
power conversion is achieved to improve the conversion
efficiency of the overall DC-AC power system. Principles,
characteristics and implementations of the proposed
three-phase DC-AC converter and its PWM strategy are
analyzed in detail. The feasibility and effectiveness of the
proposed solutions are verified with experimental results.
Index Terms—Bidirectional DC-AC
embedded DC-DC converter, quasi
conversion, pulse width modulation.
I. INTRODUCTION
B idirectional three-phase DC-AC converters play a key role
in applications such as uninterrupted power supplies,
electric vehicles, grid integrations of renewable energy sources,
energy storage systems, and micro-grids [1]. Regarding the
power flow from DC to AC, topologies of three-phase
converters can be classified into three categories: Buck-type
(voltage-fed) [2], Boost-type (current-fed) [3] and
Buck-Boost-type [4] topologies. Among them, the Buck-type

Manuscript received January 24, 2018; revised April 25, 2018 and
June 15 2018; accepted August 2, 2018. This work was supported by
the National Natural Science Foundation of China under Grant
51677085, the Fok Ying-Tong Education Foundation, China, the
Fundamental Research Funds for the Central Universities (No.
NE2018102), Six talent peaks project in Jiangsu Province
(2016-XNYQC-008) and Qing Lan Project.
J. Wang, H. Wu, T. Yang and Y. Xing are with the Center for
More-Electric-Aircraft Power System, College of Automation
Engineering, Nanjing University of Aeronautics and Astronautics,
Nanjing 211106, China.
L. Zhang is with the college of Energy and Electrical Engineering and
the Research Center for Renewable Energy Generation Engineering of
Ministry of Education, Hohai University, Nanjing 211100, China.
(corresponding author: Hongfei Wu, e-mail: wuhongfei@nuaa.edu.cn).
0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Transactions on Industrial Electronics
Battery Cascaded DC-DC DC-AC AC Grid
vA
vB
VL VH
vC
(a)
Embedded DC-DC DP-TPC
Battery
vA
AC Grid
VH
vB
VL vC
(b)
Fig. 1. Bidirectional three-phase converters: (a) traditional two-stage
architecture with cascaded DC-DC converter, (b) proposed quasi
single-stage architecture with embedded DC-DC converter.
converters have been the most popular solution for industrial
applications due to their simple topology, high efficiency,
flexible modulation and control strategy. However, according
conversion, to the voltage relationship between the input and output voltage
single-stage of the Buck-type converters, the DC input voltage must be
greater than the peak amplitude of AC line voltage. In practical
applications, e.g., battery charging/discharging for electric
vehicles and energy storage systems, the DC voltage of storage
battery can be either lower or greater than the peak amplitude of
AC line voltage [5][6]. In order to adapt to the wide DC voltage
range, another bidirectional DC-DC converter is required to be
cascaded with the DC-AC converter, as illustrated in Fig. 1(a)
[7]. However, for this two-stage architecture with cascaded
DC-DC converter, all the power has to be processed twice,
which significantly degrades the overall efficiency.
Many efforts have been made to improve the efficiency of
two-stage bidirectional DC-AC power conversion systems.
Multilevel DC-AC topologies are effective to reduce the
voltage stresses and switching losses of active switches [8], but
the conversion stages cannot be reduced yet. Bidirectional
Z-source and qZ-source DC-AC converters are attractive
solutions because single-stage power conversion can be
achieved [9][10]. However, these topologies suffer from higher
voltage/current stresses, more power losses of switching
devices and complicated control, which makes them difficult to
achieve high efficiency. Quasi single-stage architecture with
embedded DC-DC converter is another attractive solution for
high efficiency DC-AC power conversion. The effectiveness of
quasi single-stage architecture applied to single-phase power
conversion systems has been verified by the authors in [11],
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

DC-DC
DP-TPC
which drops a hint that similar principles can also be applied to Converter iH

three-phase power systems. As shown in Fig. 1(b), the S1 S Ha S Hb S Hc

proposed quasi single-stage bidirectional three-phase DC-AC VH
C2 S La 2 S La1 vA
L1 ia La
converter consists of an embedded DC-DC converter and a S2 a
dual-DC-port three-phase DC-AC converter (DP-TPC). It iL
S Lb 2 S Lb1
ib Lb
vB
o
should be noted that, the performance and characteristics of b
S Lc 2 S Lc1 vC
quasi single-stage bidirectional three-phase DC-AC converter VL ic Lc
c
are highly dependent on the modulation strategy of the DP-TPC, C1 S Za S Zb S Zc
which is much more complicated than that a single-phase
DC-AC power system. n
Various modulation schemes have been developed for Fig. 2. Bidirectional three-phase DC-AC converter with embedded
bidirectional three-phase DC-AC converters. Generally, they DC-DC converter.
can be mainly classified into space-vector (SV) pulse-width Emedded DC-DC DP-TPC
Battery AC Grid
modulation (PWM) and carrier-based (CB) PWM strategies.
SV-PWM strategies are widely used due to their flexible PH
control capability, but suffer from the main drawback of PL
computational complexity due to the requirement of several
steps: the selection of three nearest vectors, the vector (a)
dwell-time calculation, and the duty cycle calculation for each Battery
Embedded DC-DC DP-TPC
AC Grid
switch [12][13]. As an alternative, by injecting a proper PH
zero-sequence voltage to modulation signals, CB-PWM
strategies are capable of producing same results, e.g., in terms
PL
of dc bus utilization, as space-vector-based approaches [14][15].
In comparison with the SV-PWM scheme, the CB-PWM (b)
method requires less computation resources and results in Fig. 3. Power flow diagram of the bidirectional three-phase DC-AC
converter with embedded DC-DC converter: (a) inverter mode, (b)
simple implementation, because it directly generates the duty rectifier mode.
cycles for the switches by comparing modulation signals with
conversion. It is seen that dual DC ports, i.e., a low-voltage (LV)
carrier waveforms [16]. Numerous significant works have been
DC port and a high-voltage (HV) DC port, are provided
done on the CB-PWM strategies, among which the simultaneously by the DP-TPC. The LV DC port is directly
zero-sequence components are changed to satisfy various connected to the battery, while the HV one is connected to the
control aims, e.g., to realize voltage balance for a three-level intermediate bus. It is obvious that a new power flow branch
converter [17][18] or to reduce power losses for high efficiency between the battery and the AC grid is built by the DP-TPC, by
applications [19][20]. However, all these CB-PWM strategies means of introducing a bidirectional switch, i.e., two
are designed for traditional three-phase DC-AC converters with series-connected IGBTs SLx1 and SLx2 (x=a,b,c), to each
only one DC port and none of them can be directly applied to a switching-leg. Hence, part of the power can be directly supplied
DP-TPC. For the DP-TPC, the main challenges are as follows: from the battery to the AC grid without processed by the
1) a variable voltage level VL is introduced by the new embedded DC-DC converter, and vice versa.
low-voltage (LV) DC port, rather than constant and The power flow diagram of the bidirectional DC-AC
symmetrical voltage levels in traditional three-phase DC-AC converter with embedded DC-DC converter is illustrated in
converters; 2) the modulation target of the DP-TPC is to Fig.3. As shown in Fig. 3(a), when the power flows from the
minimize the power processed by the embedded DC-DC battery to the AC grid, it is defined as inverter mode, while the
converter, which is totally different from that of a traditional reverse power flow from the AC grid to the battery, as shown in
three-phase DC-AC converter. Fig. 3(b), is defined as rectifier mode. Taking the inverter mode
The major contribution of this paper is to propose a novel as an example, it is seen that part of the input power from the
bidirectional three-phase DC-AC converter with embedded battery, i.e., PL, can be directly fed to the AC grid only through
the DP-TPC within single power conversion stage, while the
DC-DC converter. To minimize the power rating and power
other part of the input power, PH, is transferred to the AC grid
losses of the embedded DC-DC converter, a simple CB-PWM
through both the embedded DC-DC converter and the DP-TPC
strategy with zero-sequence injection is proposed. With the
by two conversion stages. Since only partial power is processed
help of the proposed CB-PWM strategy, the power losses of the by the embedded DC-DC converter, the power rating and
DP-TPC can also be reduced. Hence, the conversion efficiency power losses of the DC-DC converter are reduced. For the
of the overall DC-AC power system is improved. DP-TPC, there are three cases for the switching state of each
phase, in terms of which the midpoint voltage of each
II. BIDIRECTIONAL THREE-PHASE DC-AC CONVERTER switching-leg can be described as follows:
WITH EMBEDDED DC-DC CONVERTER
VH ( S Hx , S Lx1 , S Lx 2 , S Zx )  (1,1, 0, 0)
The bidirectional three-phase DC-AC converter with 
vxn  VL ( S Hx , S Lx1 , S Lx 2 , SZx )  (0,1,1, 0) (1)
embedded DC-DC converter is shown in Fig. 2, where a 0
DP-TPC is employed and responsible for bidirectional DC-AC  ( S Hx , S Lx1 , S Lx 2 , SZx )  (0, 0,1,1)

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

LV and HV ports of the DP-TPC. Therefore, an outer voltage

iH iH
VH VH loop of VL determines the active current reference id* and
S Ha S Ha
regulates the total active power flowing into the battery. For the
S La 2 S La1 S La 2 S La1 La ia
La ia embedded DC-DC converter, a sign function Sgn is introduced
iL a iL a to the control loop to determine the power flow directions. It is
vA vA
VL S Za o VL S Za o seen that the control of the bidirectional DC-AC converter with
von von embedded DC-DC converter is similar to that of the traditional
n n solution with cascaded DC-DC converter. However, the
(a) (b) modulation strategy of the DP-TPC, which is the key to
iH
determine the power flow of the bidirectional DC-AC converter
VH S Ha
with embedded DC-DC converter, is totally different from the
S La 2 S La1
modulation strategy applied to a traditional three-phase DC-AC
La ia
converter. The carrier-based PWM (CB-PWM) strategy for the
iL a
vA DP-TPC is the main focus of this paper due to its simplicity for
VL S Za o practical implementation, and will be analyzed in detail in the
von
next section.
n
(c) III. PROPOSED CARRIER-BASED PWM STRATEGY
Fig. 4. Equivalent circuits of phase A related to each switching state: (a)
(SHa,SLa1,SLa2,SZa)=(1,1,0,0), (b) (SHa,SLa1,SLa2,SZa)=(0,1,1,0), (c) As shown in Fig. 2, the topology of DP-TPC is similar to the
(SHa,SLa1,SLa2,SZa)=(0,0,1,1). traditional T-type three-level converter. However, unlike the
Embedded DC-DC DP-TPC traditional three-level converter, the voltage VL in the DP-TPC
AC Grid is determined by the voltage of the battery and not always
equals to one half of VH. Meanwhile, the modulation target of
VL load
iabc v ABC the DP-TPC is to minimize the power processed by the
PWM embedded DC-DC converter PH, i.e., to maximize the power
abc abc
VH Proposed
Sgn
- CB-PWM dq dq directly fed to the AC grid PL (note that the inverter mode is
PI
+ vabc i
-d
iq taken as an example in this section to derive the proposed
VH*
1
 abc PI
+
PLL CB-PWM strategy), instead of realizing voltage balance of
if id* >0 inverter mode
Sgn=  dq
PI
-  neutral point in a traditional three-level converter.
1 if id  0 rectifier mode
*

VL + id* + iq*
- PI A. Asymmetrical Carrier Waveforms
VL*
When the conventional CB-PWM strategy is applied to a
Fig. 5. Control block diagram of the bidirectional three-phase DC-AC
converter with embedded DC-DC converter.
traditional three-level DC-AC converter, due to voltage balance
of the dividing capacitors, two carriers are displaced
where x=a, b, c, for phase A, phase B and phase C respectively. symmetrically with respect to the zero-axis, which results in the
Taking phase A in the inverter mode as an example, the same peak to peak value of the carriers. However, this is not
equivalent circuits related to each switching state are illustrated always valid for the DP-TPC because the voltage of LV port VL
in Fig. 4, and the corresponding current path is marked with the is not constant. When the CB-PWM strategy is applied to the
red line. As shown in Fig. 4(a), when SHa and SLa1 turn on, the DP-TPC, the peak to peak values of carriers should be varied
current supplied from the HV port, iH, flows into the AC grid, according to the voltages of VL and VH. As shown in Fig. 6, the
which means part of input power, PH, can be fed to the grid after amplitudes of two carriers are in proportion to the DC voltage
processed by the DC-DC converter. On the other hand, when (VH-VL) and VL, respectively, and can be normalized by
V  VL 2 VH  VL 
SLa1 and SLa2 turn on, the current iL is directly transferred from
the LV port to the AC grid without processed by the DC-DC VPeak _ Top  H  (2)
converter, as shown in Fig. 4(b). When SLa2 and SZa turn on, VH 2 VH
both iH and iL would not fed to the grid through phase A, as VL 2V
shown in Fig. 4(c). The current path of other two phases is the VPeak _ Bottom   L (3)
same as that of Phase A, and for the rectifier mode, it just has a
VH 2 VH
reversed current path and can be studied in a similar manner. 2 VL VH  1  0 2 VL VH  1  0
The control block diagram of the bidirectional DC-AC va vb vc va vb vc
1 1
converter with embedded DC-DC converter is illustrated in
Fig.5. The voltage VH is regulated by the embedded DC-DC
converter, while the voltage VL is regulated by the DP-TPC. It is
0 0
worth to mention that, either the battery voltage or the battery
current can be regulated by the current id, thus, the current
reference id* can be generated by the battery control loop. For
-1 -1
the DP-TPC in rectifier mode, the battery is directly connected 0  2 0  2
to the LV port and the power from the HV port is also fed to the
(a) (b)
LV port through the embedded DC-DC converter. That means Fig. 6. Three-phase modulation signals and two carrier waveforms for
the power on the LV port represents the total power of both the the DP-TPC: (a) case I: VL<VH/2, (b) case II: VL≥VH/2.

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

According to (2) and (3), the value of the boundary line of vx vtop vtop
carrier waveforms shown in Fig. 6 can be derived as (2VL/VH-1). 1 1
With different locations of the boundary line, there are two 2 VL VH  1 2 VL VH  1
cases for the DP-TPC. When VL<VH/2, the boundary line lies vbottom vx vbottom
below zero-axis, and the amplitude of the top carrier waveform
is larger than that of the bottom one, as shown in Fig. 6(a). -1
When VL≥VH/2, the situation is contrary to the former one, as 1 1
shown in Fig. 6(b). It is worth to mention that, when VL=VH/2, 0 0
the boundary line locates on zero-axis, and the amplitude of two (a) (b)
carrier waveforms is equal to each other, which means that the Fig. 7. Switching state function Sx: (a) case I: vx≥2VL/VH-1, (b) case II:
carrier waveforms of the traditional three-level converter is vx<2VL/VH-1.
only a special case of the DP-TPC. Due to space constraints, three-level converter. For a three-level converter, a
only detailed analysis of case II (i.e., VL≥VH/2) will be given zero-sequence signal is always added to the sinusoidal
here and for the other case it can be studied in a similar manner. modulation signal vx to adjust the duty cycle of switches and
further achieve the voltage-balancing task. Inspired by this idea,
B. Modified Modulation Signals with Zero-Sequence to maximize the power PL for the DP-TPC, the key point is to
Injection explore the proper zero-sequence voltage, v0.
Assume that the original three-phase modulation signals are It is necessary to further analyze (6) to carry out the proper
sinusoidal, it can be written as zero-sequence injection. After adding the zero-sequence
va  m cos  component v0, (6) is replaced by
  1  vx  v0
vb  m cos   2 3 (4) if vx  v0  2VL VH  1
v  m cos   2 3  2  2V V

 c 
dx   L H
(8)
where m is the modulation index, θ is the phase angle.  1  vx  v0 if v  v  2V V  1
As mentioned above, the modulation target of the DP-TPC is 
 2VL VH
x 0 L H

to maximize the power PL, which is directly transferred from Noting that the physical meaning of d x is the duty cycle when
the LV port to the AC grid within single power conversion the phase leg is connected to the LV port, which, absolutely, is
stage. To analyze the power flow of the DP-TPC, the foremost nonnegative. Hence, the span of the zero-sequence component
step is to deduce the averaged current flowing out of the LV that can be injected is expressed as
port of the DP-TPC, which is defined as iL as shown in Fig. 2. 1  vmin  vo  1  vmax (9)
The averaged current is determined by both the switching
pattern and the phase current. Generally, one-phase current where
contributes to the LV port if and only if this phase is connected vmin  min(va , vb , vc ) vmax  max(va , vb , vc ) (10)
to the LV port, as shown in Fig. 4(b). Assumed that the are defined as the minimum and maximum value of the original
frequency of the carrier waveforms is much higher than the sinusoidal-modulation signals, respectively.
frequency of modulation signals, the phase current can be In order to maximize the active power PL, which is directly
considered as a fixed value in a switching cycle. Then iL can be fed to the AC grid with only single-stage power conversion, it is
expressed as necessary to increase the average value of iL. A straightforward
iL   d x  ix (5) method is to block the negative phase current flowing into the
x  a ,b, c LV port, that is to say, to make the duty cycle d x to be zero
where dx (x=a,b,c) is the duty cycle when the phase leg is when the phase current ix<0. The three-phase currents of the
connected to the LV port, and d x  [0,1] , ix is the DP-TPC can be given by
corresponding phase current. ia  I m cos    

ib  I m cos   2 3   
In one switching period, either the top carrier waveform or (11)
the bottom one intersects with the modulation signal, as shown i  I cos   2 3   
in Fig. 7. The darkened regions in Fig. 7 represent the duration c m

in which the phase leg is connected to the LV port. With the where Im is amplitude of phase current, φ is power factor angle.
graphical method, the duty cycle dx can be derived as For convenience of analysis, the unity power factor case,
 1  vx where the power factor angle φ=0, is firstly taken into account
 2  2V V if vx  2VL VH  1 and the influence of power factor will be discussed afterwards.

dx   L H
(6) According to the polarity of the phase current, the analysis is
 1  vx if vx  2VL VH  1 performed in six sections (i.e., S1-S6) shown in Fig. 8.

 2VL VH In section S1, where π/6≤θ≤π/2, the followed relationship is
in which vx (x=a, b, c) is the modulation signal of each phase. satisfied, i.e., ia≥0, ib≥0, ic<0. In this case, the phase current ia
Particularly, when VL=VH/2, (6) can be simplified by and ib flow out of the VL port, while the phase current ic flows
into the VL port. To block the negative current ic, the most ideal
d x  1  vx (7)
zero-sequence component is to make d c to be zero. Thus, the
Equation (7) shows the same expression as the duty cycle when injected zero-sequence component can be easily derived as
the phase current flows out of the neutral point in the traditional

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

The modified modulation signals with zero-sequence

ia ib
Im
0 modulation signals, the modified modulation signals will be
Im
S6/2 S1 S2/1 S2/2 S3 S4/1S4/2 S5 S6/1
0 6  2 5 6 7 6 3 2 11 6 2
Fig. 8. Division of analysis period.
(-1-vc). With the zero-sequence injection, the negative current
in section S1 can be blocked completely.
In section S2, where π/2<θ≤5π/6, the relationship meets ia≤0,
ib>0, ic≤0. To block the negative current ia and ic, the most
appropriate zero-sequence component is to make both d a and
d c to be zero, which, however, cannot be realized
simultaneously. According to the relationship of the
three-phase sinusoidal-modulation signals, section S2 can be
further divided into two subsections, i.e., S2/1 and S2/2. In
subsection S2/1, where π/2<θ≤2π/3, it is easily obtained from
(4) that vc≤va<vb, hence, vmin=vc. To make d a  0 , the
zero-sequence component v0 should be (-1-va), which,
obviously, exceeds the span given in (9). Alternatively, to make
dc  0 , the zero-sequence component v0 is (-1-vc) and satisfied
with (9). Thus, the injected zero-sequence component v0 in
subsection S2/1 is derived as (-1-vc). Substituting v0=(-1-vc)
into (8), it is derived that da  da , which indicates that, even
though the duty cycle d a cannot be clamped to zero to
completely block the negative current ia, it has also been
reduced effectively. Similarly, in subsection S2/2, where
π/3<θ≤2π/3, it can be obtained that va≤vc<vb, hence, vmin=va.
The injected zero-sequence component v0 is derived as (-1-va)
to make d a  0 , and meanwhile the duty cycle d c can also be
reduced effectively to mitigate the influence of the negative
current ic. The analysis process for other sections is the same as
that in section S1 or section S2. In conclusion, the results of the
zero-sequence component in all six sections are listed in Table I.
ic
injection vx ( vx  vx +v0 ) are illustrated in Fig. 9. It is seen that,
when the zero-sequence signal is added to the sinusoidal
clamped at minus one during 120°interval of a fundamental
cycle. That is to say, the corresponding phase does not switch
during these intervals and the negative current flowing into the
VL port will be cut-off. For instance, during the interval of
0≤θ≤2π/3, the modulation signal vc is clamped at minus one,
hence, phase C does not switch and the negative phase current ic
is prevented from flowing into the LV port. Therefore, the
injected zero-sequence signal can assist to increase the average
value of iL and accordingly increase the power PL for the
DP-TPC. On the other hand, since the switches SLx1 and SZx of
each phase are not in action during 120° interval of a
fundamental cycle, the average switching frequency of these
switches can be reduced by 33%, which indicates that much
lower power losses of the switches can be achieved by the
DP-TPC. This would be another advantage of the proposed
CB-PWM strategy.
The block diagram of the proposed CB-PWM strategy for
the DP-TPC is illustrated in Fig. 10, where the two key parts,
i.e., the asymmetrical carrier waveforms and the modified
modulation signals, are highlighted. The inputs are the original
va vb vc
1
0
-1
0 2 / 3 4 / 3 2
Fig. 9. The modified modulation signals with zero-sequence injection.
1 1
Modified
0 0 modulation
1
signals
1

According to Table I, the uniform expression of the va va Sta

zero-sequence component v0 can be derived as
v0  vmin  1 (12) vb Stb
vb
TABLE I
ZERO-SEQUENCE SIGNALS IN EACH SECTION vc vc Stc
Section Polarity of phase current Zero-sequence signals
Zero-sequence v0 1
Asymmetrical
S1 ia≥0, ib≥0, ic<0 v0=-vc-1 Generator 0 0 carrier
waveforms
S2/1 v0=-vc-1 1

ia≤0, ib>0, ic≤0 Fig. 10. Block diagram of the proposed CB-PWM strategy with
S2/2 v0=-va-1
zero-sequence injection.
S3 ia<0, ib≥0, ic≥0 v0=-va-1 vx1
Eq. (13)
S4/1 v0=-va-1 S Hx
vx
ia≤0, ib≤0, ic>0 1
S Lx 2
0
S4/2 v0=-vb-1 vx 2
Eq. (14)
S5 ia≥0, ib<0, ic≥0 v0=-vb-1 S Lx1
1

0
S Zx
S6/1 v0=-vb-1
ia>0, ib≤0, ic≤0
S6/2 v0=-vc-1 Fig. 11. Block diagram of the proposed CB-PWM strategy with the
invariable carrier.

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

three-phase sinusoidal-modulation signals, which are modified modulation signals and the phase current during each 2π/3
by adding the zero-sequence component determined by (12), interval, (15) can be replaced by
generating the proposed modulation signals. Then these signals 3 23
2 0
are compared with the asymmetrical carrier waveforms to PL  VL  (d aia  dbib  dcic )d (16)
generate the switch gating signals.
In practical implementation with digital controllers, such as During the interval of 0≤θ≤2π/3, the zero-sequence
DSP, the asymmetric carrier is not easy to be implemented with component is (-vc-1), hence, the modified modulation signals
the ePWM module. As an alternative, the carrier can be kept can be derived as
invariable while the modulation signals are equivalently va  va  v0  3m cos    6   1
modified to ensure the same switching signals for each switch. 

vb  vb  v0  3m sin   1 (17)
When the modulation signal vx intersects with the top carrier, v  v  v  1
SHx and SLx2 operate in high frequency. To ensure the same duty 
 c c 0

cycle of these two switches with the carrier kept invariable Substituting (8), (11), (17) into (16), the single-stage power
from 0 to 1, the modulation signal is modified as supplied by the LV port is expressed as (18), shown at the
v  1  2VL VH bottom of this page, where l=VL/VH, 1  arccos(2l
vx1  x (13) 3m) ,
2  2VL VH
2  arcsin(2l 3m) , respectively. The span of l and the
Similarly, when the modulation signal vx intersects with the
modulation index m is 0<l≤1 and 0  m  2 3 .
bottom carrier, SLx1 and SZx operate in high frequency. To ensure
the same duty cycle of these two switches, the modulation Neglecting the power losses of the converter, the total active
signal is modified as power is given by
v  1 I
Po  3  VAC  m cos  (19)
vx 2  x (14) 2
2VL VH
where VAC is the RMS value of AC line voltage, equal to 380V.
The block diagram of the proposed CB-PWM strategy with
The single-stage power supplied by the LV port PL is
the invariable carrier is given in Fig. 11. It is seen that dual
normalized by the total active power Po, which is expressed as
modulation signals, vx1 and vx 2 , intersect with the invariable PLN=PL/Po. Based on (18) and (19), the curve of the normalized
carrier and then generates the gating signals for each switch. It single-stage power PLN is drawn in Fig. 12, where it is plotted
is obvious that the procedure to implement the proposed with the condition φ=0 and m=0.88 (the modulation index is
CB-PWM strategy is very simple, which implies that it is an derived with the condition VH=700V). In Fig. 12, VACPK is the
effective method suitable for practical applications. 1.01

IV. CHARACTERISTICS AND ANALYSIS 0.8

A. Active Power Transfer Characteristics 0.6

PLN 0.5
With the proposed CB-PWM strategy for the DP-TPC, part
0.4
of the input power from the battery (i.e., the LV port) can be
directly fed to the AC grid. The single-stage power supplied by 0.2
the LV port can be expressed as
1 2 1 2 00
PL  VL 
2 0
iL ( )d  VL 
2 
0
(d aia  dbib  dcic )d (15) 0
0
17
100 200
37
VL VH400
300
5 7 VACPK VH 1
500 600 700

Considering the symmetrical characteristics of the modified Fig. 12. Curve of the normalized single-stage power PLN.
2
3
PL  VL 
2 
0
3
(d aia  d bib ) d 

        
  1 +  2  3m cos(  6 )  2
 3m cos(  6 )  
  0 6 cos(   )   d   3  cos(   )   d 
 3I m   2  2l   2l   3m
 
1
6
       if 0  l 
 2   4
   2  3m sin   2
2  2  3m sin   
 0 cos(  3   )   d   3 cos(    )   d 
2

 2l 3 2  2l
    2
  
            (18)
   1  3m cos(  6 )  
1  2  3m cos(  6 )  2
 3m cos(  6 )  
  0 cos(   ) 
6
 d    cos(   ) 
6
 d    cos(   ) 
3
 d 
 3I  2  2l
      
2l 1 1 2l 3m 3m
 m 
6 6
if l 
 2       4 2
 
  2 2  3m sin    - 2 2  2  3m sin   2
2  3 m sin   
  0
         2          -2       
3
cos( )   d cos( )   d cos( )   d 
  3  2l  3  2  2l  3  2l  


 3m
1 if <l  1
 2

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

peak value of AC line voltage, which is equal to 380 2 V, VH
is the HV port voltage and keeps as a constant value, 700V. As
shown in Fig. 12, it is found that PLN increases with the voltage
VL, which means a higher VL is better for reducing the power
processed by the embedded DC-DC converter. In particular, if
VL is higher than the peak value of AC line voltage, VACPK, all
the power can be directly supplied by the LV port without using
the embedded DC-DC converter.
B. Influence of Power Factor
As stated earlier, the derivation of the proposed CB-PWM
scheme is carried out under unity power factor condition.
However, for some practical applications, the influence of the
power factor must be taken into consideration. In this case, the
active power transfer characteristics of the DP-TPC should be
re-verified, with taking account of the power factor angle φ.
When considering the influence of power factor, the apparent
power of the DP-TPC should keep as a constant value, which
stands for the power capacity of the converter. Therefore, the
total active power varies with the power factor angle φ, as
expressed in (19). Referring to (19), the power factor angle φ
cannot reach to -π/2 or π/2, because the total active power
would be equal to zero and there is no physical meaning for PLN.
Taking the range of φ∈[-π/3, π/3] as an example, the curve of
PLN in terms of the variable VL and φ is drawn in Fig. 13. It is
a T-type three-level converter [21], is also constructed and
tested based on the schematic shown in Fig. 15. The parameters
of these two solutions are both listed in Table II, based on
which the voltage and current stresses (including turn on/off
current, average and RMS current at full load) in each
semiconductor are given in Table III. It is worth to mention that
the voltage stresses of SLx1 and SLx2 in the DP-TPC are VL and
(VH-VL) respectively. Therefore, the maximum value of VL is
taken as the worst case when considering the voltage stress of
SLx1, while the minimum value of VL is taken as the worst case
when considering the voltage stress of SLx2. The current stresses
Embedded
DC - DC
Load
DP - TPC
Fig. 14. The picture of the hardware prototype.
DC-DC
Converter
T-type Three-level Converter

seen that, with any specific value of VL, when φ changes from
S Ha S Hb S Hc
-π/3 to π/3, PLN almost lies on a horizontal line, which indicates C2 S La 2 S La1 vA
S1 ia La
that the influence of the power factor is very slight. a
S Lb 2 S Lb1 vB
iL C3 ib Lb
V. EXPERIMENTAL EVALUATION AND ANALYSIS L1 VH b
o
S Lc 2 S Lc1 vC
A. Description of the Experimental Setup ic Lc
VL c
S2
An experimental platform of a 3kW bidirectional three-phase C1 S Za S Zb S Zc
DC-AC converter, which is composed of an embedded
bidirectional DC-DC converter and a DP-TPC, is built and n
tested. The experimental setup is shown in Fig. 14. For Fig. 15. The traditional two-stage DC-AC converter with cascaded
comparison, the traditional two-stage DC-AC converter, which DC-DC converter.
is composed of a cascaded bidirectional DC-DC converter and TABLE II
TEST SETUP PARAMETERS
Values
Parameters
Proposed Solution Traditional Solution
DC voltage VL 250~500V 250~500V
DC voltage VH 700V 700V
PLN
Filter capacitor C1, C2, C3 350μF, 560μF, NA 220μF, 220μF, 470μF
Inductor L1 2.5mH 2.5mH
Inductor Lx (x=a,b,c) 1.6mH 1.6mH
Switching frequency of
50kHz 50kHz
DC-DC converter fs1
Switching frequency of
DP-TPC or T-type 20kHz 20kHz
VL VH  converter fs2
Switches S1, S2 CMF20120D CMF20120D
Fig. 13. The normalized single-stage power PLN versus different VL Switches SHx, SZx (x=a,b,c) HGTG18N120BND HGTG18N120BND
values and different power factor angles φ. Switches SLx1, SLx2 (x=a,b,c) HGTG18N120BND FGH20N60UFD
TABLE III
VOLTAGE AND CURRENT STRESSES IN EACH SEMICONDUCTOR
Voltage Stress (V) Turn On/Off Current (A) Average Current (A) RMS Current (A)
Devices
Proposed Traditional Proposed Traditional Proposed Traditional Proposed Traditional
S1 700 700 11.15 13.55 3.29 4.32 5.67 7.42
S2 700 700 11.15 13.55 6.4 8.37 7.91 10.33
SHx (x=a,b,c) 700 700 6.43 6.43 1.41 1.43 1.87 2.72
SLx1/SLx2 (x=a,b,c) 500/450 350 6.43 6.43 1.75 0 2.87 2.39
SZx (x=a,b,c) 700 700 6.43 6.43 1.93 1.43 3.19 2.72

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

non-switching switching va (1V/ div) non-switching switching va (1V/ div) non-switching switching va (1V/ div)

VL (400V/ div) VL (400V/ div)

VL (400V/ div)

van (400V/ div) van (400V/ div) van (400V/ div)

t (5ms/div) ia (20A/ div) t (5ms/div) ia (20A/ div) t (5ms/div) ia (20A/ div)

(a) (b) (c)
Fig. 16. Experimental waveforms of the modified modulation signals: (a) VL=250V, (b) VL=350V, (c) VL=500V.
of S1 and S2 of the embedded DC-DC converter in the proposed van (1kV/div) zoom-in
solution are less than the traditional solution, because only part
of the total power needs to be processed by the embedded vbn (1kV/div)
DC-DC converter. It should be noted that the power rating of
the embedded DC-DC converter is determined by the range of VH  VL VL VH  VL
VL. A higher value of VL is much better for the DC-DC 0 0
converter. For the specifications of the prototype, the worst vab (1kV/div)
case is related to VL=250V, in which the normalized t (5ms/div) ia (20A/div)
single-stage power supplied by the LV port is minimum, i.e.,
Fig. 17. Experimental waveforms of van, vbn, vab and ia when VL=250V.
PLN =0.2, and almost 80% of the total power is processed by the
DC-DC converter. Therefore, compared to the traditional VH (400V/ div) VH (400V/ div)
two-stage solutions, the power rating of the DC-DC converter
can be reduced by 20%. In practice, if the minimum value of VL VL (400V/ div) VL (400V/ div)
is higher, the power rating of the DC-DC converter can be
reduced more significantly.
The most popular CB-PWM strategy, where the  =  60 van (400V/ div)  =60 van (400V/ div)
zero-sequence component is expressed as v0 = - (vmin+ vmax)/2,
is used for the T-type three-level converter [15], while the t (10ms/div) ia (20A/ div) t (10ms/div) ia (20A/ div)
proposed CB-PWM strategy is employed for the DP-TPC. The (a) (b)
control is realized with a digital controller DSP28335. As Fig. 18. Steady-state waveforms of grid voltage vA and phase current ia
shown in Fig. 5, PI controller is employed for the current and with VL=350V and different values of φ: (a) φ= -60°, (b) φ= 60°.
voltage control loops. The controller design of the DP-TPC is 1.0
given in Appendix, while that of the embedded DC-DC
0.80.8 VL VH  5 7
converter is just the same as the traditional solution [22] and not
be repeated here.
0.60.6
B. Steady-state Waveforms PLN
VL VH  1 2
0.40.4
To validate the proposed CB-PWM strategy for the DP-TPC,
experimental tests are carried out taking three specific VL VL VH  5 14
0.20.2
values, i.e., VL=250V, 350V, 500V, respectively, as examples. Theoretical curve
The experimental waveforms of the modified modulation 0  01.047
Experimental results
 3  6  6  3
 0.524 0 0.524 1.047
signals, which are obtained by D/A conversion, are given in 0

Fig.16, where va is the modified modulation signal of phase A,
Fig. 19. Comparison between the theoretical curves and the
VL is the voltage of the LV port, van is the midpoint voltage of experimental results of PLN.
phase A and ia is the phase current. As shown in Fig. 16, the action during that time and the average frequency of these
waveform of the modulation signal is fully compatible with the switches can be reduced by 33%. This fully agrees with the
analysis illustrated in Fig. 9. The modulation signal keeps theoretical analysis illustrated in Section III.
invariant with different values of VL, because the modulation The steady-state waveforms of the midpoint line voltage
index m is only determined by the ratio of VACPK and VH, both of between phase A and phase B vab of the DP-TPC when
which are kept as constant values. However, along with VL VL=250V are given in Fig. 17. It is seen that, the midpoint
varying, the boundary line of the asymmetrical carrier voltage is asymmetrical and changes among four voltage levels,
waveforms, which is in proportion to VL, would be changed i.e., 0, VL, VH-VL, VH, because the voltage levels VL and VH-VL
accordingly. This can be observed by the yellow solid line in are not equal. This would be very different from the traditional
Fig. 16, which represents VL and can be further equivalent to the three-level converter.
boundary line of the asymmetrical carrier waveforms by To validate the influence of power factor, experimental
properly adjusting the ratio of D/A conversion. Moreover, it is waveforms at different power factor conditions are given in
observed that during each 120°interval of a fundamental cycle, Fig.18. As shown in Fig. 18(a) and (b), there exists a
both the modulation signal va and the voltage van are clamped displacement angle, which is equal to -60°and 60°respectively,
to zero, which implies that the switches SLa1 and SZa are not in between the grid voltage and phase current. The normalized

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

single-stage power supplied by the LV port, PLN, at various harmonic distortion (THD) analysis. The THD is measured
values of VL and φ is tested with power analyzer, with power analyzer, YOKOGAWA WT1800. The data of the
YOKOGAWA WT1800, which guarantees power accuracy of phase current was collected by a Tektronix MDO3014
0.05% of reading plus 0.05% of range. The comparison oscilloscope and then processed using the Matlab fast Fourier
between the theoretical and experimental results of PLN is transform (FFT) function for harmonics analysis. The
illustrated in Fig. 19. The theoretical curves are obtained by measured results are given in Fig. 21. Due to the asymmetrical
picking up several specific VL values from Fig. 13. It is multilevel characteristics, the THD performance of the
observed that the errors between the experimental tested results proposed DP-TPC is not as good as the traditional symmetrical
and theoretical curves, which are possibly caused by the power operated three-level converter. As shown in Fig. 21(a), the
losses of the experimental setup and the measurement errors, THD performance of the DP-TPC is almost the same with the
are relatively small. Moreover, all the tested results indicate symmetrical operated three-level converter when VL is close to
that the normalized single-stage power PLN is slightly 350V, but becomes worse as the increasing of VL voltage, which
influenced by the power factor angle φ. indicates that the THD performance of the DP-TPC is related to
the voltage of VL. The relatively significant harmonic
C. Dynamic Waveforms
components for the THD performance are shown in Fig. 21(b),
The experimental result of the transition operation for where it is seen that the low-order harmonics of the DP-TPC are
bidirectional power flow of the proposed DC-AC converter is slightly higher than the three-level converter. This is possibly
given in Fig. 20, where iLoad is the load current, VL is the LV port because the dead-time effect would be different with the
voltage, vA is the grid voltage and ia is the phase current, variation of VL for the DP-TPC. To improve the THD
respectively. It is seen that the phase current ia is in phase with performance, the dead time compensation or resonant control
the grid voltage vA in the inverter mode, whereas ia is 180°out based harmonic compensation technique could be used.
of phase with vA in the rectifier mode. Meanwhile, when the
load suddenly changes, the converter can change from the E. Efficiency Evaluation
inverter mode to the rectifier mode immediately, which The overall efficiency of both the traditional and the
indicates that fast dynamic performance can be achieved by the proposed solutions is tested and compared. The efficiency
proposed bidirectional DC-AC converter. curves are tested under different VL values with two typical
loads, i.e., half load and full load, and different load conditions
D. Line Voltage and Current THD Performance
with two typical VL values, i.e., 350V and 500V, respectively.
The quality of line voltage (vab) waveform is evaluated by 98 98
weighted total harmonic distortion (WTHDV) analysis [23]. For 97 97
Efficiency(%)

Efficiency(%)
the proposed solution, the WTHDV values at different VL values, 96 96
95 95
i.e., 250V, 350V and 500V, are 0.40%, 0.41%, 0.43%, 94 94
respectively, while for the traditional solution, the WTHDV 93 93
92 92
value is 0.45%. It is found that the WTHDV values of the 91
DC-DC+DP-TPC DC-DC+DP-TPC
DC-DC+Three-level 91 DC-DC+Three-level
proposed and traditional solutions are quite close to each other, 90 90
200 250 300 350 400 450 500 200 250 300 350 400 450 500
which indicates that the proposed CB-PWM strategy used for VL (V) VL (V)
the DP-TPC does not lead to the increasing of WTHDV values.
(a) (b)
The quality of phase current (ia) is evaluated by total Fig. 22. Efficiency comparison with different VL: (a)half load, (b)full load.

zoom-in iLoad (10A/ div) 98 98

97 97
VL (100V/ div)
Efficiency(%)
Efficiency(%)

96 96
v A (400V/div) 95 95
94 94
93 93
ia (10A/ div) 92 92
DC-DC+DP-TPC DC-DC+DP-TPC
91 91
DC-DC+Three-level DC-DC+Three-level
t (1s/div) t (20ms/div) 90 90
20 30 40 50 60 70 80 90 100 20 30 40 50 60 70 80 90100
inverter mode rectifier mode inverter mode rectifier mode Load ratio(%) Load ratio(%)
Fig. 20. Dynamic waveforms of the proposed bidirectional DC-AC (a) (b)
converter changing from the inverter mode to the rectifier mode when Fig. 23. Efficiency comparison under different load conditions: (a)
the load suddenly changes. VL=350V, (b) VL=500V.
前后级总损耗
30
30
Percentage of fundamental (%)

33 S1 S2 SHx SLx2 SLx1 SZx

DP-TPC(VL=250V) DP-TPC(VL=250V) 120
Power losses of switches (W)

25
25 DP-TPC(VL=350V) 2.5
2.5
DP-TPC(VL=350V) A1:Proposed A2:Traditional
DP-TPC(VL=500V) 100
THD of ia(%)

DP-TPC(VL=500V) :Switching :Conduction

20
20
Three-level Converter 22
Three-level Converter 80
15
15 1.5
1.5

10
10 11 60

55 0.5
0.5 40
00 00 20
0.10 0.20 30
20 0.40 50
0.30 40 0.60 70
0.50 60 0.80 90
0.70 80 0.90 100
1.00 1.10 1 2
5th
3 4 5 6 7
7th 11th 13th 17th
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Load ratio(%) 1 2
Harmonic order
3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25 0 A1 A2 A1 A2 A1 A2
(a) (b) VL=250V VL=350V VL=500V
Fig. 21. Comparison of THD performance and harmonics of phase
Fig. 24. Comparison of the power losses of active switches between
current ia: (a) THD performance, (b) harmonics analysis.
the proposed DC-AC converter and the traditional two-stage solution.

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

The tested results are shown in Fig. 22 and Fig. 23, where it is vd iLoad
VL*  id*    VL
obvious that much higher efficiency can be achieved by the  1 id 3vd idc  1
Gv ( s ) Gi ( s ) Gd ( s ) K PWM
 sLx 2VL sC1
proposed DC-AC converter compared to the traditional  
Hi
two-stage solution. Detailed power loss breakdown of active
switches of the proposed DC-AC converter and the traditional Hv

two-stage DC-AC converter is calculated [24] and shown in
Fig.24. It is seen that the power losses of active switches can be
reduced by the proposed solution, in which the power loss
reduction of S1, S2 and SHx benefits from the quasi single stage
structure, while the power loss reduction of SLx1 and SZx benefits
from the reduced average switching frequency. Taking the case
of VL=350V as an example, the power loss reduction of active
switches of the proposed solution is 15.9W, in which 8.3W is
from the reduced average switching frequency and the other is
from the quasi single stage structure.
These attractive advantages, e.g., higher overall efficiency,
lower power rating and cost of the DC-DC converter, suggest
that the proposed bidirectional three-phase DC-AC converter is
a good candidate for practical applications such as energy
storage systems, uninterrupted power supplies, etc.
VI. CONCLUSION
A novel bidirectional three-phase DC-AC converter with
embedded DC-DC converter and its carrier-based PWM
(CB-PWM) strategy is proposed in this paper. Theoretical
analysis and experimental verification indicate that the
proposed DC-AC converter with the CB-PWM strategy has the
following features:
(1) With the help of the embedded DC-DC converter, the
voltage of storage battery can vary in a wide range.
(2) By employing the proposed CB-PWM scheme, most
active power is processed by the DP-TPC within single power
conversion stage and only a small ratio of total power needs to
be processed by the embedded DC-DC converter. Therefore,
the power rating and power losses of the embedded DC-DC
converter are reduced.
(3) For the DP-TPC, the proposed CB-PWM strategy
reduces the average switching frequency of the switches and
consequently lower power losses can be achieved.
(4) Since quasi single-stage power conversion is achieved by
the proposed DC-AC converter, the conversion efficiency of
the overall DC-AC power system is improved.
All these attractive features make the proposed DC-AC
converter with the CB-PWM strategy be attractive for various
high efficiency bidirectional DC-AC power conversion
applications, such as energy storage systems, electric vehicles,
micro-grids and so on.
APPENDIX
This Appendix presents the controller design of the DP-TPC.
The DC voltage VL is regulated by the DP-TPC, and the control
diagram is shown in Fig. A1. The current loop in d-axis is
inside the dashed block. PI controller is applied in both the
inner current control loop and the outer voltage control loop.
The stability of the current control loop is determined by the
open-loop transfer function Gi_open(s) as follows
1 [9]
Gi _ open ( s)  Gi ( s)  Gd ( s)  K PWM   Hi (A1)
sLx
Fig. A1. DC voltage control diagram in d-axis.
where Gi(s) is the PI current controller expressed as
Gi (s)  kip  kii s , Gd(s) is the digital delay expressed as
Gd (s)  e1.5sTs , KPWM is the PWM unit and Hi is the feedback
coefficient of the inductor current. In this paper, KPWM=350 and
Hi=1. To ensure the stability and good dynamic performance,
the cutoff frequency of the current loop fci is set at 1.7kHz with a
phase margin of 450. This yields kip=0.057, kii=20.7. Since the
current loop in q-axis is similar to the d-axis, the parameters of
the current controller in q-axis are the same as that in d-axis.
As the current loop already designed, the open-loop transfer
function of the voltage loop is given by
Gi _ open ( s) 3vd 1
Gv _ open ( s)  Gv ( s)     H v (A2)
1  Gi _ open ( s) 2VL sC1
where Gv(s) is the PI voltage controller expressed as
Gv (s)  kvp  kvi s , vd is the peak value of the phase voltage and
Hv is the feedback coefficient of the DC voltage. In this paper,
vd= 220 2 and Hv=1. To ensure the stability of the system, the
bandwidth of the voltage loop should be lower than the current
loop. Hence, the cutoff frequency of the voltage loop fcv is set at
200Hz with a phase margin of 450. This yields kvp=0.6, kvi=488.
REFERENCES
[1] S. Vazquez, S. M. Lukic, E. Galvan, L. G. Franquelo and J. M. Carrasco,
“Energy Storage Systems for Transport and Grid Applications,” IEEE
Trans. Ind. Electron., vol. 57, no. 12, pp. 3881-3895, Dec. 2010.
[2] J. G. de Matos, F. S. F. e Silva and L. A. d. S. Ribeiro, “Power Control in
AC Isolated Microgrids With Renewable Energy Sources and Energy
Storage Systems,” IEEE Trans. Ind. Electron., vol. 62, no. 6, pp.
3490-3498, June 2015.
[3] V. Vekhande, K. V. K. and B. G. Fernandes, “Control of Three-Phase
Bidirectional Current-Source Converter to Inject Balanced Three-Phase
Currents Under Unbalanced Grid Voltage Condition,” IEEE Trans.
Power Electron., vol. 31, no. 9, pp. 6719-6737, Sept. 2016.
[4] S. Mehrnami, S. K. Mazumder and H. Soni, “Modulation Scheme for
Three-Phase Differential-Mode Ćuk Inverter,” IEEE Trans. Power
Electron., vol. 31, no. 3, pp. 2654-2668, March 2016.
[5] M. Kesler, M. C. Kisacikoglu and L. M. Tolbert, “Vehicle-to-Grid
Reactive Power Operation Using Plug-In Electric Vehicle Bidirectional
Offboard Charger,” IEEE Trans. Ind. Electron., vol. 61, no. 12, pp.
6778-6784, Dec. 2014.
[6] Y. Zhang, Q. Liu, J. Li and M. Sumner, “A Common Ground
Switched-Quasi-Z-Source Bidirectional DC-DC Converter With
Wide-Voltage-Gain Range for EVs With Hybrid Energy Sources,” IEEE
Trans. Ind. Electron., in publication, 2017, DOI:
10.1109/TIE.2017.2756603.
[7] X. Wang, C. Jiang, B. Lei, H. Teng, H. K. Bai and J. L. Kirtley,
“Power-Loss Analysis and Efficiency Maximization of a Silicon-Carbide
MOSFET-Based Three-Phase 10-kW Bidirectional EV Charger Using
Variable-DC-Bus Control,” IEEE J. Emerg. Sel. Topics Power Electron.,
vol. 4, no. 3, pp. 880-892, Sept. 2016.
[8] S. Kim, M. Kwon and S. Choi, “Operation and Control Strategy of a New
Hybrid ESS-UPS System,” IEEE Trans. Power Electron., in publication,
2017, DOI: 10.1109/TPEL.2017.2733019.
S. Hu, Z. Liang and X. He, “Ultracapacitor-Battery Hybrid Energy
Storage System Based on the Asymmetric Bidirectional Z-Source
Topology for EV,” IEEE Trans. Power Electron., vol. 31, no. 11, pp.
7489-7498, Nov. 2016.

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
[10] S. Hu, Z. Liang, D. Fan and X. He, “Hybrid Ultracapacitor–Battery
Energy Storage System Based on Quasi-Z-source Topology and
Enhanced Frequency Dividing Coordinated Control for EV,” IEEE Trans.
Power Electron., vol. 31, no. 11, pp. 7598-7610, Nov. 2016.
[11] H. Wu, L. Zhu, F. Yang, T. Mu, H. Ge, “Dual-DC-Port Asymmetrical
Multi-Level Inverters with Reduced Conversion Stages and Enhanced
Conversion Efficiency,” IEEE Trans. Ind. Electron., vol. 64, no. 3, pp.
2081-2091, Mar. 2017.
[12] P. Chamarthi, P. Chhetri and V. Agarwal, “Simplified Implementation
Scheme for Space Vector Pulse Width Modulation of n-Level Inverter
With Online Computation of Optimal Switching Pulse Durations,” IEEE
Trans. Ind. Electron., vol. 63, no. 11, pp. 6695-6704, Nov. 2016.
[13] J. Wang, Y. Gao and W. Jiang, “A Carrier-Based Implementation of
Virtual Space Vector Modulation for Neutral-Point-Clamped
Three-Level Inverter,” IEEE Trans. Ind. Electron., vol. 64, no. 12, pp.
9580-9586, Dec. 2017.
[14] C. Wang and Y. Li, “Analysis and Calculation of Zero-Sequence Voltage
Considering Neutral-Point Potential Balancing in Three-Level NPC
Converters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2262-2271,
Jul. 2010.
[15] J. Pou, J. Zaragoza, S. Ceballos, M. Saeedifard and D. Boroyevich, “A
Carrier-Based PWM Strategy With Zero-Sequence Voltage Injection for
a Three-Level Neutral-Point-Clamped Converter,” IEEE Trans. Power
Electron., vol. 27, no. 2, pp. 642-651, Feb. 2012.
[16] J. I. Leon, S. Kouro, L. G. Franquelo, J. Rodriguez and B. Wu, “The
Essential Role and the Continuous Evolution of Modulation Techniques
for Voltage-Source Inverters in the Past, Present, and Future Power
Electronics,” IEEE Trans. Ind. Electron., vol. 63, no. 5, pp. 2688-2701,
May 2016.
[17] Z. Wang, F. Cui, G. Zhang, T. Shi and C. Xia, “Novel Carrier-Based
PWM Strategy With Zero-Sequence Voltage Injected for Three-Level
NPC Inverter,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 4, no. 4,
pp. 1442-1451, Dec. 2016.
[18] S. K. Giri, S. Chakrabarti, S. Banerjee and C. Chakraborty, “A
Carrier-Based PWM Scheme for Neutral Point Voltage Balancing in
Three-Level Inverter Extending to Full Power Factor Range,” IEEE
Trans. Ind. Electron., vol. 64, no. 3, pp. 1873-1883, Mar. 2017.
[19] J. S. Lee, S. Yoo and K. B. Lee, “Novel Discontinuous PWM Method of a
Three-Level Inverter for Neutral-Point Voltage Ripple Reduction,” IEEE
Trans. Ind. Electron., vol. 63, no. 6, pp. 3344-3354, June 2016.
[20] R. Maheshwari, S. Busquets-Monge and J. Nicolas-Apruzzese, “A Novel
Approach to Generate Effective Carrier-Based Pulsewidth Modulation
Strategies for Diode-Clamped Multilevel DC–AC Converters,” IEEE
Trans. Ind. Electron., vol. 63, no. 11, pp. 7243-7252, Nov. 2016.
[21] M. Schweizer and J. W. Kolar, “Design and Implementation of a Highly
Efficient Three-Level T-Type Converter for Low-Voltage Applications,”
IEEE Trans. Power Electron., vol. 28, no. 2, pp. 899-907, Feb. 2013.
[22] D. Somayajula and M. L. Crow, “An integrated active power filter–ultra
capacitor design to provide intermittency smoothing and reactive power
support to the distribution grid,” IEEE Trans. Sustain. Energy, vol. 5, no.
4, pp. 1116–1125, Oct. 2014.
[23] B. Diong, H. Sepahvand and K. A. Corzine, “Harmonic distortion
optimization of cascaded H-bridge inverters considering device voltage
drops and noninteger dc voltage ratios,” IEEE Trans. Ind. Electron., vol.
60, no. 8, pp. 3106–3114, Aug. 2013.
[24] A. K. Sadigh, V. Dargahi and K. A. Corzine, “Investigation of
Conduction and Switching Power Losses in Modified Stacked Multicell
Converters,” IEEE Trans. Ind. Electron., vol. 63, no. 12, pp. 7780-7791,
Dec. 2016.
Jiangfeng Wang (S’15) was born in Zhejiang
Province, China, in 1990. He received the B.S. degree
in electrical engineering and automation from
Nanjing University of Aeronautics and Astronautics,
Nanjing, China, in 2012, where he is currently
working toward the Ph.D. degree in electrical
engineering.
His research interests include the grid-tied inverter
control, renewable energy generation system and
power quality.
0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Hongfei Wu (S’11, M’13, SM 18) received the B.S.
and Ph. D degrees in electrical engineering and power
electronics and power drives from Nanjing University
of Aeronautics and Astronautics (NUAA), Nanjing,
China, in 2008 and 2013, respectively.
Since 2013, he has been with the Faculty of
Electrical Engineering, NUAA, and is currently a
Professor with College of Automation Engineering,
NUAA. He has authored and co-authored more than
140 peer-reviewed papers published in journals and
conference proceedings. He is the holder of more than 30 Patents. His research
interests are high performance power converters and distributed power
generation system.
Dr. Wu was the recipient of the Outstanding Reviewer of IEEE Transactions
on Power Electronics (2013). He was a recipient of the Changkong Scholar
Award and Young Scholar Innovation Award of NUAA in 2017. He serves as
an Associate Editor of Journal of Power Electronics and CPSS Transactions on
Power Electronics and Applications.
Tianyu Yang was born in Jiangsu Province, China, in
1994. He received the B.S. degree in electrical
engineering from Nanjing University of Aeronautics
and Astronautics (NUAA), Nanjing, China, in 2016.
He is currently working toward the M.S. degree in
electrical engineering and power drives from NUAA,
Nanjing, China.
His research interests include modulation and
control of AC-DC converters, power quality.
Li Zhang (S’11-M’13) received the B.E. and Ph.D.
degrees in electrical engineering from Nanjing
University of Aeronautics and Astronautics (NUAA),
Nanjing, China, in 2007, and 2012, respectively.
He joined the Faculty of Electrical Engineering,
Hohai University, Nanjing, China, in 2014, where he
is currently a Professor. From Oct. 2012 to Sep. 2014,
he was a Post-Doctoral Research Fellow with the
Department of Electrical Engineering, Tsinghua
University, Beijing, China. From Jul. to Aug. 2012,
he was a Visiting Scholar of Electrical Engineering at Department of Energy
Technology, Aalborg University, Denmark. From Oct. 2016 to Oct. 2017, he
was a Visiting Scholar of Electrical Engineering at Department of Electrical
and Computer Engineering, Ryerson University, Canada. His current research
interests include topology, control of dc-ac converter and distributed generation
technology.
Dr. Zhang was a recipient of the IEEE TRANSACTIONS ON POWER
ELECTRONICS Outstanding Reviewer Award in 2014.
Yan Xing (M’03) was born in Shandong Province,
China, in 1964. She received the B.S. and M.S.
degrees in automation and electrical engineering from
Tsinghua University, Beijing, China, in 1985 and
1988, respectively, and the Ph.D. degree in electrical
engineering from Nanjing University of Aeronautics
and Astronautics (NUAA), Nanjing, China, in 2000.
Since 1988, she has been with the Faculty of
Electrical Engineering, NUAA, and is currently a
professor with College of Automation Engineering,
NUAA. She has authored more than 100 technical papers published in journals
and conference proceedings and has also published three books. Her research
interests include topology and control for dc-dc and dc-ac converters.
Dr. Xing is an Associate Editor of the IEEE Transactions on Power
Electronics and Journal of Power Electronics. She is a member of the
Committee on Renewable Energy Systems within the IEEE Industrial
Electronics Society.