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The University of Lahore

Assignment # 1
CLO1 (PLO2)
CEP [1, 3, 4]

Name:_____________________________ Registration No:________________________________

Total Marks: 10 Time allowed: 1 week

Q1. Recent trends in hardware reconfiguration have shown that the basic parameters of hardware can
be improved by Genetic Engineering technique called Evolutionary Hardware (EHW). EHW can
transform autonomously to adapt to the surrounding environment. EHW process is stochastic in nature
where all the design steps mimic the biological evolution given below.
1. Initialize population with random candidate solutions
2. Evaluate each candidate
3. Repeat until best solution is produced
a) Select parents
b) Recombine pairs
c) Mutate the resulting offspring
d) Evaluate new candidates
e) Select individuals from new generation

Breakdown the above information with the help of research papers on EHW and analyze the gate level
circuits given in table 1 (extracts from research papers) with respect to their timing waveform and area
consumption in Xilinx Artix7. Your analysis should be in context of EHW.

Table 1 Comparison of Original and Evolved Hardware Circuit

Original Circuit Evolved Circuit

1-bit Full Adder


The University of Lahore
Assignment # 1
CLO1 (PLO2)
CEP [1, 3, 4]

Name:_____________________________ Registration No:________________________________

Total Marks: 10 Time allowed: 1 week


Original Circuit Evolved Circuit

2-bit Full Adder

3-bit Full Adder


The University of Lahore
Assignment # 1
CLO1 (PLO2)
CEP [1, 3, 4]

Name:_____________________________ Registration No:________________________________

Total Marks: 10 Time allowed: 1 week


Original Circuit Evolved Circuit

4-bit Full Adder

Rubrics 9-10 6-8 3-5 1-2


Breakdown and Analysis is Analysis is Vague analysis is There is no
Program reinforced with somewhat similar presented which analysis and
Functionality results from to the results is not verified by simulations
synthesis report from synthesis synthesis report. results do not
by choosing report by Simulations verify program
correct FPGA choosing correct results verify functionality.
device and FPGA device and program
simulations simulations functionality.
results verify results verify
program program
functionality. functionality.