Email: kokkera484@gmail.com K.

Triveni Mobile: 8008477597

Career Objective

VLSI enthusiastic having good understanding of Advanced digital design concept seeks employment to be part of the
dynamic team that will allow me to further expand on these skills and contribute my best to the company

Professional Training

An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon Systems (ISS). Hyderabad (Aug-2018 -
Present) .

COURSE OUTLINE:

VLSI Fundamentals, CMOS Basics, Digital Design Floor Planning, Power Planning, Placement and Routing, clock tree
synthesis, static timing analysis timing optimization, cross talk analysis, IR Drop Analysis and Physical Verification.

Tools:

Experience in physical design of 130nm and 180nm technologies using Cadence tool

 Cadence Innovus–Floor Planning, Place & Route, and clock tree synthesis
 Tempus –Static Timing Analysis and Crosstalk Analysis
 Genus- Logic Synthesis
 Assura – Physical Verification

PROJECTS:

Project 1: BLOCK 1
Objective: Timing Driven Layout
Tools: Innovus
Aspect Ratio: 1.8906
Core Utilization: 87.2%
Gate Count/Area: 2, 95,935/ 1062025.81 um^2
Macros /STD Cells: 12/27096
No. of Clocks: 17
Frequency: 200MHz
Technology/Layers: TSMC 0.13 micron/5 Metal Layers

Role:
Performing sanity check, Design import , Floor Plan , Power Plan , Placement ,Trail Route, Power Analysis, RC
Extract, Timing Analysis, IPO, CTS, Adding filler cells, Timing Analysis.
Email: kokkera484@gmail.com K. Triveni Mobile: 8008477597

Project 2: BLOCK 2
Objective: Timing Driven Layout
Tools: Innovus
Gate Count: 1,18,676
Blocks/Cells/IOs: 12/24450/120
No. of Clocks: 4
Frequency: 150 MHz
Technology: TSMC 0.18 micron

Role:
Performing sanity check, Design import , Floor Plan , Power Plan , Placement ,Trail Route, Power Analysis, RC
Extract, Timing Analysis, IPO, CTS, Adding filler cells, Timing Analysis.

Project 3: BLOCK 3

Objective: Timing Driven

Tools: Innovus
Aspect Ratio: 0.9986
Core Utilization: 85.4%
Gate count/Area: 2,96,296/1508801.9num^2
No. of Clocks: 17
Frequency: 200 MHz
Technology: TSMC 0.13 micron

Role:

Performing sanity check, Design import , Floor Plan , Power Plan , Placement ,Trail Route, Power Analysis, RC Extract,
Timing Analysis, IPO, CTS, Adding filler cells, Timing Analysis.

LOGIC SYNTHESIS

Project 1: COUNTER_16

Objective: Running Zero and Force Wire Load Model Synthesis by meeting Timing, optimizing Area and Power.
Tools: Cadence Encounter RTL Compiler
No. of Clocks: 2
Frequency: 200MHz
Technology: TSMC 0.18 micron

Responsibilities:

Writing SDC, TCL Scripts, Extracting Timing, Optimizing Area, Timing and Power.
Email: kokkera484@gmail.com K. Triveni Mobile: 8008477597

Project 2: COUNTER_32
Objective: Running Zero Wire Load Model Synthesis and to achieve Maximum possible frequency for different
VTs.
Tools: Cadence Encounter RTL Compiler
No. of Clocks: 1
Frequency: 645MHz (RVT), 322MHz (HVT), 645MHz (MVT)
Technology: TSMC 0.18 micron

Responsibilities:
Writing SDC, TCL Scripts, Extracting Timing, Optimizing Area, Timing and Power.

LAYOUT DESIGN

STANDARD CELLS
Tools: Virtuoso Layout Editor (Designing Layouts), Assura (Physical Verification)
Cells Designed: INVERTER, NAND, NOR, AND, OR, EX-OR, EX-NOR
Technology: TSMC 0.13 micron

Responsibilities:
Designing Layouts and Verifying DRC and LVS checks.

Technical Skill Set

Hardware Description Languages : Verilog

Programming Languages: : Basics of C
Operating Systems: Linux, Windows.

Education

1. 61% in Bachelor of Technology (ECE).Swarna Bharathi Institute of Science & Technology

2. 82.4% in Board of Intermediate(MPC).Resonance Junior college
3. 75% in Board of Secondary school Education. RR High School

ACADEMIC PROJECTS:
1. MAJOR PROJECT TITLE: Color Based Automatic Gun Targeting System.
2. MINI PROJECT TITLE: Repetition pattern extraction technics.

Personal Strengths

1. I can easily adopt to any Technology.

2. I have good logical knowledge towards problem solving.