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 INVITED
PAPER
Progress and Challenges in
VLSI Placement Research
Extensive research studies performed over the last 50 years addressed numerous
aspects of global and detailed placement, a fundamental step in the physical design of
integrated circuits. This paper surveys the history of placement research, the progress
leading up to the state of the art, and outstanding challenges.
By Igor L. Markov, Fellow IEEE , Jin Hu, and Myung-Chul Kim
ABSTRACT | Given the significance of placement in integrated
circuit (IC) physical design, extensive research studies per-
formed over the last 50 years addressed numerous aspects of
global and detailed placement. The objectives and the con-
straints dominant in placement have been revised many times
over, and continue to evolve. Additionally, the increasing scale
of placement instances affects the algorithms of choice for
high-performance tools. We survey the history of placement
research, the progress leading up to the state of the art, and
outstanding challenges.
KEYWORDS | Circuit placement; large-scale optimization;
layout
I. INTRODUCTION
Integrated circuits (ICs), whose invention by Jack Kilby and
Robert Noyce was honored by the 2000 Nobel prize in
Physics, have captured the minds of scientists, engineers,
students, entrepreneurs, as well as users of industrial and
consumer electronics. Buoyed by high demand, ICs grew in
size over the last 50 years from several hundred compo-
nents to over a billion components on a single semiconduc-
tor chip. Their increasing sophistication helped automate
the design process [114], [206] and necessary bookkeeping,
as well as perform efficient global optimization. Physical
design is particularly involved [10], [95], due to its com-
Manuscript received September 11, 2014; revised July 5, 2015 and August 25, 2015;
accepted September 2, 2015. Date of publication October 9, 2015; date of current
version October 26, 2015. This work was supported in part by the U.S. National Science
Foundation under Award 1162087; by the Semiconductor Research Corporation under
Project 2264; and by the Mentor Graphics Corporation.
I. L. Markov is with the Department of Electrical Engineering and Computer Science,
University of Michigan, Ann Arbor, MI 48109 USA (e-mail: imarkov@eecs.umich.edu).
J. Hu is with IBM Corporation, Hopewell Junction, NY 12533 USA.
M.-C. Kim is with IBM Corporation, Austin, TX 78758 USA.
Digital Object Identifier: 10.1109/JPROC.2015.2478963
0018-9219  2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE
putational complexity, multiobjective optimization, and
sensitivity to advances in semiconductor manufacturing.
Here we focus on circuit placementVthe challenge of
finding good locations for individual circuit components.
The importance of the topic can be seen from previous
surveys [30], book chapters [10], [114], [206], and entire
books on circuit placement [141], [173]. This survey covers
developments in the field up to 2015 and discusses the
necessary interactions with other aspects of modern
physical design.
Research on very large scale integration (VLSI) place-
ment can be traced back to the 1960s, when the first netlist
partitioning methods were developed in the industry, and
subsequently motivated improvements in graph partition-
ing heuristics. Analytical placers1 started appearing in the
early 1980s, but were eclipsed by combinatorial techniques
when simulated annealing was invented. Annealing-based
placers [183] dominated industry use and academic results
for a decade, but by the mid-1990s, annealing was no longer
scalable for newer and larger designs. Despite the steady
improvement of analytical placement, partitioning-based
methods improved enough to provide leading-edge perfor-
mance: 1) (multilevel) Fiduccia–Mattheyses (FM) [63]
heuristics produced much better results much faster than
previous methods; 2) the use of end-case techniques (op-
timal partitioning and end-case placement) during top–
down layout optimization provided high-quality detailed
placement [18]; and 3) the use of flat and multilevel FM
heuristics was carefully optimized, including cutline selec-
tion and hierarchical whitespace allocation [24].
By 2005, several analytical techniques have matured to
the point where they reliably outperformed min-cut place-
ment on contemporary large global placement instances. In
addition to the innovations in algorithms, this was due to
1
Analytical placers model interconnect length by differentiable
functions and use smooth optimization techniques.
1985
Markov et al.: Progress and Challenges in VLSI Placement Research

the change in the nature of placement instances. In parti-
cular, having between 100 000 and 10 million movable
objects during global placement provided a better justifi-
cation to modeling each object as a dimensionless dot.
Industry methodologies provided global placement with a
large number of fixed objects [input/ouput (I/O) pads, fixed
pins, macro blocks, etc.]. Due to concerns of routability,
physical synthesis, power density, large size of I/O pads,
large IP blocks, etc., core placement area now often in-
cludes a large amount of unused space [141] which provides
analytical algorithms with useful freedom. In terms of
algorithms, high-quality detailed placement was developed,
resolving a long-standing handicap in analytical engines.
These improvements fueled algorithmic developments
based on multivariate calculus, numerical analysis, and
combinatorial optimization [141]. Resulting reductions in
interconnect length enhanced many types of semiconduc-
tor designsVfrom field-programmable gate arrays (FPGAs)
and application-specific integrated circuits (ASICs) to cen-
tral processing units (CPUs) and mixed-signal systems on a
chip (SoCs). They have surpassed the length reduction ty-
pical for a new technology node. Despite such major prog-
ress, there is currently no agreement on which algorithms
are considered best. Comparisons remain largely empirical
[141] and are often affected by the quality and maturity of
software implementations, use of parallel processing and
high-performance libraries, as well as reporting methodol-
ogies. Fig. 1 depicts the evolution of academic global
placers and their correspondence to commercial placers.
Experimental results suggest that academic placers are
competitive to industry placers on very specific objectives,
but less effective on multiobjective optimizations prevalent
in commercial designs [94].
Recent advances in placement algorithms include:
1) high-performance wirelength-driven placement; 2)
mixed-sized placement (i.e., simultaneous placement of
both cells and macros); 3) routability-driven placement;
4) timing- and power-driven placement; and 5) the
integration of global placement into physical synthesis.
I I. WIRELENGTH-DRI VEN PLACE MENT
Modern placement is an optimization problem with many
objectives and constraints. However, the most common ap-
proach is to first develop a wirelength-driven global place-
ment engine that solves a straightforward mathematical
formulation and is competitive on common benchmarks.
This is a prerequisite for strong performance in multiob-
jective optimization, and the handling of additional objec-
tives and constraints can be implemented as the next step.
We cast global placement [95] as constrained optimi-
zation and explain how the objective is approximated by
smooth differentiable functions to facilitate fast numerical
methods. Common types of global placement algorithms
are reviewed next, followed by legalization and detailed
placement.

Fig. 1. Historical development of global placement algorithms and implementations in academia. Asterisks indicate placers that were developed
or implemented in the industry (often by recent students)Vat IBM, Synopsys, and Mentor Graphics. Daggers indicate adoption of academic work
and commercialization: TimberWolf was used by most EDA flows in the late 1980s, algorithms in PROUD were adapted in Cadence QPlace
throughout the 1990s, KraftWerk algorithms were used by Intel and Magma, the Capo codebase was commercialized by Synplicity and Achronix,
NTUPlace was commercialized by MediaTec, and mPL was commercialized for FPGA layout. Most academic placers presaged respective
industry placers, and are described in greater detail in the literature. Part of APlace’s contribution was deconstructing and describing
Naylor’s original patent [142].

1986 Proceedings of the IEEE | Vol. 103, No. 11, November 2015
 Markov et al.: Progress and Challenges in VLSI Placement Research
A. The Objectives and the Constraints
The intuition for placement objectives is based on
viewing a circuit as a graph where vertices model gates.
The shorter the wires connecting the gates, the faster is the
circuit. Therefore, we add up the lengths of edges and
minimize the sum. Given that wire routes consist of only
horizontal and vertical segments, lengths must be mea-
sured in the Manhattan planeVas the sum of x-span and
y-span. When a single logic gate drives multiple logic gates,
we generalize edges to hyperedges by replacing two-
element vertex sets with larger sets of vertices. The length
contribution of a hyperedge is also calculated as the sum of
its x-span and y-span. We now formalize this intuition.
Global placement [95, Ch. 4] of a netlist N ¼ ðE; VÞ
with nets E and n nodes (cells) V seeks a set of planar node
locations ð~x;~yÞ 2 ½xmin ; xmax n  ½ymin ; ymax n that mini-
mize the weighted Half-Perimeter WireLength (wHPWL).
Locations of individual circuit elements ðxi ; yi Þ are com-
bined in two vectors ~x ¼ ðx1 ; . . . ; xn Þ and ~
y ¼ ðy1 ; . . . ; yn Þ.
While less intuitive, this notation helps dealing with the x
and y components separately. Net weights are captured as
vector ~w ¼ ðwÞi , then wHPWLN ð~ x;~yÞ ¼ wHPWLN ð~
wHPWLN ð~ yÞ, where
wHPWLN ð~
xÞ ¼ S e2E we ½max xi  min xi :
i2e i2e
The HPWL function is continuous and convex, but
not everywhere differentiable. It is amenable to combi-
natorial optimization, especially linear programming and
network flows. However, these techniques do not
combine well with other co-objectives, and are less scala-
ble than smooth optimization applied to approximations of
HPWL. Moreau’s theorem from convex analysis [177,
Prop. IV.1.8] implies that the gradient of such a convex
function is defined almost everywhere and can be ap-
proximated by the Yosida approximation of the function
whose accuracy is controlled by the positive parameter
 ! 0. While this specific approximation has not been used
in placement applications, a number of specialized ap-
proximations of HPWL have been proposed (Section II-B).
Minimizing a convex objective is not difficult in itself.
The main source of complexity in global placement is the
nonconvex constraints. Despite the variety of constraints
imposed in practice, two types are considered first. The
fixed-position constraints enforce given locations of certain
cells or macros. They are convex, can be substituted di-
rectly into the objective function, and do not require dedi-
cated computations. The density constraints 1) ensure
porosity, which is critical for routability and timing-
optimization transformations; and 2) prevent movable
objects from concentrating in small regions to ensure that
legalization can find nonoverlapping positions for all objects
with minimum disturbance from a global placement. When
analytical techniques for global placement are used, fixed-
position constraints play the important role of spreading
movable nodes between fixed positions as a side effect of
interconnect optimization before density constraints are
seriously considered. A second use, now commonly seen in
quadratic placers, is to temporarily extend the netlist with
fake nets (pseudonets) and fake cells (anchors) fixed at
carefully chosen locations. Again, the purpose is to decrease
peak density in the course of interconnect optimization.
B. Smooth Approximations of HPWL
Modern placement algorithms (Section II-C) rely on
approximations of the HPWL function, briefly surveyed
below.
Quadratic approximations used in many placers are
obtained by pricing every edge by its squared length, with a
certain weight. Their general form is
Q ð~ yÞ ¼ ~
x;~ x=2 þ ~
xT Qx~ x þ~
fx~ y=2 þ ~
yT Qy~ fy~
y (2)
xÞþ with matrices Qx ; Qy derived from the netlist and vectors
~
fx ; ~
fy that reflect connections to fixed objects. When
sufficiently many nodes in a connected netlist are fixed,
Q is strictly convex. The x and y components can be
(1)
optimized separately and quickly by solving sparse systems
of linear equations Qx~ x ¼ ~ fx and Qy~ y ¼ ~fy .
To make such quadratic functions more appropriate for
HPWL modeling, they are linearized [178] by adjusting the
approximations at every global placement iteration. In
particular, single-edge terms of the form wij ðxi  xj Þ2 are
changed to ðwij ðxi  xj Þ2 Þ=ðjx0i  x0j j þ "Þ where the primed
values are constants based on the result of the last itera-
tion. These adjustments modify nonzero elements of Qx
and Qy , but not the sparsity pattern.
To approximate HPWL by a quadratic objective, the
netlist N is first transformed into graphs Gx and Gy that
preserve the node set V and represent each two-pin net by a
single edge with weight 1=length. Larger nets are decom-
posed depending on the relative placement of vertices using
the Bound2Bound (B2B) model [62], [181]Vfor each p-pin
net, the extreme nodes (min and max) are connected to
each other and to each internal node by edges, with the
following weight:
1
wB2B
x;ij ¼
 : (3)
ðp  1Þ jxi  xj j þ "
The B2B model is inherently local as it is instantiated
for a particular set of x and y values and accurately repre-
sents HPWL only near those values. As x and y locations
change, the decomposition is recalculated, and the sparsity
patterns of matrices Qx and Qy change, while preserving
the numbers of nonzeros.
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE 1987
Markov et al.: Progress and Challenges in VLSI Placement Research

Nonquadratic approximations of HPWL, such as the rium states correspond to spread out placements.
log–sum–exp technique [170], approximates the bracketed Acknowledging that the density function ðx; yÞ may not
term in (1) for  ! 0 by the convex function be smooth, Kraftwerk [62], [181] looks for a twice-
differentiable potential function uðx; yÞ whose gradient
! ~
F ¼ ru represents a conservative force pointing away
X xk X from dense regions.2 The latter condition is formalized in
x =
 log e  þ log e k
! ½max xi  min xi : (4)
k2e k2e
i2e i2e terms of flux overH an arbitraryR closed
R contour C that
bounds region R: C ð~F  nC Þd~
c¼ R  dx dy. Then, using
the divergence theorem and ~ F ¼ ru, we have
Other such techniques are surveyed and compared in
[26], [77], and [117]. As with quadratic approximations, I ZZ ZZ
gradients are computed in closed form, but their numerical ð~
F  nC Þd~
c¼ Du dx dy ¼  dx dy: (5)
values must be updated as the placement changes. Nume-
C R R
rical minimization requires more than solving two sparse
linear systems.
This condition is satisfied by solutions of Poisson’s
C. Modern Global Placement Algorithms equation Du ¼ , which can be interpreted as finding the
We now review main types of modern placement algo- electrostatic potential u for the curl-free field ru generated
rithms and refer to specific publications for additional details. by a spatial charge distribution  (positive charges repre-
The common classification that we follow is not disjoint, sent cells and negative charges represent unused cell cites)
and some placement software combines multiple ideas. A word of caution: Poisson’s equation only gives a way to
Quadratic placement is the foundation of BonnPlace satisfy properties postulated for ~F. The developers of mPL6
[17], DPlace2.0 [131], mFAR [80], Kraftwerk [181], [27] noted that Poisson’s equation can be ill-defined and
FastPlace [195], and RQL [195], as well as SimPL [103], added a new term, producing the nonhomogenous
[105], MAPLE [107], and ComPLx [106]. The netlist is Helmholtz (screened Poisson’s) equation Du  "u ¼ ,
modeled by a graph, for which the quadratic objective is both of which are linear second-order elliptic partial differ-
formulated (Section II-B). The placer alternates between ential equations (PDEs) [144, Figs. 2 and 3]. This smoothing
quadratic optimization and steps that involve density esti- effect is formalized in [53] for both Poisson and Helmholtz
mation (including fixed obstacles), in some cases along PDEs by representing solutions as convolutions (over the
with dedicated spreading of movable objects. To decrease entire placement region R) of  with certain Green’s func-
peak density, placers employ a variety of combinatorial and tions Gðx; sÞ dependent on the boundary conditions
numerical techniques based on 1) network flows (Bonn-
Place); 2) self-contained estimation of density gradients Z
(FastPlace and RQL); and 3) ‘‘full spreading’’ (SimPL) and uðÞ ¼ Gð; ÞðÞd (6)
derived algorithms. In all cases, the objective in a pre- R
viously solved quadratic program is modified, and the
program is resolved.
Force-directed placement models interconnects by coil where  and  represent ðx; yÞ pairs in R. This observation
springs as described by Hooke’s law, and formulates equa- leads to a particularly efficient computation of ru. For
tions for force equilibrium, and solves these equations example, for Poisson’s equation 1) without boundary con-
using quadratic programming. We illustrate force-directed ditions, and 2) with zero gradients at infinity
placement Kraftwerk [181], where three forces are involved
in force-equilibrium equationVthe spring force, the hold
1
force, and the density-based (spreading) force. The spring 1) Gð; Þ ¼
k  k
force corresponds to a quadratic approximation of the
HPWL objective (Section II-B), the hold force is its ln k  k
2) Gð; Þ ¼ : (7)
‘‘opposite action’’ in the spirit of Newton’s Third Law of 2
motion, and the density force seeks to even out cell density.
Let ðx; yÞ denote the cell density at ðx; yÞ. The density In a recent development, ePlace [125] presents a dif-
force is then, loosely speaking, weight-averaged r [see ferent way to cast density leveling as an electrostatic
(6)]. The hold and density forces acting on a cell are equilibrium problem. This approach yields closed-form
cumulatively represented by a pseudonet connected to a gradients for global density reduction and theoretically
carefully placed fake fixed cell (anchor).
Density-based force computations were pioneered in 2
A conservative force ~
F satisfies the following equivalent conditions:
H
the context of force-directed placement [62], [181] as a F ¼ ru (a potential function exists); 2) 8 closed contour C: C ~
1) 9u : ~ F
specific choice for the additional forces such that equilib- c ¼ 0 (path independence); and 3) r  ~
d~ F ¼ 0 (curl-free force).

1988 Proceedings of the IEEE | Vol. 103, No. 11, November 2015
 Markov et al.: Progress and Challenges in VLSI Placement Research
guarantees progress toward configurations with lower po-
tential energy.
Alternatively, density leveling can be modeled by the
discrete transportation problem and solved by reduction to
network flows [16]. Approaches in this category approximate
the nonconvex global-placement problem by a sequence of
convex quadratic problems, often using additional forces
(or gradients) to construct intermediate problems.
Nonconvex optimization placers such as APlace [99],
mPL6 [27], NTUPlace3 [39], NTUPlace4 [78], and ePlace
[125] typically approximate HPWL by nonquadratic objec-
tive functions for which gradients (and Hessians) can be
computed analytically (Section II-B). The contribution of
fixed obstacles (e.g., macros) is modeled by 2-D step func-
tions, and then approximated by bell-shaped [39], [99]
functions, but often postprocessed by Gaussian smoothing
and leveling [39]. The combined optimization function is
nonconvex, in stark contrast to quadratic and force-
directed placement. Additional details can be found in
[30] and the survey in [114]. Nonlinear optimization em-
ployed by these algorithms is time consuming. It is often
accelerated using combinatorial netlist clustering.
Using netlist clustering in placement typically improves
the runtime of global optimization at the cost of a small loss
in solution quality. However, in some cases, it also im-
proves quality of result [107], [215]. Global placement uses
clustering in a similar fashion to multilevel partitio-
ningVthe netlist is first coarsened by clustering its
components. After optimization is performed quickly on
the coarse netlist, the netlist is refined by dissolving some
clusters into smaller clusters. Then, optimization is applied
incrementally, so as to refine the locations of smaller clus-
ters (which are initially given the location of the containing
cluster). Such refinement iterations can be repeated, al-
though some placers only perform it once. An algebraic
scheme for refinement is described in [34]. Commonly
used clustering algorithms include First-Choice [100]
(Capo, NTUplace) and Best-Choice [6] (APlace, mPL6,
FastPlace3, RQL, MAPLE). These algorithms proceed
bottom–up and sequentially select small groups (or just
pairs) of nodes/clusters to merge. The Best-Choice algo-
rithm sets clustering scores between pair of objects using a
function that decreases with their areas, and stores them in
a lazily updated priority queue. The SafeChoice algorithm
[215] is more conservative and time consumingVit seeks
groups of objects which can be merged without worsening
placement quality. When used with several different global
placement algorithms, SafeChoice improved results by
explicitly considering current cell locations and wirelength
gradients during clustering. MAPLE [107] pays particular
attention to incremental placement optimization after
cluster refinement, which helps recover solution quality
and even improve it. Such optimizations blur the bound-
aries between global and detailed placement.
Next, we discuss locality, force orientation, and force
modulation. Density gradients in APlace [99] and NTU-
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE
Fig. 2. High-level flow of SimPL [103]. After initial wirelength-driven
placement, SimPL performs rounds of upper and lower bound global
placement iterations. The bottom graph depicts the progression
of the placement solution with respect to wirelength.
Place [39] are based on local information and, e.g., do not
account for possible paths around fixed obstacles. This may
require numerous global placement iterations. Kraftwerk
and mPL6 find density gradients by solving linear elliptic
PDEs as explained above, incorporating more global per-
spective into their density gradients. However, it remains
unclear how well this accounts for possible paths around
fixed obstacles. Whether gradients are calculated based on
local information or identify the globally best direction, the
scaling of density gradients for proper balance with
interconnect-based forces often remains unclear. To this
end, the work in [195] distinguishes the tasks of force
orientation and force modulation. It demonstrates that
force modulation in FastPlace can be improved by reducing
the magnitude of 10% strongest forces, as implemented in
RQL. These challenges are addressed in a more systematic
way in SimPL [103], [105] by lookahead legalization (LAL),
which globally identifies target locations for all cells so that
most overlaps are removed (Figs. 2 and 3).
D. Legalization and Detailed Placement
The cell locations from global placement may overlap,
and typically do not align with power rails. The global
placement must then be legalized, where all cell overlap is
removed without undermining design objectives. Legaliza-
tion removes all cell overlap while minimizing total cell
displacement, and is necessary not only after global place-
ment, but also after incremental changes, e.g., physical
synthesis optimizations [7]. Unlike cell spreading during
global placement, legalization is typically performed when
cells are both 1) well distributed over the entire region; and
2) have relatively small overlap. A legalized placement can
be improved with respect to a given objective by detailed
placement, e.g., swapping neighboring cells to reduce total
wirelength, or sliding cells to one side of the row when
1989
Markov et al.: Progress and Challenges in VLSI Placement Research
Fig. 3. Illustration of SimPL [103] during global placement. The
left-hand column depicts the lower bound placements attained at
individual iterations, while the right-hand column depicts the upper
bound placements. Each upper bound iterate is derived from the lower
bound iterate through lookahead legalization and is used to define
forces that enhance the legality of lower bound iterates with
minimal increase in wirelength.
unused space is available. Table 1 summarizes methods for
legalization and detailed placement.
Legalization algorithms can be classified as 1) local
approaches, where cells are moved one at a time or in small
groups; and 2) global strategies that relocate large groups of
cells. Some local legalizers, such as Tetris [73], greedily
assign each cell to its nearest legal location while respecting
row capacity. Abacus [180] also finds the best row the cell
belongs to, but uses dynamic programming to replace the
already placed cells such that the total displacement is
minimized. Ho and Liu [74] and Lee et al. [116] also ex-
plicitly minimize global wirelength during legalization.
Global strategies can be illustrated by the use of network
flows to find optimal solutions under mild assumptions.
Extensions include incorporating history [44] and modify-
ing path augmentation algorithms [12]. Additional techni-
ques are shown in Table 1.
1990 Proceedings of the IEEE | Vol. 103, No. 11, November 2015
Detailed placers preserve legality and often other de-
sign constraints, such as routing congestion or placement
density, while improving solutions by relocating movable
cells [108]. Branch-and-bound placers [24] reorder groups
of neighboring cells in a row by a sliding-window tech-
nique, where cells are reordered optimally inside each
window. However, this approach can handle typically up to
eight cells at a time. A more scalable optimization, handling
up to 20 cells at a time, splits the cells in a given window
into left and right halves, and optimally interleaves the two
groups while preserving the relative order of cells from
each group [85]. FastPlace-DP [149] improves wirelength
by swapping pairs of nonadjacent cells, and by cycling
triplets. When unused space is available between cells in a
row, these cells can be shifted to either side or to inter-
mediate locations. Wirelength-optimal locations in a given
row can be found by a polynomial-time algorithm [98],
which is practical in many applications. ECO-System [166],
integrated in Capo [24], [168], identifies areas where cells
need to be replaced, then applies Capo to perform both
legalization and detailed placement, simultaneously and
consistently in all such regions.
Modern circuit layout is experiencing an increasing
number of design constraints and objectives, as well as
design rules. Therefore, wirelength-optimized global place-
ment solutions must undergo numerous local transforma-
tions to generate layouts that optimize timing, routability,
and manufacturing yield (Sections VI and VIII). Such
transformations may adversely affect wirelength and
routing demand, which is why fast and effective wirelength
recovery is invoked periodically in practical physical-design
flows. While different from the traditional detailed place-
ment setting, this context leverages algorithmic techniques
developed for detailed placement. This was illustrated in
the 2013 International Conference on Computer-Aided
Design (ICCAD2013) detailed-placement contest [108]
TABLE 1 Legalization and Detailed Placement
 Markov et al.: Progress and Challenges in VLSI Placement Research
TABLE 2 Mixed-Size Placement Techniques
that focused on fast wirelength recovery subject to cell-
density constraints and maximum displacement limits. The
top three teams achieved very similar results, despite using
different algorithms. This may indicate that known
algorithms exhaust wirelength-driven detailed placement
and the extended formulation above. Two algorithms used
by top contestants, BraveDP and RippleDP, are described in
[47] and [156], respectively. BraveDP performs cell swap-
ping with lazy profit updates to reduce HPWL and density
peaks without violating displacement limits. RippleDP first
moves cells to their optimal HPWL regions subject to
displacement limits, and then locally improved locations by
inter-row moves, cell reordering, and compaction.
Challenges for legalization and detailed placement in-
clude incorporating additional geometric and performance
constraints, as well as various design objectives. For exam-
ple, legalization can simultaneously minimize wirelength
[74], [116] and improve routability [78]. Practical detailed
placers must incorporate timing optimization [196], de-
tailed routability [101], [199], as well as manufacturability
and yield optimization [112], [220]. Power minimization,
temperature gradient constraints, and new design rules for
sub-16-nm technology nodes pose additional challenges for
ASIC detailed placement.
In contrast, state-of-the-art FPGAs emphasize com-
pliance with highly structured programmable fabrics,
including carry chains, embedded arithmetic blocks, and
memories. Circuit timing for FPGAs is modeled nonconvex
discrete functions that reflect hierarchical ‘‘express wires’’
available at fixed locations throughout the chip.
II I. MIXED-SIZE PLACEMENT
The number of macros included in modern ICs is growing
[207] in response to technology and business trends. Find-
ing locations of larger circuit modules and placing standard
cells are essentially the same from an optimization view-
point, distinguished only by 1) the scale relative to the size
of layout regions; and 2) the shaping and rotations of
macros in floorplanning. Mixed-sized placement carefully
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE
combines floorplanning techniques, to pack (the relatively
few) large blocks, and placement techniques, to handle the
millions of small standard cells. Several available approaches
are summarized in Table 2 and illustrated in Fig. 4.
A. Simultaneous Flows
Simultaneous flows do not separate the placement of
standard cells and macros into separate stages. One method
to handle macros is to divide them into ‘‘shreds’’ comparable
in size to standard cells [2]. These shreds can be connected
by fake nets during wirelength optimization so as to keep
them close together [2], [17], e.g., when shaping soft blocks
[164]. In contrast, Kim and Markov [106] only shred macros
during geometric spreading. Other placement-based ap-
proaches explicitly shift macros or cells during placement
[39], [107], [197], or relegalize after every placement itera-
tion [27], [56]. Techniques that simultaneously move macros
and standard cells can be classified into force directed [62],
[197], nonconvex [27], [39], [76], min-cut [164], and flow
based [45]. However, many ideas are applicable in different
contexts. One strategy is to legalize and fix macros that are
comparable in size to the magnitude of cell displacements at
the current iteration [27], [167].
B. Sequential Flows
Sequential flows separate macro and standard-cell
placement. Some flows place all macros at once after tent-
atively placing the full netlist, and before standard-cell
placement, such as packing macros at the chip periphery of
[38]. Other approaches [2], [216] 1) cluster standard cells
into soft blocks; 2) use a floorplanner on the original
macros and new soft blocks; 3) dissolve soft blocks; and
4) place standard cells using established methods. Several
techniques [35], [38], [216] account for macro flipping
and rotation.
C. Postprocessing Placement Methods
Postprocessing placement methods remove overlap
between macros and standard cells by floorplan repair
1991
Markov et al.: Progress and Challenges in VLSI Placement Research

[139], detailed placement [17], [55], [181], and force-

directed techniques [62], [164].

I V. ROUTABILITY-DRIVEN PLACEMENT
With increasing design complexity, optimizing traditional
placement metrics is insufficient for successful routing
[8], [165]. To mitigate routing failures, routability-driven
placers incorporate route estimation as part of their flow.

A. Congestion Maps
Congestion maps indicate regions where routing will be
difficult, and are used to guide optimization during place-
ment. They are generated using: 1) static approaches,
where the congestion map is fixed for a placement instance;
2) probabilistic approaches, where net topologies are not
fixed, and probabilistically determined; and 3) constructive
approaches, where a simplified global router generates
approximate net routes (Fig. 5). Traditionally, the first two
options have been the most popular, but the last option has
been gaining traction due to advancements in global
routers, where they are designed to handle greater layout
complexity. Table 3 summarizes these approaches.

Fig. 4. Illustration of different techniques for simultaneously placing
large macro blocks (red outlines) and standard cells (blue). The top
image illustrates multilevel placement to spread standard cells
around macro blocks. The bottom image demonstrates the placement
of large macro blocks by representing each one as many smaller
standard-cell-sized blocks and maintaining tight bonds between the
smaller blocks.
B. Placement Optimizations
Placement optimizations are applied throughout the en-
tire placement flow: 1) during global placement; 2) modi-
fying intermediate solutions; 3) during legalization and
detailed placement; and 4) as a postplacement processing
step (Table 4). In global placers, the most popular techniques
are cell bloating and whitespace injection. Depending on the
placer type, e.g., quadratic and min-cut, the implementation
of these techniques will require placer modification,
including changing the optimization function. In detailed

Fig. 5. Illustration of congestion alleviation during global placement using SimPLR [104]. In the left panel, the cells (depicted in blue) are
tightly packed (right) with high areas of congestion shown in red and purple (left). In the middle panel, packing peanuts (right, depicted in red)
encourage cells to spread, thereby decreasing local cell density and reduce congestion (left). In the right panel, packing peanuts have
increased in size (left), and congestion has been substantially reduced (left).

1992 Proceedings of the IEEE | Vol. 103, No. 11, November 2015
 Markov et al.: Progress and Challenges in VLSI Placement Research
TABLE 3 Congestion Estimation for Placement
placers, the most popular techniques are cell swapping and
cell shifting. Additional optimizations can be applied to
intermediate (or near-final) placement solutions, and then
passed on to the next step of the design flow.
C. Contests
Researchers from IBM organized the 2011 International
Symposium on Physical Design (ISPD 2011) Routability-
driven Contest [192]. The benchmarks included between
483 000 and 1.29 million movable cells and a set of routing
constraints (e.g., blockages), such that many of them were
intentionally difficult to route. Placement solutions were
evaluated by running a global router and counting viola-
tions. The results indicate that routability can be improved
by increasing cell porosity. SimPLR [104] and Ripple [71]
used congestion maps to temporarily bloat cells, modulate
target aspect ratio of cell placement areas, and modify the
TABLE 4 Routability-Driven Placement
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE
anchor positions during quadratic placement. NTUPlace4
[78] uses smoothened congestion maps when modeling pin
density. To estimate congestion, SimPLR integrated a glo-
bal router [83], whereas Ripple and NTUPlace4 adopted
probabilistic congestion estimation [179]. The 2012 Design
Automation Conference (DAC 2012) [193] and ICCAD
2012 Contest Benchmarks [194] were easier to route and
emphasized the reduction of peak congestion. The evalua-
tion metric combined runtime and scaled HPWL. Since
then, further improvements [72], [84], [127] have followed.
V. TIMING- AND POWER-DRIVEN
PL ACEMENT
Timing-driven placement (TDP) seeks to optimize circuit
delay. TDP identifies critical nets using static timing
analysis (STA) [95, Sec. 8.2], and typically minimizes total
negative slack (TNS), worst negative slack (WNS), or both.
Table 5 outlines TDP; Fig. 6 illustrates the impact of net
weights on selected critical nets.
A. Net-Based Approaches
Net-based approaches optimize circuit delay by trans-
lating STA results and timing constraints into net weights
TABLE 5 Timing-Driven Placement Approaches
1993
Markov et al.: Progress and Challenges in VLSI Placement Research
Fig. 6. Illustration of modifying net weights to manipulate timing and wirelength. In the left panel, the highlighted net has no weighting,
and is given a high degree of freedom. As a higher net weight is applied to this net, the placer will restrict the net’s movement and reduce its
wirelength, as shown in subsequent panels. The higher the net weight, the more priority this net is given to reduce wirelength. However,
other (less critical) nets’ wirelength will be implicitly increased, as they may be moved to cater toward more critical nets.
and net constraints, respectively. A higher net weight en-
courages interconnect optimization to preferentially short-
en the net, whereas a net constraint limits net delay. Static
net weights remain constant during placement, and are
typically based on negative slack [20], [28], [61], [111] or
sensitivity [66], [163], [213], where placers attempt to pre-
dict the impact each net has on timing. A net weight that is
too high may shorten a net at the expense of upstream or
downstream nets, increasing circuit delay. To avoid this,
dynamic net weights are gradually updated based on slack
change [20], [160] or net criticality [62], [160]. While more
flexible, dynamic net weights may cause nets to oscillate
between critical and noncritical [54]. To dampen oscilla-
tions, net weights are accumulated based on histories, and
increased monotonically.
Net constraints limit net length, which linearly corre-
lates with the delays of buffered long wires [145], and do
not require as accurate timing predictions as net weights.
Common methods to generate delay budgets include the
zero-slack algorithm (ZSA) [95, Sec. 8.2.2], [126], [140]
and the iterative-minmax-PERT algorithm [219]. The usage
of net constraints is placer dependent. Min-cut placers [64]
modify cut costs, and analytic placers modify forces [159] or
Lagrange multipliers [188]. In detailed placement, net
constraints have also been integrated in cell movement
[86], primary objective functions [68], and as a separate
local-move step [45]. Net constraints are supported by dif-
ferential timing analysis [162], which generalizes incre-
mental STA [151].
B. Path-Based Approaches
Path-based approaches directly model timing on indi-
vidual critical paths, and explicitly ensure that each consid-
ered path meets timing constraints. These approaches
typically achieve better solutions than net-based ap-
proaches because of their global scope, but remain practical
for only a limited number of paths. To deal with numerous
critical paths in large designs, path-based approaches
1) embed a graph-based timing model; and 2) formulate a
1994 Proceedings of the IEEE | Vol. 103, No. 11, November 2015
mathematical program that maintains intermediate timing
variables. Auxiliary techniques, e.g., partitioning [89] and
Lagrangian relaxation [69], [182], can solve the program and
improve quality. Other approaches solve linear programs in
local regions [48] and use simulated annealing [183].
C. Compound Approaches
Compound approaches seek to combine the scalability
of net-based approaches and accuracy of path-based ap-
proaches. They can be illustrated by [130], which uses a
hybrid path-based delay sensitivity function for net weights
and minimizes critical nets’ wirelength.
D. IC Power Optimization
IC power optimization distinguishes dynamic power
from static power, which does not directly depend on cell
locations. With multiple voltages, static power can be re-
duced by changing voltage-island assignments. In contrast,
dynamic power depends on interconnect lengths, which
are determined by placement. To support higher clock
frequencies, modern designs are heavily pipelined, and re-
quire more capacitive clock networks, which can contrib-
ute 30% of total IC power [134]. To support design scaling
[88], placers must co-optimize 1) the hundreds of millions
of signal nets, each consuming a small amount of power;
and 2) clock networks with significant power consumption,
as illustrated in [42] and [115]. Table 6 outlines power-
driven placement; Fig. 7 illustrates placement optimization
within regions.
E. Static-Power Reduction
Static-power reduction techniques trade positive timing
slack for power. When multiple supply voltages are present,
cells can be moved closer to voltage sources in rows [218],
where cells are in interleaving (half) rows of high and low
VDD rows, and in regions [82], [113], [157], where cells are
powered by the closest voltage island. Other approaches
leverage cell hierarchy using clustering [124], and exploit
the locality of connections [158].
 Markov et al.: Progress and Challenges in VLSI Placement Research
TABLE 6 Power-Driven Placement Techniques
Fig. 7. Region-based optimization during placement. At the top,
marked cells are not constrained. At the bottom, the cells’ locations
are constrained to a small rectangle to shorten particular nets and
reduce delay and dynamic power.
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE
F. Dynamic-Power Reduction
Dynamic-power reduction can be accomplished by
1) reducing net activity; and 2) optimizing register loca-
tions and optimizing the clock tree. These classes are not
mutually exclusive. Clustering registers at the clock-tree
leaves facilitates inverter sharing [32], [92] and reduces
clock-tree capacitance [42], [115]. Such optimizations can
be performed using net weights based on activity factors
[42], [143], [171], [190]. Register placement is described
in [43], [115], [133], and [153], whereas clock-tree
synthesis is incorporated into global placement in [50],
[115], [153], [176], and [204]. In [115], this integration
reduces clock trees by 30% and total dynamic power of the
netlist and clock tree by 7%. Shen et al. [176] add clock-
gating logic, and further refine the tree with incremental
placement techniques. An IBM physical-synthesis flow that
accounts for gated clocks in high-performance ICs is
described in [153].
VI . PLACEMENT IN PHYSICAL
SYNTHES IS
Physical synthesis [7] modifies the netlist based on place-
ment information so as to 1) fix timing violations; and
2) optimize performance metrics. After a round of opti-
mizations, the design can be replaced to facilitate further
optimizations. Hence, the interaction between placement
algorithms and physical synthesis is crucial for timing
closure. Table 7 lists physical synthesis techniques that
heavily interact with placement.
A. Logic Transformations
Logic transformations [95, Sec. 8.5.3] such as cloning,
gate decomposition, and combinational restructuring
manipulate area-power-timing tradeoffs in combinational
circuits. Newly inserted gates must be given valid loca-
tions, which can make or break a given transformation
[60], as illustrated by 1) restructuring fanin trees [212] and
cones [208]; and 2) simulation-driven restructuring that
uses controllability and observability don’t-cares [155].
B. Interconnect Buffering
Interconnect buffering [121], [191] improves circuit
timing by speeding up signal transitions in long nets.
1995
Markov et al.: Progress and Challenges in VLSI Placement Research
TABLE 7 Placement-Aware Physical Synthesis
Approximately equal-spaced buffers break down timing-
critical nets into shorter segments. Due to technology scal-
ing, buffers comprise 10%–44% of standard-cell instances
in large designs [152]. As the final buffer requirement is
unknown in advance, placers reserve unused space (white-
space) throughout the layout [3]. Virtual buffering [152],
[174] assigns buffers to long interconnects without chang-
ing the netlist, but accounts for their impact on area and
timing. Porosity-aware buffer planning integrated in an
analytical-placement framework adds buffer density to the
objective function [36]. Porosity-aware Steiner trees place
buffers in available sites [5].
C. Gate Sizing
Gate sizing [81], [147] does not change connectivity but
impacts timing-power tradeoffs, facilitating other optimiza-
tions. Papa et al. [151] develop placement-aware branch-and-
bound search using a discrete cell library. Alternatively, gate
sizes can be extrapolated using continuous delay models
within performance-driven physical design [184], [198].
D. Physical Retiming
Physical retiming moves registers through combina-
tional logic in the netlist in order to ease timing constraints.
Despite numerous publications on retiming in the logic
domain, practical implementations must account for inter-
connect delay, and therefore gate locations and buffering.
A retiming-based physical-transformation system [150]
uses virtual buffering and exploits the interaction between
retiming, placement, and cloning in a unified mixed
integer-linear program.
E. Compound Optimizations
Compound optimizations perform sophisticated area-
timing-power tradeoffs along multiple design dimensions
while limiting design iterations and turnaround time. Logic
transformations, buffer insertions, and gate sizing may
require legalization and detailed placement. Additionally,
Li et al. [118] adjust floorplans to accommodate area
changes. Industrial physical-synthesis flows are reported in
[151], [153], [186], and [198].
1996 Proceedings of the IEEE | Vol. 103, No. 11, November 2015
VII. BENCHMARKING
INFRASTRUCTURE AND COM PARISONS
OF PLACEMENT ALGORITHMS
Benchmarking activities for research on placement algo-
rithms have a long tradition [1]. Key elements of bench-
marking infrastructure have been developed by the
placement research community over the last ten years:
• rigorous geometry and netlist descriptions;
• closed-form objective functions;
• community-shared file formats, based on the Book-
shelf format originally designed for the Capo
placer [23];
• a variety of circuit designs contributed by industry
(IBM Research and Mentor Graphics) for regular
research contests held at ISPD and ICCAD, avail-
able on respective conference websites.
This infrastructure made possible to measure and report
even fairly small improvements to placement algorithms,
which appear consistently over multiple benchmarks.
Moreover, such improvements typically survive in the in-
dustry environment and gradually add up. In our experience,
some algorithmic changes exhibited greater improvements
on proprietary designs than on public benchmarks.
A. Research Contests
The availability of a common data formats and industry
benchmarks enabled research contests, which typically give
graduate students several months to adapt their algorithms
to a new set of industry netlists, constraints, and objectives,
and develop high-performance optimizers. Such contests
were held regularly in the placement community since
ISPD 2005, and dozens groups built up extensive software
libraries. In the last ten years, these contests have spear-
headed and validated significant advances in placement
research. Starting from the pure-wirelength-driven for-
mulations in 2005, the contests broadened their interests
toward cell density [141], global routability [192]–[194],
detailed routability [21], [221], and timing [109]. The ISPD
2005 and 2006 contests on newly released large netlists
have confirmed that analytic global placers have matured to
the point where previously leading min-cut placers became
uncompetitive [141]. Subsequent contests were often domi-
nated by quadratic placers, which were faster than general
nonlinear optimization placers that produced better solu-
tions. Incorporating routability and runtime into the objec-
tives identified algorithmic frameworks that could be best
adapted to practical design flows. Contest organizers were
EDA professionals involved in placement R&D in the
industry, and this ensured prompt recognition of contest
results, employment opportunities for best performing
graduate students, and even commercialization of best ideas.
B. Comparisons Between Academic and Industry
Placement Tools
Historically, academic placement tools have been
closely related to their industrial counterparts. Many
 Markov et al.: Progress and Challenges in VLSI Placement Research
academic placers presaged industry placers, whereas
Nalyor’s patent [142] spearheaded nonquadratic academic
placer development (Fig. 1). Even so, direct comparisons
between academic and industry placers have been restrict-
ed by terms of specific license agreements, as well as
mismatches in data models and details of the larger chip
context. Recent research in [94] created a framework and
specific benchmarks that enable comprehensive ‘‘apples-to-
apples’’ assessments across commercial and academic tools
including placers, routers, and gate sizers. The results
suggest that state-of-the-art academic tools can outperform
industry tools on individual well-studied objectives, such as
wirelength (measured after placement) and overflow
(measured after routing), but are more likely to underper-
form in highly constrained multiobjective optimization.
This is to be expected, since comprehensive, customer-
focused software development is a lengthy and capital-
intensive process that does not reflect the goals of academic
research. Instead, academic tools focus on some aspects of
the placement process and often pursue the objectives
proposed in academic contests.
VIII . OPEN CHALLENGES
As modern ICs continue to grow [88], flat placement will
require new algorithms and data structures to support
physical design and physical synthesis with numerous
macros and multiple clock domains [9]. Most gate-level
techniques for 3-D placement remain impractical due to
high TSV costs [102].
A. Automatic Generation of Datapath Layout
Automatic generation of datapath layout currently
remains inferior to manual placement, but significant
improvements have been made in the last few years [46],
[205]. A key issue is whether general-purpose placement
approaches can be extended to handle datapath layouts as
successfully as unstructured layouts, or specialization is
required. Recent studies [205] suggest the latter, pointing
Fig. 8. Illustration of datapath optimization during global placement. The red or light lines (black or dark lines) show horizontal (vertical)
alignments. Techniques such as weighting (center) and fixed-point alignment (right) significantly improve datapath alignment.
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE
out that conventional optimization objectives optimized by
conventional placers have serious pitfalls in the case of
datapaths (Fig. 8). In particular, datapaths require more
accurate modeling of multipin nets and their routing. To
facilitate specialized datapath placement techniques, it is
important to identify datapath subcircuits and, after
placement is performed, integrate the results into a larger
layout. Specialized placement can also be viewed in terms
of componentsValignment of bit slices, careful spacing of
aligned groups, as well as structure-aware legalization
algorithms [46], [205] (Fig. 8). The least studied aspect of
such a design flow is the integration into a larger layout.
B. Layout-Friendly High-Level Synthesis
Layout-friendly high-level synthesis [52] promises
improvement in IC power and performance by invoking
physical optimization much earlier in the design flow. Such
operations require reasonably accurate modeling of key
design parameters, fast layout estimation, and powerful
high-level design transformations that would generate mul-
tiple configurations to choose from. Large datapaths offer
significant freedom for such transformations and algebraic
structure that facilitates high-level transformations. More-
over, datapaths arise as bottlenecks for power and perfor-
mance in mass-market IC designs and science-support
projects. Another key domain for layout-friendly high-level
synthesis is in tradeoffs between computation and commu-
nication. To this end, layout information is necessary to
determine 1) spatial resources available for compute mod-
ules; and 2) the cost of communication. Specialized bus
routing is necessary to determine appropriate serialization/
deserialization tradeoffs.
C. Integrated Timing and Power Optimizations
As timing-critical nets are typically identified by sign-
off quality timing engines after placement, significant
placement modification may be required in the presence of
a large number of near-timing critical nets. Removing all
slack violations on these critical nets during placement,
1997
Markov et al.: Progress and Challenges in VLSI Placement Research

however, can undermine placement quality, generate new
critical nets, and hamper timing closure. Moreover, as the
distance between metal layers (and neighboring nets) is
reduced, coupling delay further complicates timing analy-
sis, as it can now be induced by nets above and below in
addition to the parallel wires on the same layer. Further
challenges arise when integrating placement with clock-
network synthesis to address process variation, useful
skew, hold constraints, clock gating, and other low-power
optimizations. In particular, short-path (hold) constraints
pose surprisingly difficult challenges in commercial IC
designs, and inserting buffers to mitigate these problems
results in an expensive overhead for power and area. Clock
gating optimizations can yield major savings in power, but
also increase and complicate the connectivity of the
combined netlist containing signal and clock nets. A typical
netlist transformation in this context moves the gaters
further away from the clock source and clones them to
handle tree fanout.
E. Quantifying the Impact
Given the significant investment in placement algo-
rithms and tools, as well as the tangible progress achieved,
it is important to quantify their impact on the cost and
quality of ICs and semiconductor products. Experiments in
[169] show that more effective congestion-driven place-
ment facilitates die-size reductions, which translate into
lower manufacturing costs and higher profits. A variety of
cost functions and large-scale design-optimization effects
must be evaluated conclusively. Due to the significant
effort involved and the need for careful analysis of results,
EDA tool vendors prepare circuit designs that demonstrate
key layout issues, and then release these benchmarks to
universities as part of student contests. Top performers
then describe their techniques in scholarly publications.
This open-research environment has been instrumental in
advancing the state of the art in physical layout, with many
contests targeting global placement.

D. Lithography-Aware Physical Synthesis I X. CONCLUSION

Lithography-aware physical synthesis [146], [211] ena-
bles early manufacturability optimization by, e.g., con-
trolling wire density to enhance chemical–mechanical
polishing (CMP) [37] and improve timing yield [97]. Such
optimizations are numerous, and their significance de-
pends on the technology node. In particular, starting with
90–45-nm nodes global routers have to prevent excessive
wire density to minimize crosstalk and avoid pitfalls in
CMP. Since global placement holds significant influence
over global routing (and the two have been integrated),
wire density must be considered in global placement for
large ICs. Starting at 45 nm, forbidden pitches and other
lithography constraints required additional support.
Manufacturing yield optimization created a new situation
where many single violations of soft rules can be tolerated,
but their numbers must be kept low. More recently,
double- and triple-patterning required even more involved
support during place-and-route and standard-cell
synthesis.
Research in VLSI physical design advanced quickly in the last
30 years. The first ten years (and prior research) identified
well-defined optimization stages such as placement, routing,
and clock-tree synthesis, with established algorithms and
intuitions. The next ten years of research discovered algo-
rithms with increasing sophistication, better scalability, and
competitive quality of results. The last ten years saw an ex-
plosion of benchmarking activities and software-based con-
tests, which revealed significant room for improvement over
prior art. Additionally, isolated physical-design steps were
extended to multiobjective optimizations and coordinated
with other aspects of IC design, to serve the needs of design
flows focused on timing closure and manufacturing con-
cerns. Research on placement has been at the forefront of
these developments. It contributed profoundly to the intel-
lectual underpinnings of physical design and its performance
improvements in practice. Current commercial software
tools for IC design draw heavily upon academic research, and
further improvements are likely. h

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ABOUT THE AUTHORS
Igor L. Markov (Fellow, IEEE) received the Ph.D.
degree in computer science from the University
of California Los Angeles (UCLA), Los Angeles,
CA, USA.
He is a Professor of Electrical Engineering and
Computer Science at the University of Michigan,
Ann Arbor, MI, USA, currently on leave at Google.
He researches computers that make computers.
He has coauthored five books, four U.S. patents,
and over 200 refereed publications, some of
which were honored by the best-paper awards at the Design Automation
and Test in Europe Conference (DATE), the International Symposium on
Physical Design (ISPD), the International Conference on Computer-Aided
Design (ICCAD), and the IEEE Transactions on Computer-Aided Design
(TCAD). During the 2011 redesign of the ACM Computing Classification
System, he led the effort on the Hardware tree.
Prof. Markov is an Association for Computing Machinery (ACM)
Distinguished Scientist. He is the recipient of a DAC Fellowship, an ACM
SIGDA Outstanding New Faculty award, an NSF CAREER award, an IBM
Partnership Award, a Microsoft A. Richard Newton Breakthrough
Research Award, and the inaugural IEEE CEDA Early Career Award. He
has served on the Executive Board of ACM SIGDA and Editorial Boards of
several ACM and IEEE Transactions, Communications of the ACM and IEEE
Design & Test.
Jin Hu received the B.S. degrees in electrical and
computer engineering from Northwestern Univer-
sity, Evanston, IL, USA, in 2006 and the M.S.E. and
Ph.D. degrees from the University of Michigan, Ann
Arbor, MI, USA, in 2008 and 2012, respectively.
She is currently with IBM Corporation,
Hopewell Junction, NY, USA, in the EDA Depart-
ment working on timing modeling and statistical
analysis. Her research interests include physical
design, particularly in global routing and
routability-driven placement, as well as timing analysis and modeling.
Vol. 103, No. 11, November 2015 | Proceedings of the IEEE
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Dr. Hu won first place at the 2012 International Conference on
Computer-Aided Design (ICCAD 2012) Routability-driven Placement
Contest, and has been the organizer of the annual TAU Workshop Timing
Contest in 2014 and 2015, and the Co-Chair for the ICCAD 2014 and 2015
Timing-driven Placement Contests.
Myung-Chul Kim received the B.S. degree in
electronic and electrical engineering from the
Pohang University of Science and Technology
(POSTECH), Gyeongsangbuk-do, Korea, in 2006
and the M.S. and Ph.D. degrees in electrical
engineering from the University of Michigan, Ann
Arbor, MI, USA, in 2009 and 2012, respectively.
He is with IBM Corporation, Austin, TX, USA. His
research interests include VLSI physical-design
automation with emphasis on placement, clock-
ing, gate sizing, and timing analysis.
Dr. Kim is the recipient of the IEEE/ACM William J. McCalla Best Paper
Award at the 2010 International Conference on Computer-Aided Design
(ICCAD 2010) for his placement work. During his Ph.D., he won the ISPD
2010 clock-network synthesis contest and ICCAD 2012 Routability-driven
Placement Contest. He has served as a Topic Chair for physical design
problems at ICCAD contests from 2013 through 2015, and he has been a
Chair of ACM/SIGDA CADathlon programming contest since 2014.
2003