[2] A. B. A. Ghani, “The Study on the Effect of Soil Thermal Resistivity on the
Level of Partial Discharge in xlpe Underground Power Cable”, Master of
Engineering Thesis, University Tenaga Nasional, Malaysia; May 2002
[3] M.S. Chong, “Partial Discharge Mapping of Medium Voltage Cables – TNB’s
Experience”, CIRED 2001, 18-21 June 2001, Conference Publication No. 482
IEEE 2001
[6] G.C. Stone, and S.A. Boggs, “Propagation of Partial Discharge Pulses in
Shielded Power Cable”, Proceedings of Conference on Electrical Insulation &
Dielectric Phenomena, IEEE Publication 82CH1773-1, p.275, Oct 1982.
[11] International Standard IEC 60270:2000, “High voltage test technique – Partial
discharge measurements”.
228
[12] IEEE Standard 400, “IEEE Guide for Field Testing and Evaluation of the
Insulation of Shielded Power Cable System”, 2001
[13] R. Miller and I. A. Black, “Partial Discharge Measurement Over the Frequency
Range 0.1Hz to 50Hz”, IEEE Transaction on Electrical Insulation, Vol EI-12
No.3, June 1977
[14] H. Oetjen, “Principals and Field Experience with the 0.1Hz VLF Method
regarding the Test of Medium Voltage Distribution Cables”, Conference
Record of the 2004 International Symposium on Electrical Insulation,
Indianapolis, IN USA, 19-22 September 2004
[16] R. J. Van Brunt, “Physics and Chemistry of Partial Discharge and Corona –
Recent Advances and Future Challenges”, IEEE Transaction on Dielectrics and
Electrical Insulation; Vol.1 No.5, October 1994.
[21] F.H. Kreuger, M.G. Wezelenburg, A.G. Wiemer and W.A. Sonneveld, “Partial
Discharge Part XVIII: Errors in the Location of Partial Discharges in High
Voltage Solid Dielectric Cables”, IEEE Electrical Insulation Magazine, Vol.9,
No.6, Nov/Dec 1993
[24] M.S. Naidu and V. Kamaraju, “High Voltage Engineering”, 3 rd Edition, 2004,
McGraw Hill; ISBN 007-049464-9
229
[25] L. Niemeyer, “A Generalized Approach to Partial Discharge Modeling”, IEEE
Transaction on Dielectrics and Electrical Insulation, Vol.2, No.4, August 1995
[26] J.Y. Tian, “Partial Discharge Detection In Cable System”, PhD Thesis, April
2001, University of Southampton
[29] Y. Tian, P.L.L. Lewin and A.E Davies, “Acoustic Emission Techniques for
Partial Discharge Detection within Cable Insulation”, Dielectric Materials,
Measurements and Applications, Conference Publication No.473, IEEE 2000
[33] M.D Judd and O. Farish, “High Bandwidth Measurement of Partial Discharge
Current Pulses”, page 436-439; Conference Record of the 1998 IEEE
International Symposium on Electrical Insulation, Arlington, Virginia, USA,
June 7-10 1998.
[35] M.D Judd and O. Farish, “Transfer Functions for UHF Partial Discharge
Signals in GIS”, page 74-77 High Voltage Engineering Symposium, 22-27
August 1999, Conference Publication No.467, IEEE, 1999.
230
Antenna Model”, 10th International Symposium on High Voltage Engineering,
Montreal, Quebec, Canada, August 25-29,1997
[37] K. R. Sturley, “Radio Receiver Design; Part 1”, Chapman & Hall Ltd, 1965,
ASIN: B000H1P99E
[41] Michael Carl Gorven, “Design of a 3GSPS ADC board for the iBOB”, in
October 2007 Thesis of Bachelor of Science in Electrical and Computer
Engineering, University of Cape Town, 2007
[43] Brad Brannon and Allen Barlow Aperture Uncertainty and ADC System
Performance, 2006 URL http:
//www.analog.com/UploadedFiles/Application_Notes/49406491234250544717
5991257024546937062255921511183854180687755AN501_a.pdf.
[46] Walt Kester. Converting Oscillator Phase Noise to Time Jitter, 2005. URL
http://www.analog.com/en/content/0,2886,760%255F788%255F91502,00.
html.
231
[51] Walt Kester. Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so
You Don't Get Lost in the Noise Floor, Mar 2005. URL
http://www.analog.com/en/content/0,2886,760%255F788%255F91250%255F0
,00.html.
[52] Reference Board User’s Guide, ADC08(B)3000RB: 8-Bit, 3.0 GSPS, A/D
Converter with Xilinx Virtex 4 (XC4VLX15) FPGA
[53] Development Board User’s Guide, ADC083000DEV: 8-Bit, 3.0 GSPS, 1.9W
A/D Converter withXilinx Virtex 4 (XC4VLX15) FPGA
[55] National semiconductor, The sight and sound of information,” LVDS Owner’s
Including High Speed CML and Signal Conditioning” Fourth Edition 2008,
national.com/LVDS.
[56] Jon Brunetti, Brian Von Herzen, “The LVDS I/O Standard”, Application note:
Virtex E Family, Xilinx, XAPP230 (v1.1) November 16, 1999
[57] Jean P. Nicolle,” FPGA Introduction, What are FPGA?” April 30 th 2009, url://
www.KNJN.com and www.FPGA4FUN.com
[60] Peter J. Ashenden,” The Designer’s Guide to VHDL” Second Edition, Morgan
Kaufmann Publishers, 2004.
[61] A. Morgado, V.J. Rivas, R. del Rio, R. Castro-Lopez, F. Fernandez and J.M de
la Rosa, ”Behavioral Modeling, Simulation and Synthesis of Multi-standard
Wireless Receivers in MATLAB/SIMULINK” VLSI Journal 2008, Vol.41.
[62] User guide SEBAKMT LPD Monitor and User guide HVPD monitor.
232