CX880

CX880

CX880
6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

Project : MT6797 BPI, APC

REF_SCH TOP LEVEL eMMC MSDC0

MSDC0 / eMMC RXD ANT- HB
DRX
RF IQ RxD FEM
MSDC 4-bit RXD ANT - LB
BSI ctrl
MSDC1
Connectivity ANT Micro SD
+ hot-plug Main ANT - HB
PRX
CONN IQ
I/Q ABB
TX FEM Main ANT - LB
MT6631 CONN ctrl 26M_BB
CONN IF
TCXO CLK Ctrl
C VTCXO C
26M
26M_AUD
I2C 26M_NFC
I2C_0
Misc. I2C
SRCLKENA0
slave SRCLKENA0

MEMs & ALS/PS I2C

I2C_1

VGPU I2C-7

LCD
LCD IF
LCD
VGPU
module (MIPI DSI)
Camera IF VProc1/2 I2C-6
Camera
Camera
I2C 2 /3
(MIPI CSI) 2+2Phase Buck
Modules I2C_2 / 3
I2C
CTP I2C_4

I2C
32K_BB
MT6351
NFC

2+2PhaseBuck
I2C
I2C_5

I2C_6
MT6797 LDOs LDOs
RTC 32K

VIB
VGPU
I2C
I2C_7
(POP) Vibrator

Headset
GPIOs VMD/VMD1/ Bucks (HPL, HPR, AU_VIN1)
SPI_0 Receiver
VSRAM_MD/ Audio
SPI VDRAM//VCORE Speech AU_VIN0
Finger print SPI_1 AUD I/F
Audio I/F VPA/VS1/VS2
SPI SPI
eSE SPI_2 PWRAP I/F
GPIOs VSYS
SPI_3
I2C-0

SIM1 / 2
BC1.1 PWR THIRD-PARTY
SIM1 / 2 BC 1.1
SIM2
Buck-Boost LCM_AVDD/AVEE
Buck-Boost LCM Gate
Keypad Keypad Driver

I2S
Smart PA I2S0 / 3 BST_LX FLASH
B B
WLED BST Flash
GPIOs
I2S1 / 2
I2S
VSYS
Battery
VSYS Charger/
TDM
DPI SW
DPI

JTAG
USB 3.0 / 2.0 USB Type-C
Debug UART JTAG USB
port UART

A
猎人电子图 A

COMPANY:

TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 1OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

I2C Function I2C Spec.[1] Budgeted Timing I2C Slave Address (7-bit mode)

SW charger 400 Kbps bq25896 / SW charger I2C address: 0X6B (Write:0xD6, Read:0xD7)

LCM Gate Driver 400 Kbps NT50358 / LCM Gate Driver I2C address: 0X3E (Write:0x7C, Read:0x7D)

Buck-boost 400 Kbps FAN49101 / Buck-boost I2C address: 0X70 (Write:0xE0, Read:0xE1)

Flash LED Driver 400 Kbps LM3643 / Flash LED I2C address: 0X63 (Write:0xC6, Read:0xC7)
I2C-0
C *[2]
C
Speaker Amp. 400 Kbps MAX98926EWV+T / Speaker AMP I2C Address: 0x31 (Write:0x62, Read:0x63) when ADDR = GND.
MAX98926EWV+T / Speaker AMP I2C Address: 0x34 (Write:0x68, Read:0x69) when ADDR = VIO18.
FUSB302 / USB Type-C channel configure I2C Slave Address:0x22, write:0x44, read:0x45) or
USB Type-C CC 400 Kbps FUSB302 / USB Type-C channel configure I2C Slave Address:0x23, write:0x46, read:0x47)

MHL 400 Kbps SI8348 / CI2CA Low:MHL I2C Address =0x39/3D/4D/64/48/60.(Write:0x72/7A/9A/C8/92/C0, Read:0x73/7B/9B/C9/93/C1)

M Sensor 400 Kbps AK09912 / M-Sensor I2C Address 0x0C (Write: 0x18, Read: 0x19)

A+Gyro Sensor 400 Kbps Yes. ICM-20645 / A+Gyro I2C Address: 0x68 (Write:0xD0, Read:0xD1)

I2C-1 Baro Sensor 400 Kbps BMP280 / Baro I2C address: 0X77 (Write:0xEE, Read:0xEF)
*[2]
RGB / PS Sensor 400 Kbps CM36558 / ALPS + UV I2C address: 0X51 (Write:0xA2, Read:0xA3)

Humidity Sensor 400 Kbps HTS221 / Humidity I2C address: 0X5F (Write:0xBE, Read:0xBF)

Rear camera 400 Kbps Yes. OV23850 / Rear camera I2C address: 0X36 (Write:0x6C, Read:0x6D) if SID = low.
I2C-2 OV23850 / Rear camera I2C address: 0X10 (Write:0x20, Read:0x21) if SID = high.

Rear camera's AF 400 Kbps LC898212XD-SH / AF driver I2C address: 0X72 (Write:0xE4 Read:0xE5)

400 Kbps Yes.

S5K5E2 / Rear camera I2C address: 0X10 (Write:0x20, Read:0x21);
2nd front camera
It can be changed by register[7:1] of addr 0x0107.
I2C-3 (Fixed Focus)
Front camera 400 Kbps Yes. S5K3M2XXM3 / Front camera I2C address:0X2D (Write:0x5A, Read:0x5B);

Front camera's AF 400 Kbps Yes. DW9714A / AF driver I2C address: 0X0C (Write:0x18, Read:0x19)

I2C-4 CTP 400 Kbps Yes. GT1511 / CTP I2C address: 0X5D (Write:0xBA, Read:0xBB) or 0X14 (Write:0x28, Read:0x29)

I2C-5 NFC 1.3 Mbps Yes. MT6605 / NFC I2C address: 0X28 (Write:0x50, Read:0x51)

I2C-6 VPROC buck 3.4 Mbps Yes. MT6313 / 2+2Phase Buck I2C address: 0X6B (Write:0xD6, Read:0xD7)
B B
I2C-7 VGPU Buck 3.4 Mbps Yes. FAN53555 / Buck I2C address: 0X60 (Write:0xC0, Read:0xC1)

Note 1: I2C Spec. : Standard mode (100 kbps) and Fast mode (400 kbps), Fast mode Plus (1 Mbps) and High-speed mode (3.4 Mbps)

Note 2: For MEMs sensor/sensor hub application, these I2C slave devices must be connected to I2C0 or I2C-1.

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 2OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

Schematic design notice of "11_BB_POWER" page.

Note 11-1: Reserve 1uF capacitor in VCC18IO0 for MHL.

Note 11-2:
AVDD28_DAC (F1 ball) must be powered by
"VTCXO28_PMU".
Note 11-3:
Schematic design notice of "10_BB_POWER_1" page.

Note 10-1: The placement of power/de-coupling capacitors of

Note 10-2: DVDD18_MSDC0/1 &DVDD28_MSDC1should C
Note 11-4: be placed as close to its power ball as possible
Note 10-3: Differential pairs of buck's remote sense must be placed at PCB Analog GND that should be connected to main GND
Note 10-4: back side right beneath MT6797 chip. within 150mil.
directly.
Note 11-5:
Note 10-5: For PCB layout, the star connection should be implemented in Differential pair of VDRAM_PMU remote sense should
the MT6351's VIO18 output. be placed in the farest power plane from MT6351 point
of view.
The purpose of this symbol is used for including POP LPDDR3 in BOM. Note 11-6:
POP_DDR_ Connect AVDD33_USB_P1 to "VUSB33_PMU" for
U / H9CKNNNDATMRPR
USB application; Connect AVDD33_USB_P1 to
"VSIM1_PMU" for IC-USB / Samrt card application.

U301-F
U301-G
U301-E VIO18_PMU MT6797
DVDD_CORE MT6797
MT6797 DVDD_PROC2 MT6797-MVFPOP-950P
MT6797-MVFPOP-950P MT6797-MVFPOP-950P Note: 11-1

1.0uF
C301
PERI_D AVDD & MD_A
VCCK PROC 2 GND GND

C368
A9 AA2

22uF
DVDD18_IO0 AVDD18_MD 6mil VIO18_PMU
B32 DVSS DVSS V20 D1 DVDD18_IO0
G11 Y25

C370
DVDD_CORE DVDD_PROC2 C4 V21 C302 100nF 1.0uF

22uF
H9 Y27 DVSS DVSS
DVDD_CORE DVDD_PROC2 C9 V22
H10 AA19 DVSS DVSS

C369
DVDD_CORE DVDD_PROC2 C14 V23 A22 AB2

22uF
DVSS DVSS DVDD18_IO1 AVDD18_AP C315

1.0uF
H11 AA20 VIO18_PMU

C394
H21
DVDD_CORE DVDD_PROC2
AA21
C22 DVSS DVSS V24 Note: 11-2
DVDD_CORE DVDD_PROC2 D29 V25
H22 AA23 DVSS DVSS
C372 DVDD_CORE DVDD_PROC2 22uF C371 E24 V27 J34
H23 AA24 DVSS DVSS DVDD18_IO2
DVDD_CORE DVDD_PROC2 F2 V29
C 47uF/0603
H24
H25
DVDD_CORE
DVDD_CORE
DVDD_PROC2
DVDD_PROC2
AA25
AA27 Note: 10-1 DVDD_PROC2_PMIC_FB[7]
G21
G23
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
W15
W19
C303 100nF AL34 DVDD18_IO3 AVDD28_DAC F1
6mil VTCXO28_PMU C
H26 DVDD_CORE DVDD_PROC2 AA28 DVDD_PROC2_GND[7] H8 W21

C316
DVSS DVSS

100nF
C373 22uF J9 DVDD_CORE DVDD_PROC2 AA29 C304 100nF
H13 DVSS DVSS W23 AM1 DVDD18_IO4
J11 DVDD_CORE DVDD_PROC2 AB19
H15 DVSS DVSS W25 AC1 DVDD18_IO4
J22 DVDD_CORE DVDD_PROC2 AB23 NC/MMD/L8/4MIL NC/MMD/L8/4MIL
[6]DVDD_CORE_PMIC_FB H17 DVSS DVSS W26
J24 DVDD_CORE DVDD_PROC2 AB27
H19 DVSS DVSS W27
[6]DVDD_CORE_GND J26 DVDD_CORE DVDD_PROC2 AC19
C374 H32 DVSS DVSS W29 VIO18_PMU AC34 DVDD18_MSDC0 AVSS18_MD G3
K9 DVDD_CORE DVDD_PROC2 AC20
J8 DVSS DVSS Y9 AVSS18_MD H3
K22 DVDD_CORE DVDD_PROC2 AC21 C305 100nF
NC/MMD/L8/4MIL J10 DVSS DVSS Y11 AVSS18_MD J2
NC/MMD/L8/4MIL K24 DVDD_CORE DVDD_PROC2 AC23
J13 DVSS DVSS Y13 AVSS18_MD J3
K26 DVDD_CORE DVDD_PROC2 AC24 C306 100nF
C375 J15 DVSS DVSS Y15 AG33 DVDD18_MSDC1 AVSS18_MD K3
L9 DVDD_CORE DVDD_PROC2 AC25
J16 DVSS DVSS Y17 AVSS18_MD L4
M9 DVDD_CORE DVDD_PROC2 AC27
J17 Y26 M3
Note: 10-2 M22 DVDD_CORE DVDD_PROC2 AC28
J18
DVSS DVSS
Y28
AVSS18_MD
N3
M23 AC29 DVSS DVSS AVSS18_MD
DVDD_CORE DVDD_PROC2 C377 J19 Y29 AF34 P4

1.0uF
M24 AD19 DVSS DVSS VMC_PMU DVDD28_MSDC1 AVSS18_MD

C307
DVDD_CORE DVDD_PROC2 J20 Y32 R2
M25 AD23 DVSS DVSS AVSS18_MD
DVDD_CORE DVDD_PROC2 J21 AA8 R3
M26 AD27 DVSS DVSS AVSS18_MD
C350 100nF DVDD_CORE DVDD_PROC2 J23 AA9 T3
M27 AE19 DVSS DVSS AVSS18_MD
DVDD_CORE DVDD_PROC2 C376 J25 AA11 T4
M28 AE20 DVSS DVSS AVSS18_MD
C351 100nF DVDD_CORE DVDD_PROC2 J27 AA13 AJ33 U3
N22 AE21 DVSS DVSS VIO18_PMU DVDD18_SIM AVSS18_MD
DVDD_CORE DVDD_PROC2 K8 AA15 V2
N24 AE27 DVSS DVSS AVSS18_MD
C352 100nF
N26
DVDD_CORE DVDD_PROC2 K10 DVSS DVSS AA17 Note: 11-3 VSIM1_PMU AH33 DVDD28_SIM
DVDD_CORE DVDD_PROC1 K11 AA18
N28 DVSS DVSS
C353 100nF DVDD_CORE K12 AA22 AB3
P22 DVSS DVSS AVSS18_AP
C378

DVDD_CORE K13 AA26 AK33

22uF

P24 DVSS DVSS DVDD18_SIM2

C354 100nF DVDD_CORE K14 AB9
P26
C379 DVSS DVSS VIO18_PMU
DVDD_CORE K15 AB10 AK34
22uF

C355 100nF
P28 DVDD_CORE PROC 1 K21
DVSS
DVSS
DVSS
DVSS AB11
VSIM2_PMU DVDD28_SIM2
R16
C380

DVDD_CORE K23 AB12

22uF

DVSS DVSS
1.0uF

R17 AE23
C395

C356 100nF DVDD_CORE DVDD_PROC1 K25 AB13

R18 AE24 DVSS DVSS
DVDD_CORE DVDD_PROC1 K27 AB14
C357 100nF
R19 DVDD_CORE DVDD_PROC1 AE25 Note: 10-1 L2
DVSS DVSS
AB15
R20 AF23 C381 DVSS DVSS
T16
DVDD_CORE
DVDD_CORE
DVDD_PROC1
DVDD_PROC1 AG19 22uF
DVDD_PROC1_PMIC_FB[7]
L8 DVSS DVSS AB16 WBG PLL
C358 100nF L10 DVSS DVSS AB17
T18 DVDD_CORE DVDD_PROC1 AG20 DVDD_PROC1_GND[7] L15 DVSS DVSS AB18 VIO18_PMU A32 AVDD18_WBG AVDD18_MCU1PLLGP AE28
T20 DVDD_CORE DVDD_PROC1 AG21
C359 100nF L17 DVSS DVSS AB20 AVDD18_SYSPLLGP E33
T21 DVDD_CORE DVDD_PROC1 AG23
L19 DVSS DVSS AB21 AVDD18_MDPLLGP D3
T22 DVDD_CORE DVDD_PROC1 AG24 NC/MMD/L8/4MIL NC/MMD/L8/4MIL L21 AB22

C308

100nF
T23 AG25 DVSS DVSS
DVDD_CORE DVDD_PROC1 L22 AB24 B26 1.0uF
T24 AG27 DVSS DVSS AVSS18_WBG
DVDD_CORE DVDD_PROC1 C382 L23 AB25 B29
T25 AH19 DVSS DVSS AVSS18_WBG
DVDD_CORE DVDD_PROC1 L24 AB26 C24
T26 AH23 DVSS DVSS AVSS18_WBG C317
DVDD_CORE DVDD_PROC1 L25 AB28 C25
T27 AH27 DVSS DVSS AVSS18_WBG
DVDD_CORE DVDD_PROC1 L26 AB29 C26
T28 AJ19 DVSS DVSS AVSS18_WBG
[3,6]VSRAM_PROC_PMU DVDD_CORE DVDD_PROC1 C383 L27 AC3 C29 AF28
U16 AJ20 DVSS DVSS AVSS18_WBG AVSS18_MCU1PLLGP
DVDD_CORE DVDD_PROC1 M8 AC15 C30 D33
D301 U18 AJ21 DVSS DVSS AVSS18_WBG AVSS18_SYSPLLGP
DVDD_CORE DVDD_PROC1 M10 AC17 C31 C3
U20 AJ23 DVSS DVSS AVSS18_WBG AVSS18_MDPLLGP
DVDD_CORE DVDD_PROC1 M11 AC18 D25
U22 AJ24 DVSS DVSS AVSS18_WBG
DVDD_CORE DVDD_PROC1 C384 M13 AC22 D26
U24 AJ25 DVSS DVSS AVSS18_WBG
U26
DVDD_CORE DVDD_PROC1
AJ27
M15 DVSS DVSS AC26 D27 AVSS18_WBG Note: 11-4
DVDD_CORE DVDD_PROC1 M16 AD9 D28
U28 AJ28 DVSS DVSS AVSS18_WBG
DVDD_CORE DVDD_PROC1 M17 AD11 F25
V26 DVSS DVSS AVSS18_WBG
DVDD_CORE C385 M18 AD13 AE29
V28 DVSS DVSS MCU1PLLGP_TP
DVDD_CORE M19 AD18
W16 DVSS DVSS
DVDD_CORE M20 AD20 AF29
W17 DVDD_CORE GPU M21
DVSS
DVSS
DVSS
DVSS AD21
MCU1PLLGP_TN
W18 DVDD_CORE M32 DVSS DVSS AD22
W20 DVDD_CORE DVDD_GPU G12 DVDD_GPU N8 DVSS DVSS AD24
W22 DVDD_CORE DVDD_GPU G13
N9 DVSS DVSS AD25
W24 DVDD_CORE DVDD_GPU G14
N10 DVSS DVSS AD26
Y18 DVDD_CORE DVDD_GPU G15
N13 DVSS DVSS AD32
Y19 DVDD_CORE DVDD_GPU G17
22uF C387 N15 DVSS DVSS AE8
Y20 DVDD_CORE DVDD_GPU G18
N17 DVSS DVSS AE9
Y21 DVDD_CORE DVDD_GPU G19
N19 DVSS DVSS AE10
Y22 DVDD_CORE DVDD_GPU G20
N21 DVSS DVSS AE11
Y23 DVDD_CORE DVDD_GPU H12 22uF C388 VIO18_PMU
N23 DVSS DVSS AE12
Y24 DVDD_CORE DVDD_GPU H14
N25 DVSS DVSS AE13
AH11 DVDD_CORE DVDD_GPU H16
N27 DVSS DVSS AE14
AJ30 DVDD_CORE DVDD_GPU H18
P2 DVSS DVSS AE15
AK21 H20
DVDD_CORE DVDD_GPU
DVDD_GPU J12
P9 DVSS DVSS AE16 PERI_A / MIPI VDD1
P10 AE17
MD

C318

2.2uF
J14 DVSS DVSS
DVDD_GPU P11 AE18 AN19 C2

C319

2.2uF
K16 DVSS DVSS AVDD18_MIPITX0 VDD1
DVDD_GPU P12 AE22 VIO18_PMU AP17 D32
DVDD_MODEM AB8 K17 DVSS DVSS 6mil AVDD18_MIPITX1 VDD1
DVDD_MODEM DVDD_GPU P13 AE26 M34
AC8 K18 DVSS DVSS VDD1
C386

DVDD_MODEM DVDD_GPU P14 AF3 AN18 AH32

22uF

AC9 K19 DVSS DVSS AVSS18_MIPITX VDD1

DVDD_MODEM DVDD_GPU C389 P21 AF9 AP18 AN3
AC10 K20 DVSS DVSS AVSS18_MIPITX VDD1 100nF
DVDD_MODEM DVDD_GPU P23 AF11 AP12 C320
AC11 L11 DVSS DVSS VDD1 100nF
DVDD_MODEM DVDD_GPU P25 AF13 VIO18_PMU AP27 C321
[6] DVDD_MD_PMIC_FB AC12 L12 DVSS DVSS 1.0uF 6mil VDD1
DVDD_MODEM DVDD_GPU P27 AF15
[6]DVDD_MD_GND Note: 10-3 AC13 DVDD_MODEM DVDD_GPU L13
R14
DVSS DVSS
AF17 1.0uF
AD8 L14 DVSS DVSS
DVDD_MODEM DVDD_GPU C349 100nF R15 AF18 C309 B12
AD10 L16 DVSS DVSS AVDD18_CSI
DVDD_MODEM DVDD_GPU R21 AF19
B NC/MMD/L8/4MIL NC/MMD/L8/4MIL AD12
AF10
DVDD_MODEM
DVDD_MODEM
DVDD_GPU
DVDD_GPU
L18
L20
C348 100nF R22
R23
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
AF20
AF21
C310
B13
C15
AVSS18_CSI
AVSS18_CSI
B
1.0uF

AF12 M12
C360

DVDD_MODEM DVDD_GPU C347 100nF R24 AF22 C19 VDRAM_PMU

AF14 M14 DVSS DVSS AVSS18_CSI
DVDD_MODEM DVDD_GPU R25 AF24
DVSS DVSS
1.0uF

AF16 N11
C361

DVDD_MODEM DVDD_GPU C346 100nF R26 AF25 VUSB10_PMU

AG10 N12 DVSS DVSS 6mil
DVDD_MODEM DVDD_GPU R27 AF26
DVSS DVSS
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1.0uF

AG11 N14
C362

DVDD_MODEM DVDD_GPU R28 AF27

AG12 N16 DVSS DVSS C311
DVDD_MODEM DVDD_GPU T9 DVSS DVSS AG9 PERI_A / USB VDDQ
1.0uF

AG13 N18
C363

AG14
DVDD_MODEM DVDD_GPU
N20
T11 DVSS DVSS AG17
4.7uF
Note: 11-4
DVDD_MODEM DVDD_GPU T13 AG18 A6
AG15 P15 DVSS DVSS VDDQ
DVDD_MODEM DVDD_GPU T15 AG22 AP13 A11
AG16 P16 DVSS DVSS AVDD10_SSUSB VDDQ
DVDD_MODEM DVDD_GPU T17 AG26 A12
AH14 P17 DVSS DVSS VDDQ
DVDD_MODEM DVDD_GPU T19 AG29 AM12 A21
AH16 P18 DVSS DVSS VIO18_PMU 6mil AVDD18_SSUSB VDDQ
DVDD_MODEM DVDD_GPU
P19 VSRAM_PROC_PMU
T32 DVSS DVSS AH13 VDDQ C1 Note: 11-5
DVDD_GPU U9 AH15 AM8 C32
P20 DVSS DVSS AVDD18_USB VDDQ
DVDD_GPU U11 AH18 D30 VDRAM_PMIC_FB [6]
P8 DVSS DVSS VIO18 star VDDQ
DVDD_MD1 DVDD_MD1 U13 AH20 AM9 F34 DVDD_DRAM_GND [6]
R8 DVSS DVSS AVDD33_USB_P0 VDDQ
C345

connection
2.2uF

DVDD_MD1 U15 AH21 VUSB33_PMU L3

C390 22uF
R9 DVDD_MD1 SRAMs U17
DVSS
DVSS
DVSS
DVSS AH22 6mil AP9 AVDD33_USB_P1
VDDQ
VDDQ L34 NC/MMD/L8/4MIL NC/MMD/L8/4MIL
R10 DVDD_MD1 U19 DVSS DVSS AH24 VDDQ P3
R11 DVDD_MD1 DVDD_SRAM_CORE G10 6mil
C344 100nF U21 DVSS DVSS AH25 VDDQ R34
R12 DVDD_MD1 DVDD_SRAM_CORE G22
VIO18_PMU U23 DVSS DVSS AH26 AN13 AVSS10_SSUSB VDDQ Y34
R13 DVDD_MD1 DVDD_SRAM_CORE L28 1.0uF C324 100nF
U25 AH28 1.0uF 1.0uF AM10 AA1
[6]DVDD_MD1_PMIC_FB Note: 10-3 T8 DVDD_MD1 DVDD_SRAM_CORE U29
U27
DVSS DVSS
AJ18 Note: 11-6
AVSS33_USB VDDQ
AD34 C326 100nF
[6]DVDD_MD1_GND T10 DVSS DVSS VDDQ 100nF
DVDD_MD1 V3 AJ22 C314 AE1 C325
T12 DVDD_MD1 Note: 10-5 V8
DVSS DVSS
AJ26
C312 C313 VDDQ
AH34 C327 100nF
T14 W28 DVSS DVSS VDDQ 100nF
DVDD_MD1 DVDD_SRAM_PROC2 12mil V9 AL3 AL1 C328
U8 DVSS DVSS VDDQ 100nF
DVDD_MD1 V10 AL33 AP4 C335
U10 AG28 DVSS DVSS VDDQ 100nF
NC/MMD/L8/4MIL NC/MMD/L8/4MIL
U12
DVDD_MD1 DVDD_SRAM_PROC1 8mil V11 DVSS DVSS AM3 Note: 11-4 VDDQ AP6 C329
100nF
DVDD_MD1 V12 AM7 AP10 C334
U14 G16 DVSS DVSS VDDQ 100nF
DVDD_MD1 DVDD_SRAM_GPU 10mil V13 AM11 AP15 C330
W9 C342 DVSS DVSS VDDQ 100nF
DVDD_MD1 C343 V14 AM14 AP20 C333
Note: 10-4 W10 DVDD_MD1 C341
V15
DVSS DVSS
AM19
VDDQ
AP23 C331 100nF
W11 DVSS DVSS VDDQ 100nF
DVDD_MD1 1.0uF 1.0uF V16 AM22 AP28 C332
W12 DVSS DVSS VDDQ
DVDD_MD1 1.0uF V17 AM27
W13 DVSS DVSS C391
C364 100nF DVDD_MD1 V18 AM31
W14 DVSS DVSS
DVDD_MD1 V19
Y8 DVSS
C365 100nF DVDD_MD1
1.0uF

Y10 W8
C366

DVDD_MD1 DVDD_SRAM_MD DVDD_SRAM_MD

Y12 AF8 C392
C339

4.7uF

DVDD_MD1 DVDD_SRAM_MD C340

22uF Note: 10-4
1.0uF

Y14 AH12
C367

DVDD_MD1 DVDD_SRAM_MD
AA10 DVDD_MD1 DVDD_SRAM_MD AH17
AA12 DVDD_MD1 DVDD_SRAM_CORE_MD_PMIC_FB[6]
AA14 DVDD_MD1 [6]
DVDD_SRAM_CORE_MD_GND C393
AC14 DVDD_MD1 NC/MMD/L8/4MIL
AC16 NC/MMD/L8/4MIL
DVDD_MD1
[3,6] DVDD_SRAM_MD AD14 DVDD_MD1 DVDD_PSMCU AA16
C338 100nF
AD15 DVDD_MD1 DVDD_PSMCU Y16
D302 AD16 C337 100nF
DVDD_MD1
AD17 DVDD_MD1 C336 100nF

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 3OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

NC U301-A U301-B
TP18
MT6797 MT6797

MT6797-MVFPOP-950P MT6797-MVFPOP-950P
PMU_IF DRAM_IF SIM ABB_IF
AN28 ZQ AN11 R401 240R/1% AG30 AB6 RFIC_CLK_BB [9]
[6] SYSRSTB SYSRSTB ZQ0_A 0201 [17] SIM1_SCLK SIM1_SCLK MAIN_X26M_IN
AE33 R402 240R/1%
ZQ0_B 0201
[6,7] WATCHDOG AK27 WATCHDOG [17] SIM1_SIO AJ31 SIM1_SIO
AN10 R403 240R/1%
ZQ1_A 0201
AD33 R404 240R/1% AH30
ZQ1_B 0201 [17] SIM1_SRST SIM1_SRST
[6,7,9] SRCLKENA0 AL29 SRCLKENA0 MAIN_TX_BBIP L1 LTE_TX_BB_IP[9]
[17] INT_SIM1 W30 INT_SIM1 MAIN_TX_BBIN M1 LTE_TX_BB_IN[9]
[6] SRCLKENA1 AK28 SRCLKENA1
MAIN_TX_BBQP M2 LTE_TX_BB_QP[9]
[20] SRCLKENAI AK29 SRCLKENAI0 [17] SIM2_SCLK AH31 SIM2_SCLK MAIN_TX_BBQN N2 LTE_TX_BB_QN[9]
DVDD_CORE
AM29 SRCLKENAI1 [17] SIM2_SIO AK32 SIM2_SIO
MAIN_PRX1_BBIP G2 LTE_PRX_BB1_IP[9]
[17] SIM2_SRST AK31 SIM2_SRST MAIN_PRX1_BBIN H2 LTE_PRX_BB1_IN[9]
[6] RTC32K1V8 AM28 RTC32K_CK
C402 100nF Y30 J1
INT_SIM2 INT_SIM2 MAIN_PRX1_BBQP LTE_PRX_BB1_QP[9]
MAIN_PRX1_BBQN H1 LTE_PRX_BB1_QN[9]
[6] PWRAP_SPI0_CSN AN33 PWRAP_SPI0_CSN
AVDD08
AVDD08_RDDR_CA AN2 C403 100nF
BPI
[6] PWRAP_SPI0_CK AL32 PWRAP_SPI0_CK AVDD08_RDDR_CB C34
AM33 B2 C404 100nF AM5 J5
[6] PWRAP_SPI0_MO PWRAP_SPI0_MO AVDD08_RDDR_AB BPI_BUS23_DET1 MAIN_DRX1_BBIP LTE_DRX_BB1_IP [9]
AM34 PWRAP_SPI0_MI MAIN_DRX1_BBIN J4 LTE_DRX_BB1_IN [9]
[6] PWRAP_SPI0_MI
AM4 BPI_BUS22_DET0
MAIN_DRX1_BBQP K4 LTE_DRX_BB1_QP [9]
[6] AUD_CLK_MOSI AM32 AUD_CLK_MOSI AVSS08_RDDR_CA AM2 AG6 BPI_BUS21_SWP3 MAIN_DRX1_BBQN K5 LTE_DRX_BB1_QN[9]
[6] AUD_DAT_MOSI_1 AP32 AUD_DAT_MOSI AVSS08_RDDR_CB D34
[6] AUD_DAT_MISO_1 AN32 AUD_DAT_MISO AVSS08_RDDR_AB B3 AG5 BPI_BUS20_SWP2
MAIN_PRX2_BBIP V1 LTE_PRX_BB2_IP [9]
[6]VOW_CLK_MISO AN27 VOW_CLK_MISO AH6 BPI_BUS19_SWP1 MAIN_PRX2_BBIN U1 LTE_PRX_BB2_IN[9]
[6] ANC_DAT_MOSI AL27 ANC_DAT_MOSI VDRAM_PMU AJ6 T2
BPI_BUS18_SWP0 MAIN_PRX2_BBQP LTE_PRX_BB2_QP[9]
MAIN_PRX2_BBQN U2 LTE_PRX_BB2_QN[9]
AVDD15
C [18] LCM_PWM AN6 DISP_PWM
AVDD15_BRDDR_CB J28
AN4 BPI_BUS17_VM1 C
AVDD15_BRDDR_CB K28 AL2 BPI_BUS16_VM0
AVDD15_ARDDR_B02 H27 MAIN_DRX2_BBIP V6 LTE_DRX_BB2_IP [9]
AVDD15_ARDDR_B02 H28 [11] BPI_BUS15 AL4 BPI_BUS15_ANT3 MAIN_DRX2_BBIN V5 LTE_DRX_BB2_IN [9]

AVDD15_ARDDR_CA AH9 BPI_BUS14 AK4 BPI_BUS14_ANT2 MAIN_DRX2_BBQP U6 LTE_DRX_BB2_QP [9]

AVDD15_ARDDR_CA AH10 MAIN_DRX2_BBQN U5 LTE_DRX_BB2_QN [9]
AVDD15_BRDDR_B13 AG8 [11] BPI_BUS13 AK3 BPI_BUS13_ANT1
AVDD15_BRDDR_B13 AH8 3.3nF 3.3nF

100nF
AK1 R5 LTE_DET_BB_IP[9]

C406
[8] BPI_BUS12 BPI_BUS12_ANT0 DPDADC_IP

100nF

C408
DPDADC_IN R4 LTE_DET_BB_IN[9]
C405 C407 [8] BPI_BUS11 AK2 BPI_BUS11
DPDADC_QP R1 LTE_DET_BB_QP[9]
[8] BPI_BUS10 AK5 BPI_BUS10 DPDADC_QN P1 LTE_DET_BB_QN[9]
AVDD15_BRDDR_B02 H7
AVDD15_BRDDR_B02 G7 [8] BPI_BUS9 AJ3 BPI_BUS9
Digital Pre-distortion Detection (DPD)
G8 100nF
AVDD15_ARDDR_B13

3.3nF
G9 AJ4

C410
AVDD15_ARDDR_B13 BPI_BUS16 BPI_BUS8
VIO18_PMU C409
BPI_BUS7 AJ5 BPI_BUS7

JTAG AVDD18
C411 100nF [12] BPI_BUS6 AH1 BPI_BUS6 MAIN_RX_REF K2 R406
0201
NC
AVDD18_RDDR_CA AK6
TP9 TP8 TP7 TP6 TP5

E9 F28 C413 100nF [12] BPI_BUS5 AH3

NC NC NC NC NC

JTRST_B AVDD18_RDDR_CB C412 100nF BPI_BUS5

AVDD18_RDDR_AB F7
E10 [12] BPI_BUS4 AH5
JTCK BPI_BUS4
RFIC_ET_P M4
D11 JTDO [12] BPI_BUS3 AB4 BPI_BUS3 RFIC_ET_N N4

D10 JTDI
Note: 12-1 [12] BPI_BUS2 AC4 BPI_BUS2
VREF
E11 JTMS VREF(CA) AN14 [12] BPI_BUS1 AD4 BPI_BUS1
APC1 G6 APC1[11]
VREF(CA) AA34 [12] BPI_BUS0 AC2 BPI_BUS0

VREF(DQ) B22
MISC MIPI RFIC BSI
VREF(DQ) Y1

[11] MIPI0_SCLK AG3 MISC_MIPI_CK_0 RFIC0_BSI_CK AE2 RFIC0_BSI_CK[9]

AG4 AD2

100nF

C414

100nF
RFIC0_BSI_EN[9]

C417
[11] MIPI0_SDATA MISC_MIPI_DO_0 RFIC0_BSI_EN

100nF

C416
100nF

C415
RFIC0_BSI_D2 AD5 RFIC0_BSI_D2 [9]
Misc Impedance cal.
[10] MIPI1_SCLK AG2 MISC_MIPI_CK_1 RFIC0_BSI_D1 AE5 RFIC0_BSI_D1 [9]
VEFUSE_PMU D31 FSOURCE_P
[10] MIPI1_SDATA AH2 MISC_MIPI_DO_1 RFIC0_BSI_D0 AF4 RFIC0_BSI_D0 [9]
1.0uF AL5 TESTMODE
C401
RTP_AB A2 AUX IN
B1 AF6
RTN_AB MISC_MIPI_CK_2 Note: 12-4
AF5 MISC_MIPI_DO_2 AUXIN4 W3
W4 ID0 [18]
Note: 12-3 NC Note: 12-2 AUXIN3
AUXIN2 Y4 AUX_IN2_BATID [6]
RTN_CB B34 AUXIN1 Y5 AUX_IN1_NTC [10]
A1 NC AF2 MISC_MIPI_CK_3 AUXIN0 AA5 AUX_IN0_NTC [19]
A34 NC 1.0uF 1.0uF 1.0uF
AN34 AF1 1.0uF
NC MISC_MIPI_DO_3
AP1 NC RTP_CA AP3
AP2 AN1 C418 C419 C422 C420
NC RTN_CA
AP33 NC
40.2R/1%

AP34 REF POWER

0201
R405

NC
A33 NC
REFP W2
AVSS_REFN Y2
Note: 12-5

100nF

C421
Close to BB IC.

B B

Schematic design notice of "11_BB_11" page.

Note 12-1: The DRAM's VREF(CA)(AA34 ball) must connect to VREF(DQ)(B22 ball).

Note 12-2: The de-coupling cap. of DRAM VREF have to be placed as close to BB as possible.

Note 12-3: Apply 1.8V to FSOURCE_P (D31) for eFuse programming.

Note 12-4: To shunt a 1uF capacitor in the AUXIN ADC input to prevent noise coupling. It should be placed as close to BB as possible.
Connect the unused AUX ADC input to GND.

Note 12-5: For impedance calibration of DDRPHY

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 4OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

U301-C U301-D

MT6797 MT6797
MT6797-MVFPOP-950P MT6797-MVFPOP-950P
CSI-0 DSI-0 USB MSDCs
[18] RDP2 E15 RDP2 TDP0 AL19 TDP0 [18] SSUSB_TXP AL11 SSUSB_TXP MSDC0_RSTB AD30 MSDC0_RST_[13]
D15 D2 AL20 SSUSB_TXN AK11
[18]RDN2 RDN2 TDN0 TDN0[18] SSUSB_TXN
MSDC0_CMD AC30 MSDC0_CMD[13]
[18] RDP0 D17 RDP0 TDP1 AL21 TDP1 [18] SSUSB_RXP AL13 SSUSB_RXP
E17 D0 AL22 AM13 AC33 MSDC0_CLK [13]
[18] RDN0 RDN0 TDN1 TDN1 [18] SSUSB_RXN SSUSB_RXN MSDC0_CLK
MSDC0_DSL AB30
MSDC0_DSL [13]
[18] RCP C16 RCP TCP AM21 TCP [18]
[18] RCN D16 C AM20 Y31 MSDC0_DAT7
RCN TCN TCN[18] MSDC0_DAT7
[8]USB_DP_P0 AK8 USB_DP_P0 MSDC0_DAT6 AA31 MSDC0_DAT6
[18] RDP1 B15 RDP1 TDP2 AN22 TDP2[18] [8] USB_DM_P0 AK9 USB_DM_P0 MSDC0_DAT5 AB31 MSDC0_DAT5
B16 D1 AP22 AB32 MSDC0_DAT4
[18] RDN1 RDN1 TDN2 TDN2[18] MSDC0_DAT4
MSDC0_DAT3 AB33 MSDC0_DAT3
[18] RDP3 A14 RDP3 TDP3 AN20 TDP3[18] MSDC0_DAT2 W33 MSDC0_DAT2
B14 D3 AN21 AN7 Y33 MSDC0_DAT1
[18] RDN3 RDN3 TDN3 TDN3[18] USB_DP_P1 MSDC0_DAT1
AP7 USB_DM_P1 MSDC0_DAT0 AA33 MSDC0_DAT0

MSDC1_CMD AF31 MSDC1_CMD[17]

CSI-1 DSI-1 AN12 SSUSB_VRT MSDC1_CLK AF33
MSDC1_CLK [17]
B19 RDP2_A TDP0_A AL18 MSDC1_DAT3 AF32 MSDC1_DAT3
A19 D2 D0 AM18 AF30 MSDC1_DAT2

R505
RDN2_A TDN0_A MSDC1_DAT2

0201
5.1K
MSDC1_DAT1 AD31 MSDC1_DAT1
D18 AN16 AL6 AE31 MSDC1_DAT0
C [18] RDP0_A
[18] RDN0_A D19
RDP0_A
RDN0_A
D0 C
TDP1_A
TDN1_A AN15 Note: 13-1 [8] USB_ID IDDIG MSDC1_DAT0
C
[18]RCP_A B20 RCP_A TCP_A AM16 AK26 DRVBUS
[18] RCN_A B21 C D1 AM17
RCN_A TCN_A

[18] RDP1_A E18 RDP1_A

D1 D0
TDP2_A AL15
[8]DRV_VBUS
BC CONN_IF
[18] RDN1_A E19 RDN1_A TDN2_A AM15

D20 RDP3_A TDP3_A AL16 [6] CHD_DP_P0 AN8 CHD_DP_P0 XIN_WBG F26 CONN_XO_IN_BB [14]
C20 D3 C AL17
RDN3_A TDN3_A
[6] CHD_DM_P0 AN9 CHD_DM_P0
E21 RDP1_C GPS_IP B25 GPS_RX_IP [14]
D21 RDN1_C x D1 GPS_IN A25 GPS_RX_IN [14]
KEYPAD
AL7 A24
Note: 13-2 CSI-2
LCM_RST LCM_RST [18]
[18] LCM_ENN G30 KPROW2
GPS_QP
GPS_QN B24
GPS_RX_QP [14]
GPS_RX_QN [14]
DSI_TE AN5 DSI_TE [18] GPIO107_TOUCH_EN G29 KPROW1
RDP0_B C17 RDP0_B [17] KPROW0 F29 KPROW0 BT_IP C28 BT_IP [14]
C18 D0 R502 C27
RDN0_B RDN0_B BT_IN BT_IN [14]
1.5K/1% [7] GPIO111 F33 KPCOL2
RCP_B A16 RCP_B VRT AN23 0201 [7] GPIO110 F31 KPCOL1 BT_QP A27 BT_QP [14]
RCN_B A17 RCN_B
C [17] KPCOL0 F32 KPCOL0 BT_QN B27 BT_QN [14]
VRT_A AN17 0201
RDP1_B B18 RDP1_B R503 WF_IP B31 WF_IP [14]
B17 D1 B30
RDN1_B RDN1_B 1.5K/1% WF_IN WF_IN [14]

R506 WF_QP A30 WF_QP [14]

VIO18_PMU R507 0201
4.7K/1% I2C WF_QN A29 WF_QN [14]
0201
DPI [7,8,18] SCL0 4.7K/1%
F30 SCL0
[7,8,18] SDA0 E30 SDA0 CONN_TOP_CLK D24 CONN_TOP_CLK[14]
CAM_CLK2 E14 E8 GPIO51
CAM_CLK2 DPI_DE
VIO18_PMU R508 4.7K/1% D23
0201 CONN_TOP_DATA CONN_TOP_DATA[14]
[18] CAM_CLK1 E13 CAM_CLK1 DPI_CK D9 GPIO52_BOARD_ID0[19] 0201 4.7K/1%
R509
[6,19] SCL1 AN31 SCL1 CONN_BT_CLK B33 BT_CLK [14]
[18] CAM_CLK0 E12 CAM_CLK0 DPI_HSYNC A8 GPIO53_BOARD_ID1[19] [6,19] SDA1 AN30 SDA1
CONN_BT_DATA C33 BT_DATA[14]
B8 VIO18_PMU R510 4.7K/1%
DPI_VSYNC GPIO54_LCM_EN2 0201
CONN_WF_CTRL2 E28
R511 0201 4.7K/1% WF_CTRL2 [14]
[18] MCAM_SCL2 B10 SCL2
D14 B9 (For Camera) E27
CAM_RST2 CAM_RST2 [18] MCAM_SDA2 SDA2 CONN_WF_CTRL1 WF_CTRL1[14]
C8 GPIO50_RST [18]
DPI_D11
D12 VIO18_PMU R512 4.7K/1% E29
[18] CAM_RST1 CAM_RST1 0201 CONN_WF_CTRL0 WF_CTRL0[14]
DPI_D10 E7 GPIO49_MOTOR_PWM 0201 4.7K/1%
C12 R513 F4 C23
[18] CAM_RST0 CAM_RST0 [18] MCAM_SCL3 SCL3 CONN_WB_PTA CONN_WB_PTA[14]
C7 GPIO48 G4 (For Camera)
DPI_D9 [18] MCAM_SDA3 SDA3
CONN_HRST_B D22 CONN_RSTB[14]
C6 R514 4.7K/1%
DPI_D8 GPIO47_FUEL_SCL4 VIO18_PMU 0201
R515 0201 4.7K/1%
CAM_PDN2 D13 CAM_PDN2 DPI_D7 D7 GPIO46_FUEL_SDA4 [8] TP_SCL4 M31 SCL4 (For CTP)
GPIO
[8] TP_SDA4 L31 SDA4
C11 D6 GPIO45_LCM_EN
[18] CAM_PDN1 CAM_PDN1 DPI_D6
VIO18_PMU R516 4.7K/1% V33
0201 EINT16 EINT16_NFC_IRQ[20]
B11 CAM_PDN0 DPI_D5 B6 GPIO44_TP_RST 0201 4.7K/1%
CAM_PDN0 R517
[20] SCL5 N33 SCL5 EINT15 K30 EINT15_HS_DET [16]
B5 GPIO143_FP_RST [19] [20] SDA5 M33 (For NFC)
DPI_D4 SDA5
EINT14 J30 EINT14_HALL1 [8]
D5 VIO18_PMU R518 1K
DPI_D3 NFC_SE_RESET [20] 0201
J33
C5 R519 0201 1K AP30
EINT13 EINT13_HALL2 [8]
DPI_D2 GPIO41_NFC_1.8V_EN [20] [7] SCL6 SCL6
AM30 (For AP PMU) H29
[7] SDA6 SDA6 EINT12 NFC_SE_IRQ [20]
DPI_D1 A4 NFC_SE_EN [20]
VIO18_PMU R520 1K H30
0201 EINT11 ALSP_INT_EINT11 [19]
DPI_D0 B4 DWL_REQ [20] 0201 1K
R521 AL31 H34
[7] SCL7 SCL7 EINT10 EINT10 [18]
AK30 (For GPU PMU)
[7] SDA7 SDA7
Note: 13-3 SPI I2S EINT9 AK22 EINT9_FP_INT [19]
R501 P34 E5 AK23
[8] GPIO252_KEYPAD
0201 R30
SPI3_CK
SPI3_MI
TDM_MCK GPIO137_FLASH_EN [18]
Note: 13-4 EINT8 TP_EINT8 [8]

GPIO251 P31 SPI3_MO TDM_BCK F5 GPIO136_NFC_IRQ EINT7 AK24 EINT7_TP_RST [8]

[18] CAM_AVDD_EN
4.7K/1% P32 SPI3_CS UART
TDM_LRCK E6 GPIO135_IR_PWM0 [19] EINT6 AL24

TP2 TP1
INT_TCARD [17]
AM26

NC NC
URXD1
TDM TDM_DATA3 D4 GPIO141 [14] EINT5 AM24 EINT5 [8]
AM25 UTXD1
[20] SPI2_CK P33 SPI2_CK TDM_DATA2 E4 GPIO140_FLASH_CE [18] EINT4 AN24 EINT4
[20] SPI2_MI P30 SPI2_MI

TP4 TP3
NC NC
[20] SPI2_MO N30 SPI2_MO TDM_DATA1 E3 FP_LDO_EN [19] D2 URXD0 EINT3 AK25 MAG_RST_EINT3 [19]
[20] SPI2_CS M30 SPI2_CS
TDM_DATA0 F3 GPIO138_DSEL_EN A3 UTXD0 EINT2 AL25 GYRO_EINT2 [19]

B I2S1_MCK T30 GPIO254[8] EINT1 AN25 ACCL_EINT1[19] B

[19] FP_SPI1_CK L30 SPI1_CK I2S1_BCK T33 EINT0 AP25 EINT0 [7]
[19] SP_SPI1_MI K31 SPI1_MI
[19] FP_SPI1_MO K32 SPI1_MO I2S1_LRCK R33
[19] FP_SPI1_CS L33 SPI1_CS
T31
I2S2_DI Note: 13-5
I2S1_DO U31

[18] SUB_VCAMA_EN H31 SPI0_CK I2S0_MCK V31 GPIO71_SPK_EN [16]

H33

4.7K/1%
[8]

R504
GPIO58_CTP_PWREN SPI0_MI

0201
[20] GPIO59 G33 SPI0_MO I2S0_BCK V30 I2S0_BCK
G31 SPI0_CS
[18] GPIO60_FLASH_TX V32
I2S0_LRCK I2S0_LRCK

I2S0_DI V34 I2S0_DI

I2S3_DO U34 I2S3_DO

AUD_INTN U33 GPIO255_TORCH_EN[18]

AUD_PDN K33 GPIO256

Schematic design notice of "12_BB_2" page.

Note 13-1: Default resistor of "SSUSB_VRT" can be NC if internal USB VRT is applied.

Note 13-2: Connect the the NC pins of CSI to GND

Note 13-3: The GPIO250 can't have external pull-up. "C2K DROP_ZONE" output indicator is
not allow to have external pull-up.
Note 13-4: The I/O type of I2C6/7 is push-pull;
External pull-up is required if I2C6/7 slave devices can only support open-drain.
Note 13-5: The GPIO249 features I/O trap in system
bootup that must be pulled down.

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 5OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

U601-A
MT6351
CONTROL SIGNAL BUCK OUTPUT
[17]PWRKEY T16 PWRKEY

[4] SYSRSTB T13 RESETB

[7] EXT_PMIC_EN R14 EXT_PMIC_EN

P12 NC
D [4,7] WATCHDOG
N7 WDTRSTB_IN D
R603 200K R15
0201 UVLO_VTH
P9 FSOURCE
L601
A17 A2 50mil 30mil

[4,7,9] SRCLKENA0 N6
PMU_TEST_MODE

SRCLKEN_IN0
VMODEM
VMODEM B2 0.47 uH/2016
DVDD_MODEM
VMODEM:0.5V~1.4V/1.2A
[4] SRCLKENA1 P6 SRCLKEN_IN1 VMODEM_FB C1 DVDD_MD_PMIC_FB [3]
GND_VMODEM_FB B1 DVDD_MD_GND [3]
R10 SPI_CSN L602
[4]PWRAP_SPI0_CSN 75mil 75mil
A12
[4] PWRAP_SPI0_CK R9 SPI_CLK
VGPU
VGPU B12 0.47 uH/2016
R605 0R
BOM R605=0R R606 NC ;·ÂÕæ R605=NC R606 OR
VDRAM_PMU
VGPU (to VDRAM):0.5V~1.4V/3A
0201 VIO18_PMU [3,4,5,6,7,8,9,10,13,16,18,19,20]
[4] PWRAP_SPI0_MO L8 SPI_MOSI
E14 R606 NC VDRAM_PMIC_FB [3]
VGPU_FB 0201
[4]PWRAP_SPI0_MI P8 SPI_MISO GND_VGPU_FB D14 DVDD_DRAM_GND [3]
L603
AUX ADC A7 75mil 75mil
VA18 VCORE
VCORE
VCORE
B7
B8
0.47 uH/2016
DVDD_CORE
VCORE:0.5V~1.4V/3A
C602 100nF U5 AVDD18_AUXADC
3 mil VCORE_FB E4 DVDD_CORE_PMIC_FB [3]
R5 AVSS18_AUXADC GND_VCORE_FB E5 DVDD_CORE_GND [3]
15 mil
L604
B5 30mil 30mil
T5 AUXADC_VIN
VMD1
0.47 uH/2016
DVDD_MD1
VMD1:1V/1.2A
VBAT INPUT
VMD1_FB E3 DVDD_MD1_PMIC_FB [3]
GND_VMD1_FB D3 DVDD_MD1_GND [3]
L605
B3 30mil 30mil
VSYS
25mil A1 VBAT_VMODEM
VSRAM_MD
0.47 uH/2016
DVDD_SRAM_MD
VSRAM_MD:0.8V~0.9V/1.2A
50mil B11 VBAT_VGPU
A11 VBAT_VGPU VSRAM_MD_FB D2 DVDD_SRAM_CORE_MD_PMIC_FB [3]
50mil B6 D1
D601

VBAT_VCORE GND_VSRAM_MD_FB DVDD_SRAM_CORE_MD_GND [3] 50mil

A6
20mil
20mil
A4
A3
VBAT_VCORE
VBAT_VMD1
VBAT_VSRAM_MD VS1 B10 50mil
L606
VS1_PMU
VS1:2V/2A
SOD123 45mil B9 VBAT_VS1 VS1 A10 0.47 uH/2016 C623
A9 VBAT_VS1
500mW 30mil
30mil
A14 VBAT_VS2 VS1_FB C15
40mil
G1
0201
4mil A15
VBAT_VPA
VBAT_BUCK_CTRL1
A13 40mil
L607
C624
VS2_PMU
VS2:1.4V/2A
1R 1.0uF VS2
B13 0.47 uH/2016
R604 VS2
C603 25mil U6 B15
25mil VBAT_LDOS1 VS2_FB >=30mil
P15 VBAT_LDOS2 VPA_PMU

VBUCK_BOOST
25mil
25mil
H13
H17
VBAT_LDOS3
VBAT_LDOS4 VPA F2 30mil
L608
C625
VPA:0.5V~3.4V/800mA
2.2 uH/2016
VPA_FB E1
C16 E2 1.0uF
25mil AVDD14_SLDO1 GND_VPA_FB
VS2_PMU C17 AVDD14_SLDO1
25mil E16 SLDO INPUT
25mil AVDD14_SLDO2 25mil
D16 AVDD14_SLDO3 AVDD20_SLDO1 L17 VS1_PMU
VS1_PMU
K15 25mil
DIG Power AVDD20_SLDO2
C626 C627
10mil U9
VIO18_PMU L/W:2800mil/8mil DVDD18_IO
DVDD18_DIG T10 DVDD18_DIG 2.2uF 2.2uF
T9 DVSS18_IO LDO OUTPUT
VREF T6 L/W:2800mil/6mil
VTCXO28

C620
100nF
12mil L/W:2800mil/6mil VTCXO28_PMU
U14 VREF VTCXO24 R6 VTCXO24_PMU
1.0uF 1.0uF
4.7uF

4.7uF

1.0uF
C606

C610
4.7uF
C609

1.0uF 1.0uF 1.0uF 1.0uF 1.0uF G13 L/W:2800mil/6mil

2.2uF
4.7uF

1.0uF
C611

C622
2.2uF

100nF
2.2uF 2.2uF VSIM1 L/W:2800mil/6mil VSIM1_PMU
C617 C618 T14 GND_VREF VSIM2 H14 VSIM2_PMU
C612
C613 C614 C615 C616 C619
C604 C605 C608 C621 L/W:2800mil/8mil
C607 VCN18 L16 VCN18_PMU
GND T8 L/W:2800mil/6mil
VCN28_PMU
VCN28 L/W:2800mil/8mil
VCN33 J17 VCN33_PMU
C VDRAM B16
M16
L/W:1500mil/18mil
L/W:2800mil/8mil
VDRAM_LDO_PMU C
VMIPI L/W:2800mil/6mil VMIPI_PMU
VUSB33 H16 VUSB33_PMU
C2 E15 L/W:2800mil/8mil
GND_VMODEM VA10 VUSB10_PMU
D11 G16 L/W:2800mil/8mil
GND_VGPU VIO28 VIO28_PMU
D12 J13 L/W:2800mil/8mil
GND_VGPU VIO18 L/W:2800mil/6mil VIO18_PMU
C5 GND_VMD1 VBIF28 U8 VBIF28_PMU
D7 F13 L/W:2800mil/8mil
GND_VCORE VEFUSE VEFUSE_PMU
D8 GND_VCORE
E8 N16 L/W:2800mil/8mil
GND_VCORE VMC VMC_PMU
J15 L/W:2800mil/10mil
VMCH VMCH_PMU
C3 F17 L/W:2800mil/10mil
GND_VSRAM_MD VEMC VEMC_3V3_PMU
D10 GND_VS1
E10 N15 L/W:2800mil/8mil VCAM_AF_PMU
GND_VS1 VLDO28 L/W:2800mil/8mil
D13 GND_VS2 VCAMA T7 VCAMA_PMU
C13 F15 L/W:2800mil/8mil
GND_VS2 VCAMD L/W:2800mil/8mil VCAMD_PMU
G3 GND_VPA VCAMIO L13 VCAM_IO_PMU
P16 L/W:2800mil/8mil
VIBR VIBR_PMU
J16 L/W:2800mil/8mil
VGP3 VGP3_PMU
H8
H9
GND_LDO
T4 L/W:2800mil/10mil
Schematic design notice of "21_POWER_MT6351_2" page.
GND_LDO VXO22 L/W:2800mil/8mil VDCXO_PMU
H10 GND_LDO VA18 J14 VA18
H11 GND_LDO
J8
J9
GND_LDO VSRAM_PROC E17
F16
L/W:1500mil/18mil
L/W:2800mil/10mil VSRAM_PROC_PMU Note 21-1:
GND_LDO VRF12 VRF12_PMU
J10
J11
GND_LDO VRF18 M17 L/W:2800mil/10mil
1.0uF 1.0uF 1.0uF
1.0uF 1.0uF 1.0uF 1.0uF
VRF18_PMU Reserve 1.5K in order to give additional power to turn on
GND_LDO 1.0uF C634 1.0uF C637 1.0uF 1.0uF 1.0uF
C632
G8
G9
GND_LDO RTC T12 L/W:2800mil/6mil C628 C629 C630
C635
C638
C640 C641
charger LED driver while low battery.
GND_LDO AVDD28_VRTC C631 C633 C636 4.7uF C639 C642 C643
G10 2.2uF 4.7uF
GND_LDO 4.7uF
G11 GND_LDO XIN T11
F8 GND_LDO
F9 GND_LDO XOUT U11
F10 GND_LDO
F11 U12 VRTC
GND_LDO RTC32K_2V8
N9
Close to MT6351
RTC32K_1V8_0

RTC32K_1V8_1 N8

100nF

C646
U601-C
X601
MT6351
Charger BC1.1/1.2 F14
ACA_ID
[17] HOMEKEY B17 FCHR_ENB
C644 C645 E13
CHG_DM CHD_DM_P0 [5]
VSYS Differential M14 BATSNS
22pF 22pF CHG_DP E12 CHD_DP_P0 [5]
VBAT 4mil L14
4mil ISENSE Gauge
RTC32K1V8[4] CS_N U15 CS_N [6]
VSYS N14 VSYSSNS CS_P U16

T15 ISINK T17

1.0uF 4mil1.0uF 1.0uF BATON ISINK0
DCXO K16 VCDT ISINK1 U17 CHARGE_LED_R [15]
C647 C648 C649
K13 P17 CHARGE_LED_B [15]
VDRV ISINK2
P13 R607 0R K14 R17 CHARGE_LED_G [15]
DCXO32K_EN 0201 VRTC CHRLDO ISINK3
R13 0R R609 PCHR_LED N13 MT6351_PCHG_LED
XMODE 0201
R614
R2 VBUS GND_ISINK R16
AVSS22_XOBUF 0201
VCDT rating: 1.268V
T3
AVSS22_XO
5V ~12V
330K¡À1%
BATTERY

39K¡À1%
XTAL1 U2

0201
R615
XTAL2 U3 CONNECTOR

10uF
CHR_LDO [3,4,5,6,7,8,9,10,13,16,18,19,20]
XO_SOC R1

VIO18_PMU
TP20 TP19 TP16 TP15
U1 C601
XO_WCN
Note: 21-1 From MT6351
T1 1.5K VBIF28_PMU VBAT

C662
XO_CEL 10uF

13

14
R616
XO_NFC T2 VBUS 0201
6 7
1.0uF

24K/1%
B B

0201
R618
300mil 5 8
C650

0201
100K
R602
R617 on BAT_ON 1 4
0201

Close to PMIC
1K R620
ESD suggest <5pf 2 BM25-4S 3
[4] AUX_IN2_BATID 0201
1K J601

9 12

T601
T602
[6] CS_N
10 11

T604
T603

15

16
Rfg > 0.5W
SH2 0.01R/1%
NC/MMD/L8/4MIL
0805
R601

U601-B
MT6351
[9] RFIC_CLK_PMU J5 CLK26M
AU_MICBIAS0 N5 MICBIAS0

AU_MICBIAS1 R4 MICBIAS1
[4] AUD_CLK_MOSI N10 AUD_CLK
P5
Read Address 0xC5
AU_MICBIAS2 MICBIAS2
[4]ANC_DAT_MOSI N12 AUD_DAT_ANC_MOSI WriteAddress 0xC4
1.0uF 1.0uF
[4]AUD_DAT_MOSI_1 N11 AUD_DAT_MOSI FLYP K1 1.0uF
C653 C654 CW2015CSAD U602
[4]AUD_DAT_MISO_1 L9 AUD_DAT_MISO FLYN J1
C652 C655

[4] VOW_CLK_MISO P10 VOICE_CLK_MISO 1K

4.7uF 8 2 R622
[5,19] SDA1 SDA CELL 0201
H3 AU_LOLP
[16] AU0_HPR 7 3 R621
[5,19] SCL1 SCL VDD 0201
[16] AU0_HPL H4 AU_LOLN 100R
5 1
20mil ALRT CTG

QSTRT
[16] AU_HSP K2 AU_HSP AVDD30_AUD K5 VUSB33_PMU

GND
EP
[16] AU_HSN L2 AU_HSN AVSS30_AUD M5

4
H5 L4 C660 C661
[16] AU_HPL AU_HPL AVDD18_CODEC VA18
G5 K3 20mil R619 0R 100nF 100nF
[16] AU_HPR AU_HPR AVDD18_AUD 0201 VS1_PMU 1.0uF
L6 J2 C656 1.0uF
[16]ACCDET1 ACCDET1 AVSS18_AUD C658
[16] ACCDET2 M2 ACCDET2
AU_V18N H2 2.2uF C659
[16]AU_VIN0_P N1 AU_VIN0_P
A [16] AU_VIN0_N M1

P2
AU_VIN0_N
C657
A
[16]AU_VIN1_P AU_VIN1_P R2120 ºÍC2138 ¿ÉÒÔÅä±È£¬ÐèÒªºÍÔ-³§È·ÈÏ¡£
[16] AU_VIN1_N N2 AU_VIN1_N
4.7uF
[16]AU_VIN2_P M4 AU_VIN2_P
[16]AU_VIN2_N M3 AU_VIN2_N
P4 AU_VIN3_P
R3 AU_VIN3_N AUDREFN G4 EARPHONE_GND [16]
0R/NC
0201
R625

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 6OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

VPROC Buck

U701

MT6313
L701

VSYS A1 PVDD1 VSW1 B1 DVDD_PROC2

320mil 80mil A2 B2 100mil
PVDD1 VSW1 0.22 uH/2520
A3 PVDD1 VSW1 B3
C701 A4 PVDD1 VSW1 B4

D 10uF
C1
C2
PGND1 VSW2 E1
E2
L702
100mil
D
PGND1 VSW2 0.22 uH/2520
C3 PGND1 VSW2 E3
C4 PGND1 VSW2 E4

Buck for VDRAM

F1 PVDD2 VFBP1 C5 DVDD_PROC2_PMIC_FB[3]
80mil F2 4mil
F3
PVDD2
D5
FAN53526 / Buck I2C address: 0X60 (Write:0xC0, Read:0xC1)
PVDD2 VFBN1 4mil DVDD_PROC2_GND[3]
F4 PVDD2
C702 VSYS
D1 4 mil GND trace with Note: 23-2
PGND2 good shielding from baseband (Differential)
10uF D2 PGND2
D3 C713 C714
PGND2
D4 PGND2 U2302
100nF
4.7uF L707
A1 A2 >=30mil
VIN SW VDRAM_PMU
L703 0.22uH B1 B2 0.47uH
A8 PVDD3 VSW3 B8 DVDD_PROC1 VIN SW
80mil A9 B9 100mil
PVDD3 VSW3 4.7K 4mil
A10 B10 C1 VIN VOUT E3
PVDD3 VSW3 0201
R704
C703 A11 B11 VIO18_PMU
PVDD3 VSW3 NC/MMD/L8/4MIL
R709
C8 E8 L704 0201
10uF PGND3 VSW4 100mil 4.7K
C9 PGND3 VSW4 E9 C715
0.22 uH/2520 C716
C10 PGND3 VSW4 E10
C11 E11 [5] GPIO111 E2 SCL PGND A3
PGND3 VSW4
22uF
[5] GPIO110 D3 SDA PGND B3 47uF

PGND C2
F8 PVDD4 VFBP3 C7 DVDD_PROC1_PMIC_FB [3] Note: 23-3
80mil F9 4mil
PVDD4
F10 D7 [6,7] EXT_PMIC_EN D2 EN AGND C3
PVDD4 VFBN3 4mil DVDD_PROC1_GND [3]
F11 PVDD4
C704 D1 E1
4 mil GND trace with VSEL AGND
D8 PGND4
10uF D9 good shielding from baseband (Differential)
PGND4
D10 PGND4 Note: 23-4
D11 PGND4

R701 0R F7 F6
[6,7] EXT_PMIC_EN 0201 EN VBAT_SMPS 10mil
VSYS Schematic design notice of "23_POWER_VGPU_VM" page.
C706
Note: 22-1 BOM option to select MT6351's VGPU or 3rd party PMIC as VDRAM (1.2V) power
1.0uF
Note 23-2:
A6
[5] SCL6 SCL U2302 PL2302 C2303 C2304 R2301 R2302
[5] SDA6 A5 SDA AVSS E6
14mil
MT6351's VGPU as VDRAM NC / DNI NC / DNI NC / DNI NC / DNI NC / DNI NC / DNI
R702 NC
VSYS 0201 3rd party PMIC as VDRAM FAN53526 0.47uF 0.1uF 4.7uF 4.7K 4.7K
R703 0R F5 E7 VIO18_PMU
[5,7] EINT0 0201 VFBP2 DVDD18_IO

C705
Note: NC / DNI = No connect / Do not install.
[4,6] WATCHDOG A7 WDTRSTB_IN
100nF
B7 SRCLKEN DVSS E5
[4,6,9] SRCLKENA0
Note 23-3: Use pin muxed I2C-1 to control FAN53526 since its I2C base address is 0x60 same as VGPU and MHL.
B6 GPIO0 EINT B5

VSYS R705 NC D6 Note 23-4: FAN53526's EN pin is driven by MT6351.

0201 VFBP4 R708 NC
0201 EINT0 [5,7]

C6
NC

VFBN4
NC

C C712
C
0201

0201

150nF
R706

R707

Schematic design notice of "22_POWER_2+2PHASE_BUCK" page.

Note 22-1: Buck EN is controlled by SRCLKEN0 or I2C

B B

Companion Buck/Boost 2-Phase Buck

FAN49101 / Buck-boost I2C address: 0X70 (Write:0xE0, Read:0xE1)
FAN53555 / Buck I2C address: 0X60 (Write:0xC0, Read:0xC1)
U702
L706
FAN53555BUC09X
75mil 1.0 uH/2016 75mil
D1 VIN SW D3
U703 D2 D4 L705 0.33uH
VSYS VIN SW DVDD_GPU
E1 E3 200mil 200mil
VIN SW
C707 E2 VIN SW E4
B3 D3 C708
SW1 SW2
B4 SW1 SW2 D4
10uF 10uF VOUT A4
A3 E3 3.3V
VSYS 75mil PVIN VOUT
A4 PVIN VOUT E4 VBUCK_BOOST
75mil
[5] SCL7 A3 SCL GND B3
A1 AVIN B2
C709 GND
[5] SDA7 B1 SDA GND C1
C710 GND C2
4.7uF C711 C3
GND
[6,7] EXT_PMIC_EN A2 EN GND C4
4.7uF
22uF
A1 VSEL AGND B4
E1 AGND PGND B1
PGND C1
PGND C2 Note: 23-1
PGND C3
PGND C4
PGND D1
[5,8,18] SCL0 B2 SCL
[5,8,18] SDA0 D2 SDA

VSYS R710 0R A2 E2
0201 EN PG

FAN49101AUC340X
Schematic design notice of "24_POWER_THIRD-PARTY" page. Schematic design notice of "23_POWER_VGPU" page.

Note 24-1: Note 23-1: FAN53555's EN pin is driven by MT6351.

Note: 24-1 If R709=0ohm,R710 NC,R5109=0ohm: MT6605 can't support card mode function
when phone off (quick boot disable)
If R709=NC,R710=0ohm,R5109=0ohm: MT6605 can support card mode function
when phone off(quick boot disable)

A A

COMPANY:
LC
TITLE:

20_POWER_MT6328
DRAWN: DATED:
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 7OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D
TP17

USB_DM_P0 [5,8]
TP14

USB_DP_P0 [5,8] VIO28_PMU VIO18_PMU

TP13

USB_ID [5,8]
C823 C824
VBUS
1.0uF 1.0uF 33pF 1.0uF

2
TP11

ESD5661D07-2/TR
VBAT
C802 C801
FV801

1
TP10

44

43
VBUS

40 1
39 2
TP12

38 3
37 4
36 5 USB_DM_P0[5,8]
35 6
34 7 USB_DP_P0 [5,8]
33 8
GPIO252_KEYPAD
[5] 32 USB_ID [5,8]
9
[6,7,8,15,16,18,19,20] VSYS BPI_BUS9 [4]
31 10
30 11 BPI_BUS10[4]
[8] CTP_2.8V
25 29 12 BPI_BUS11 [4]
[5] TP_SDA4
25 28 13 BPI_BUS12 [4]
[5] TP_SCL4 VIO28_PMU[6,8,19]
27 14
[5]EINT7_TP_RST EINT13_HALL2[5]
26 15
[5] TP_EINT8
25 EINT14_HALL1[5]
16
24 17 VIO18_PMU [3,4,5,6,7,8,9,10,13,16,18,19,20]
23 18 [16] MAIN_MIC_P
[16] SPKR_OUT_P
22 19 [16] MAIN_MIC_N
[16] SPKR_OUT_M 21 20
MICBIAS0 [6]

C813 J801
C819 FV804

41
FV803

42
C810
1.0uF CM885_MAIN_SUB_40PIN_F

0201
0201
R803 R806 33pF 1.0uF
10K 10K
FV802 R813 NC
[6,18] VCAM_AF_PMU 0201

U801

[3,4,5,6,7,8,9,10,13,16,18,19,20] VIO18_PMU 4 1
C811 C812 C818 [6,7,8,15,16,18,19,20] VSYS IN OUT CTP_2.8V [8]

33pF 33pF 33pF C1829

3
EN

GND

GND
1.0uF C1830

1.0uF

5
[5] GPIO58_CTP_PWREN
C C

100K
0201
R812
SW Charger / Power Path

U802 BQ2425X-QFN
L801
VBUS 1uH
[6,8] 1 19
VBUS SW VSYS [6,7,8,15,16,18,19,20]
24 20
VBUS SW 47nF C805 L/2520H1MM/0.68/UH/3.2A
C809 C803 C807
16V 0201 C808
B 1uF 50V 0201 10uF
B
C820

21
BTST 10uF
[3,4,5,6,7,8,9,10,13,16,18,19,20] 23
PMID
VIO18_PMU

22 [8]
REGN REGN
3
/PG C806
4
STAT
17 0402
PGND
18 4.7uF
PGND
0201

10K
R801
6 15
[5,7,18] SDA0 SDA SYS
16
SYS
5
[5,7,18] SCL0 SCL
7
[5] EINT5 INT
R808 14
BAT VBAT [6,8,10,11]
8 13
[6,8,10,11] VBAT 0201 OTG BAT

[5]
10K 9
GPIO254 /CE
NC R811 C804
[5] DRV_VBUS R805 10
0201 ILIM 0201
0R 10uF
0201

10K R804
R802 R809 TS1
11
2 12 0201 REGN [8]
[8] REGN 0201 PSEL TS2 10K
GND

10K
0201

10K
25

R822

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 8OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

DRX swap
[12] RF_B3_DRX_RFIC RF_B7_PRX_RFIC [11]
RF_B40_PRX_RFIC [10]

[12] RF_B38B41_DRX_RFIC
RF_B38B41_PRX_RFIC[10]
[12] RF_B40_DRX_RFIC
[12] RF_B7_DRX_RFIC RF_B2_PRX_RFIC [11]

RF_B3_PRX_RFIC [11]
[12] RF_B1_DRX_RFIC
[12] RF_B39_DRX_RFIC RF_B1_PRX_RFIC [11]
[12] RF_B5_DRX_RFIC RF_B39_PRX_RFIC [11]
[12] RF_B8_DRX_RFIC RF_B34_PRX_RFIC [11]
RF_B8_PRX_RFIC [11]
RF_B5_PRX_RFIC [11]

VTCXO23

100nF

C904
Note:
U902
Use VCTCXO in RFIC modified 0817 by l

B10

B11

A11

B12

A12

B13

A14

B14

A15

B15

C10
C11
C12
C13
E12
R901 0R

C3
C4
C5
C6
C7
C8
D2
D3
D4
D5

D1

C2

B2

B1

A1

A2

B3

A3

B4

B5

A5

B6

A6

B7

B8

A8

B9

A9

C9
0201
[9] VTCXO23 0201 C903 0R

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

DRX1

DRX2

DRX3

DRX4

DRX5

DRX6

DRX7

DRX8

DRX9

DRX10

DRX11

DRX12

DRX13

DRX14

PRX14

PRX13

PRX12

PRX11

PRX10

PRX9

PRX8

PRX7

PRX6

PRX5

PRX4

PRX3

PRX2

PRX1

V23_ESD1

GND
GND
GND
GND
GND
10nF D6 GND GND C14
D7 GND GND C15
C902 D8 GND GND D9

3
U901 E1 D10
GND DRX PRX GND
E2 D11

VCON VCC

OUT
GND GND
E3 GND GND D13
E4 GND GND E9

GND
KT2016K26000ZAW23ZMS E5 E10
GND GND
E6 GND GND E11
E13

2
GND VRF12
[4] RFIC_CLK_BB R1 XO1 GND F9
GND F10
P2 XO2 GND F11 VRF18 100nF
26M output F13
GND
1nF RFIC_CLK_NFC R2 XO3 GND G9
G10 C905
[20] GND VRF12
P1 G11 100nF
C901 [6] RFIC_CLK_PMU XO4 GND 100nF
GND G12
R3 OUT_32K GND G13 C906
C907
R5 XTAL1 VDD_SXLV M9
VDD_SXLF M10
R4 XO M12 Note:
XTAL2 VDD_TXLV
C VTCXO23 N4 VTCXO
VDD_TXHF N10

J14
VRF18
Attenuator value : C
TXO_GND
M2 VIO TXO_GND J15
RF_VIO18
100nF
R902 TXO_GND K13
100nF Murata and Skyworks TXM use 5dB attenuator.
RF_VIO18 0201 M3 VDCXO_DIG TXO_GND L13

C909 1nF 0R
P6
TXO_GND M13
N13
C908 Qorvo TXM use 3dB attenuator.
C911 0201 XMODE TXO_GND
R903 0R R905 P13
100nF TXO_GND
C910 0201 R6 32K_EN TXO_GND R13 5dB Attenuator
R914 0R
0201
0R
M1

L1
CLK_SEL

EN_BB
MT6176 TXDET2
TXDET1
R8
R10
R904
0201 RF_TXDET1 [11]
P8 33R
[4,6,7] SRCLKENA0 RCAL
K14

0201
TX_HB1

R908
200R
VCTCXO: R914=0R, R909=NC L6

R907
200R
0201
[4] LTE_DET_BB_IP DET_BBIP
TX_HB2 K15 RF_HB2_TX_RFIC[10]
[4] LTE_DET_BB_IN L7 DET_BBIN DET pin L14

R906
TX_MB1

2K
0201
L8
R909
NC
DET_BBQP
0201
[4] LTE_DET_BB_QP
TX_MB2 M15 RF_MB2_TX_RFIC[10]
[4] LTE_DET_BB_QN L9 DET_BBQN
TX_MB3 M14 RF_MB3_TX_RFIC[11]
[4] RFIC0_BSI_EN H6 TXO
BSI_EN
TX_MB4 N15
[4] RFIC0_BSI_CK J6 BSI_CK
TX_LB1 N14
J5 BSI
[4] RFIC0_BSI_D0 BSI_D0
TX_LB2 P14
[4] RFIC0_BSI_D1 H5 BSI_D1
TX_LB3 R15 RF_LB3_TX_RFIC[11]
[4] RFIC0_BSI_D2 G5 BSI_D2
TX_LB4 R14 RF_LB4_TX_RFIC[10]
F3 GND
F4 GND TMEAS P7
F5 GND
G3 GND GND H9
G6 GND GND H10
G7 GND GND H11
G8 GND GND H12
H3 GND GND H13
H7 J9

NTC901
GND GND
H8 GND GND J10
J3 GND GND J11
J7 DRX(I/Q) PRX(I/Q) TX(I/Q) J12 closed to PA area
GND GND
J8 GND GND J13
GND K11

DRX_BB2_QN

DRX_BB1_QN
DRX_BB2_QP

DRX_BB1_QP

PRX_BB2_QN

PRX_BB1_QN
PRX_BB2_QP

PRX_BB1_QP
DRX_BB2_IN

DRX_BB1_IN
K12

DRX_BB2_IP

DRX_BB1_IP

PRX_BB2_IN

PRX_BB1_IN
PRX_BB2_IP

PRX_BB1_IP
GND

VDD_RXLV
VDD_RXHF

VDD_RXLF
L10

TX_BBQN

TX_BBQP
GND

TX_BBIN

TX_BBIP
GND L11
L12

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

MT6176

K3
K4
K5
K6
K7
K8
L2
L3
L4
L5

F7

E7

F8

G2

H2

F2

F1

E14

F14

D14

D15

J2

K2

J1

H1

G14

H14

G15

F15

P10

P11

P12

R12

M5
M8
N2
N3
N5
N6
N7
P3
P4
P5
M11
N12
P9
R9
VRF18
LTE_TX_BB_IP [4]
100nF LTE_TX_BB_IN [4]
LTE_TX_BB_QP [4]
Power domain of MT6176
C912
LTE_TX_BB_QN [4] VTCXO23

LTE_PRX_BB1_IP[4]
VRF18 R915 0R
LTE_PRX_BB1_IN[4] 0201 VTCXO24_PMU

LTE_PRX_BB1_QP[4] 100nF
100nF VRF12 LTE_PRX_BB1_QN[4]
C915
LTE_PRX_BB2_IP[4]
C913
LTE_PRX_BB2_IN[4] RF_VIO18
100nF
LTE_PRX_BB2_QP[4]
R919 0R VIO18_PMU
C914 LTE_PRX_BB2_QN[4] 0201
LTE_DRX_BB1_IP[4]
B LTE_DRX_BB1_IN[4] VRF18 B
LTE_DRX_BB1_QP[4]
LTE_DRX_BB1_QN[4] R916 0R
0201 VRF18_PMU

LTE_DRX_BB2_IP[4] 4.7uF
LTE_DRX_BB2_IN[4]
C916
LTE_DRX_BB2_QP[4] VRF12
LTE_DRX_BB2_QN[4]
R918 0R
0201 VRF12_PMU

100nF

C917

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 9OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

B5
B1/B2/B3/B5/B8/B28/ B7 / B34 / B39 / B38 / B40/ B41PA
33PF
L1013
2 1
[11]

NC
RF_B5_PA_DPX
2

2
NC

C1033

B8

C1023
1
1

L1010
33pF
2

1
RF_B8_PA_DPX [11]
2
NC NC

C1031 C1019

B3
RF_B3_PA_DPX [11]
2

C1030

3.0NH

C1024 NC
2.4PF
C1035

B2

1
1

1.5NH

L1014
4G PA input need LPF for harmonic rejection

1
2 RF_B2_PA_DPX [11]

2
NC
3/4G_PAIN_LB

C1036
3.3PF
9.1nH2 1
C1025

B1

1
R1004 RF_LB2_TX_PA
[9] RF_LB4_TX_RFIC 1

2
C1047

33pF
1

1.0NH

L1015
R1005 C1043

1
3pF 3pF 2 RF_B1_PA_DPX [11]
2

2
NC

1.5PF
3/4G_PAIN_MB C1029

C1037
1
4.7nH

16
17
18
19
20
21
1

SKY77643-21

U1002
[9] RF_MB2_TX_RFIC 2 1 RF_MB1_TX_PA

SKY77643
1

2
L1016

LB4
LB3
LB2
LB1
LB5
MB1
C1048

33pF
[6,8,11] VBAT 1 1 2 2 VPA_VCC2
C1045 C1044 GND GND
2 2 15 22 470nF
100pF
C 100nF 100pF 1pF
2
1pF
2
14
13
GND
RFIN_L
RFIN_M
MB2
GND
MB3
23
24
C1026
C
12 25 C1038
C1050 11 NC MB4 26
C1049 NC GND 1 1
10

L/M/H PA
27
9 NC VCC2_2 28
1 1 VBAT VCC1 2 2 VPA_VCC1
8 29
7 VIO VCC2 30 100pF 470nF
[4] MIPI1_SCLK 6 SCLK GND 31
[4] MIPI1_SDATA 5 SDATA B34/39 32
GND HB1 C1039 C1027
4 33

NO CA by xiaozhanglong
3 RFIN_H GND 34
GND HB2 1 1
2 35 2 2
[10,11] LTE_VMIPI 1 GND GND 36 VPA_VCC2
100pF 470nF

GND
GND
GND
GND
GND
GND
GND
GND

GND

GND
HB4

HB3
1nF

RX2
RX1
C1041 C1040 C1028

50
49
48
47
46
45
44
43

42
41
40
39
38
37
1 1 U1052

B41 TRX
PJ F6KA2G605A4LA-Z

1 4
IN1 IN2 RF_B41_TRX_TXM [11]

GND
GND
GND
L1006 L1007 1.2nH
4.7nH

3/4G_PAIN_HB

2
5
3
L1017 3.3nH NC NC
[9] RF_HB2_TX_RFIC

1
C1046
8.2pF
1 NC C1011
C1052 NC C1010
1
C1051 C1008
1.2pF C1009

Power Net Connection 2

1.2pF 2

VPA_VCC1 and VPA PMU need to be connected after Cap LPF for more margin
on Tx spurious

VPA_VCC1
0R R100210mil
0201

33pF C1007

2
4

G
1
OUT R1006 RF_B40_TRX_TXM[11]
L1012 1PF 1.2nH
0R 50mil C10203.3NH L1003 IN
R1001 1.0nH 3
VPA_VCC2 0402 VPA_PMU 1 2 G

G
C1006
[9] RF_B38B41_PRX_RFIC

L1005
L1004
B40 TRX
U1001

5
1 4.7uF 2
C1056 C1005

2
C1015 NC
1.0uF NC
NC

6.8nH
2
C1032

NC
C1022

NC
C/0201/NC
VPA_VCC1 and VPA PMU need to be connected after Cap

A
1
1

C1053 33pF L1011 1.2nH

[9] RF_B40_PRX_RFIC 1 2 1 2

0R R1003 NC
[10,11] LTE_VMIPI 0201 VMIPI_PMU [6]

2
B7 TX
4.3nH C1055
1 C/0201/NC
C1042 C1054 1

1
1.0uF
2

B L1009 2.2nH
RF_B7_PA_DPX [11] B
For power LTE_VMIPI star connection

0.5PF
NC

C1017
C1016

3 GND GND 4

2 IN OUT 5 RF_B38/B40/B41_PA_TXM_BYPASS [11]

L1002 NC L1001 NC

1 6

LF1608-B2R5KCB
NC GND GND
NC

B38/B40/B41 BYPASS

U1003
C1003
C1004 NC

A
NC
C1001
C1002

Thermister / To sense board level temperature

VIO18_PMU
390K/1%
0201
R1007

[4] AUX_IN1_NTC
NTC1001

C1034

A 1.0uF
A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 10
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

DPDT SWITCH VTCXO28 [12]

BPI_BUS15 [4]
BPI_BUS13 [4]

RF_TXDET1 [9]
[12] DRX_ANT_TUN DRX_ANT[12]

C1102
C1101

NC
NC

2
1

2
2 2 2 VBAT [6,8,10]

1.8nH
D C1155
22uF 10pF 1nF D
C1133
C1129 C1120 C1119 C1117
1nF 1nF
C1130 1 1 1

L1149
56pF

19

18

17

16

15

14

13

12
1nF R1104

NC

GND

CPL_O

GND

GND

GND

GND

GND
2 1
0201 APC1 [4]
10K

1
GND GND 2
close to ASM

1
20 11

24K/1%
C1108
0201
NC

CTL2

VDD
CTL1
GND CON1101 21 GND VBAT 10
GND 13
4 L1138 1.8nH L1133 1.2nH C1107

2
22 ANT VCC 9
2 1
RF1643A GND 12 3 4 1
RF2 23 GND VRAMP 8
5 1 NC
U1106 RF3 11 C1131 C1125 0.5pF
GND 24 TRX14 VIO 7 LTE_VMIPI [10]
6

GND
GND NC C1103 SKY77916 1

RF4
C1124

RF1
10 NC TRX13 SDATA C1111 MIPI0_SDATA [4]
2 25 6
CON1102 MIPI0_SCLK [4]

9
TRX12 SCLK

7
26 5 10nF
1.8nH 2
2 [10]RF_B40_TRX_TXM TRX11 GND
GND 1.8nH 27 4
3 1 L1101
GND RF [10]RF_B41_TRX_TXM
4 TRX10 RFIN_H 3
GND L1148 28
[10] RF_B38/B40/B41_PA_TXM_BYPASS TRX9 RFIN_L
C87P101-00003-H 1 29 2
C1132 0R
R1101 0R R1115 [11] RF_B7_TRX_TXM 30 TRX8 GND 1
0201 0201
NC

TRX7

TRX6

TRX5

TRX4

TRX3

TRX2

TRX1
GND

GND
2 39

U1107

SKY77916
31

32

33

34

35

36

37

38
[11] RF_B2_TRX_TXM

MT6169 TX Ouput need a DC block(MUST).

R1103
[11] RF_B3_TRX_TXM

0201
[11] RF_B1_TRX_TXM
[11]RF_B34_B39_PRX_TXM

RF_MB3_TX_RFIC [9]
2G_PAIN_HB

0R
[11] RF_B8_TRX_TXM

1
R1106

C1122
33pF
[11] RF_B5_TRX_TXM

0201
NC
R/0201/10/R/5%
1
R1107
0201
233pf RF_LB3_TX_RFIC [9] 2G_PAIN_LB

1
R1102

C1121
33pF
R1105
1

1
0201

0201
2

2
NC

NC
Pi attenuation for LB 8PSK TX in RX band noise

C C

no CA by xiaozhanglong
B1 TRX B3 TRX no CA by xiaozhanglong
1.8*1.4 B7 TRX
[10] RF_B1_PA_DPX [10] RF_B7_PA_DPX
[10] RF_B3_PA_DPX
C1115

L1128 3.6nH Change to 0402 on 6/21

22pF

6 3 C1118 0R
[11] RF_B1_TRX_TXM ANT TX
1
U1100 RX 0201 RF_B1_PRX_RFIC [9]
1.6nH
NC
GND
GND
GND
GND
GND

C1116

C1113
6.0pF
L1107
L1135

6.8pF
C1112
NC

6 3
[11] RF_B7_TRX_TXM ANT TX

NC
3.9nH 1.2nH 1
8
7
5
4
2

RF_B7_PRX_RFIC

C1126
RX

22pF
L1142 [9]

1.3nH
6 3

GND
GND
GND
GND
GND
3.9nH

[11] RF_B3_TRX_TXM ANT TX L1120 2.4nH

L1118

L1109

1
NC

1.0nH U1109 RX RF_B3_PRX_RFIC [9] L1134 U1104

L1114

8
7
5
4
2
2.4nH DUP/1814/B7/UNBALANCED/SAYEY2G53BA0F0A
GND
GND
GND
GND
GND

1.2pF

L1130
L1143
NC
L1116
8
7
5
4
2

L1125
L1141

NC
L1113

B no CA new 20160413 B

B2 TRX RF_B2_PA_DPX [10]

1.8*1.4
C1110

L1108
22pF
3.9nH

[11] RF_B2_TRX_TXM
6 3 C1109 3.6nH
ANT TX

NO CA by xiaozhanglong
NC

1.0nH 1 RF_B2_PRX_RFIC [9]

RX
GND
GND
GND
GND
GND

L1136
U1102
L1129

2.7nH

L1115
8
7
5
4
2

DUP/1814/B2/UNBALANCED/SAYEY1G88BA0B0A
L1106

NC

B34/39 PRX
RF_B39_PRX_RFIC [9]
C1127 1.8nH C1128 1.8nH

NC NC

B39 9 L1039 L1140

C1104

18pF
U1108
1 UNBAL3
[11]

B5 TRX
RF_B34_B39_PRX_TXM

8.2nH
B8 TRX
SAWFD1G90KA0F0A

NC
B34 6

GND2
GND1

GND3
GND4
GND5

GND7
GND6
1.8*1.4 1.8*1.4

L1102

3
2

10
5

8
L1104
A C1105 3nH
RF_B34_PRX_RFIC [9]
A

C1106
[10] RF_B8_PA_DPX

33pF
L1105 3.0pF

[10] RF_B5_PA_DPX NC L1103

L1127
L1121

22pF

L1119

L1122
7.5nH

6 3
22pF

[11] RF_B8_TRX_TXM ANT TX L1131

NC

5.6nH

1 RF_B8_PRX_RFIC [9] [11]RF_B5_TRX_TXM 6 3 COMPANY:

1.0nH RX ANT TX
LC
NC

1 L1123 12nH
5.6nH 1.0nH RX RF_B5_PRX_RFIC [9]
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND

U1103 NC L1117
U1101
8
7
5
4
2
L1112
L1111

L1110 L1126 TITLE:

8
7
5
4
2
L1132
L1137

L1124 NC

GND
NC NC
DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 11
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

W1204
W1201 W1225
W1203

DPDT SWITCH

1
1
R1200 R1230
0201 0201
0R 0R

0201
0R
R1226

R1228
0201
[11,12]
VTCXO28

0R
C1212

0201
1nF

R1231 R1232

3
0201 0201
0R 0R
L1228 68nH J1240

8
U1201
D L1229 68nH ECT818000291 D

VDD

NC
2--14, 3--2 ; 3 to B39

1
[11] DRX_ANT 3
R1219 R1220 RF1 RF_B39_DRX_ASM[12]
R1201
0R 0R

10
U1210 R1202 13 9

10
U1213 0201 0201 0201 0201 ANT RF2 LTE_B1_DRX [12]

NC

C1205
33pF
NC

RFC
R1213 NC C1216 0R 0R 2 LTE_B7_DRX [12]

RFC
1 9 C1207 NC RF3
0201 RF1 RF3 0201 1 9 DRX_ANT_TUN[11] XMSS2Q3G0PA-068TMP
0R R1214 0201 RF1 RF3 0201 10
R1212 0R R1207 R1208 NC
2 8 NC RF4 LTE_B40_DRX [12]

C1206
0201 RF2 RF4 0201 2 8 C1208 1
0R RF1694 R1215 0201 RF2 RF4 0201 5
0R 0R R1211 0R R1209 VC3 RF5 RF_B5_DRX_ASM[12]
3 7 RF1694
GND GND 3 7 11
[4] GND GND 6 RF6 [12]
LTE_B38/B39/B41_DRX
4 6 VC2
[11,12] VTCXO28 0201 VDD CTL2 BPI_BUS3 4 6
CTL1

R1216 0R [11,12] VTCXO28 0201 VDD CTL2 BPI_BUS5 [4] 14

CTL1
R1210 0R 7 RF7 RF_B8_DRX_ASM[12]
VC1
15 12 RF_B3_DRX_ASM[12]
RF8
5

C1231 GND

5
[4] C1227
BPI_BUS6 [4]
BPI_BUS4
100pF 100pF

C1234 C1233 C1230 C1229

NC NC NC NC BPI_BUS0 [4]

BPI_BUS1 [4]

BPI_BUS2 [4]
C1213 C1214 C1215

18pF 18pF 18pF

µç³Øºó¸Ç½ÓµØµã
TOPÃæ½ÓµØµ¯Æ¬
W1207
W1217 W1218 W1211 W1215 W1202 W1212 W1214 W1210 W1213
W1205 W1206 W1224 W1223
W1200 W1220

1
1
1

1
1

1
1
For power VTCXO2 star connection

1
1

1
1
1

1
0R
8mil [11,12] VTCXO28 0201 VTCXO28_PMU

R1233 0R
R1203 8mil

R1236 0R
C1200

R1235 0R
R1234 0R
1.0uF

0201

0201
0201

0201
NC
C1224
C1220

NC

C C

FDD
NO CA by xiaozhanglong DRX B3
NO CA by xiaozhanglong DRX B1
SAFFB2G65AA0F0A
B3 DRX L1200
SAFFB2G65AA0F0A

OUT 4
RF_B3_DRX_RFIC [9]

B7 DRX
[12] RF_B3_DRX_ASM 1 IN

C1203

C1204
1.2NH

22pF
L1210
OUT 4 RF_B1_DRX_RFIC [9] 1.5nH G 3

G
G
[12] LTE_B1_DRX 1 L1239
C1202

C1201
3NH

22pF

IN

L1220

L1221
1nH

5.1nH
NC
3 U1204

2
5
G 7.5nH

L1238
G
G

L1212
2.2PF

NC
L1211

1.1*0.9
NC

U1200
2
5
L1216
NC

L1203

NC

L1226 1.0nH OUT 4 RF_B7_DRX_RFIC [9]

NO CA NEW

L1224

L1225
1

C1209
22pF
C1210
LTE_B7_DRX

1.2NH
[12] IN
G 3

G
G
C1211 L1227
U1203

2
5
NC NC

1.2PF

NC
NO CA by xiaozhanglong DRX B41 B38
B
NO CA by xiaozhanglong DRX B39 SAFFB2G65AA0F0A
SAFFB2G65AA0F0A
B
1.2nH
[12] LTE_B38/B39/B41_DRX OUT 4 RF_B38B41_DRX_RFIC [9]
6.0pF C1217 4 R1204 1.2nH 1 R1206

L1206
1nF
0201

IN

22pF
C1225

OUT RF_B39_DRX_RFIC [9]

NC
NC

1 3
NC

[12] RF_B39_DRX_ASM G
L1222

50 Ohm IN
22pF

G
G
3

L1213

L1209
G
G
G

1.2nH

NC
U1207

2
5
B5 DRX / BC0
L1208
U1202
2
5

2.4nH
L1241
L1201

L1240 NC
L1223
R1205

2.4nH

U1206

NO CA NEW [12] RF_B5_DRX_ASM

1
INPUT OUTPUT
4 R1223 1.2nH RF_B5_DRX_RFIC[9]

NC
NC
1.0NH
0201

C1218

L1215

22pF
NC

GND

GND

GND
5

L1232
R1224
L1233
B8 DRX B40 DRX
1.1*0.9
1.5NH
C1221

C1222

22pF

U1212
C1223

1.0NH
0201

OUT 4 RF_B40_DRX_RFIC [9]

[12] LTE_B40_DRX 50 Ohm 1 IN
1.2nH G 3
1 4
G
G

L1217

[12] RF_B8_DRX_ASM INPUT OUTPUT RF_B8_DRX_RFIC [9]

1.2PF

L1218
1NH
0201

NC
C1226

R1225 U1205
L1235

22pF

2
5
GND

GND

GND

L1219
NC

A A
L1234

L1236
L1214

L1202
NC
5

NC
NC

NC

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 12
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

169 ball eMMC VEMC_3V3_PMU

1 bit mode for eMMC boot
C1301 C1304 C1305

4.7uF 100nF 100nF

U1301
153 ball eMMC / H26M64208EMR
MSDC0_DAT0 H3 DAT0 VCC M6
MSDC0_DAT1 H4 DAT1 VCC N5
MSDC0_DAT2 H5 DAT2 VCC T10
MSDC0_DAT3 J2 DAT3 VCC U9
MSDC0_DAT4 J3 DAT4 The eMMC VCC/VCCQ/VDDI bypass cap recommand value,
MSDC0_DAT5 J4 DAT5 VCCQ K6 VIO18_PMU
MSDC0_DAT6 J5 DAT6 VCCQ W4 please refer to vendor datasheet.
MSDC0_DAT7 J6 DAT7 VCCQ Y4
VCCQ AA3 C1302 C1306
K2 VDDI VCCQ AA5
K4 VSSQ CMD W5 2.2uF 100nF
Y2 VSSQ CLK W6
Y5 VSSQ RCLK R5
AA4 U5
C C1303 AA6
VSSQ
VSSQ
RST#_/_NC
A1_INDEX_/_NC L4 C
M7 VSS NC K7
1.0uF
P5 VSS NC K8
R10 VSS NC K9
U8 VSS NC K10 MSDC0_CMD [5]
H6 VSS NC K11
T5 VSS NC K12
NC K13 MSDC0_CLK [5]
K14
Close to A4 NC
NC
NC L1 MSDC0_DSL [5]
A6 NC NC L2
Memory A9
A11
NC
NC
NC
NC
L3
L12
MSDC0_RST_ [5]
B2 NC NC L13
B13 NC NC L14
D1 NC NC M1
D14 NC NC M2
H1 NC NC M3
H2 NC NC M12
H8 NC NC M13
H9 NC NC M14
H10 NC NC N1
H11 NC NC N2
H12 NC NC N3
H13 N12
Note: 40-1 H14
NC
NC
NC
NC N13
J1 NC NC N14
J7 NC NC P1
J8 NC NC P2
J9 NC NC P12
J10 NC NC P13
J11 P14
Schematic design notice of "40_MEMORY_eMMC" page. J12
NC
NC
NC
NC T1
J13 NC NC T2
J14 NC NC T3
K1 T12
Note 40-1: For eMMC 5.0/5.1, connect eMMC's H6 & T5 pin to GND. K3
NC
NC
NC
NC T13
R1 NC NC T14
R2 NC NC V1
R3 V2
For eMMC 4.5, check eMMC's H6 & T5 is real no connection (NC). R12
NC
NC
NC
NC V3
R13 NC NC V12
R14 NC NC V13
U1 NC NC V14
U2 NC NC Y1
U3 NC NC Y3
U12 NC NC Y6
U13 NC NC Y7
U14 NC NC Y8
W1 NC NC Y9
W2 NC NC Y10
W3 NC NC Y11
W7 NC NC Y12
W8 NC NC Y13
W9 NC NC Y14
W10 NC NC AE1
W11 NC NC AG2
W12 NC NC AH4
W13 NC NC AH6
W14 NC NC AH9
AA1 NC NC AH11
AA2 NC NC AG13
AA8 NC NC AE14
AA9 NC
AA11 NC
AA12 NC
AA13 NC
AA14 NC RFU H7
RFU K5
AA7 RFU RFU M5
AA10 RFU RFU M8
U10 RFU RFU M9
U7 RFU RFU M10
U6 RFU RFU N10
P10 RFU RFU P3

B B

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 13
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

Wifi & GPS & FM

D D

AVDD18_WBT

C1409
100nF
BT_DATA [5]

BT_CLK [5]

C1411
100pF
WF_CTRL0 [5]

WF_CTRL1 [5]

WF_CTRL2 [5]

U1406
Close to Antenna

30

29

28

27

26

25

24

23

22

21
C1413

C1414
1.8nh

WIFI_AUX_2G

WB_VDET_2G

WIFI_VDET_5G

AVDD18_WBT

AVDD18_WBT

BT_DATA

BT_CLK

WF_CTRL0

WF_CTRL1

WF_CTRL2
U1403

2nH
5
3
2
4 1

G
G
G
W1404 W1401 W1208 50 Ohm 50 Ohm OUT IN 50 Ohm
PJ F6HF2G441AF46-Z
L1405

L1404

6.8NH
NC

L1406
31 20

L1403
1

WB_RF_2G WF_IP WF_IP [5]

1Pf
R1430 R1429 8.2NH
0201 0201 <Critical!!>
0R
0R 5G PCB loss is higher and 32 NC WF_IN 19 WF_IN [5]
trace must kept short and AVDD33_WBT 0R
Close to AVDD33_WBT R1415
0402 VCN33_PMU
C 50-ohm No layer transition MT6631 10uF C1412 33 AVDD33_WBT WF_QP 18 WF_QP [5]
C
U1405

C1415
100pF
1 GND MB GND 7 34 WF_RF_5G WF_QN 17 WF_QN [5] B1401
C1416 FM_AVDD28 VCN28_PMU
CON1405
0R 0R R1409 0R 50 Ohm 0R B0402/BLM15BD102SN1D 1.0uF
R1401 R1402 2 6 R1410
W1411

1 0201 0201 0201 COM HB 50 Ohm 0201 50 Ohm 50 Ohm

2 1 35 WF_AUX_5G BT_IP 16 BT_IP [5]

6.0pF
C1402 3 4 FM_AVDD28 C1422
C1401 R1400 3 5
GND GND
0201

L1408
1.8nH
L1407
LB

NC

NC
NC 36 AVDD28_FM BT_IN 15 BT_IN [5]
nc TP2012-A1255DA
4

C1417
10nF
R1411 0R
AVDD18_GPS 0402 VCN18_PMU
50 Ohm 37 14 C1418
FM_LANT_N BT_QP BT_QP [5]
[16] FM_RX_N_6631
18pF 1.0uF
L/0201/82/NH/3%/SUNLORD R1414 0R
AVDD18_WBT 0402
C1410 [16] FM_ANT L1409 38 13 BT_QN [5]
FM_LANT_P BT_QN
82nH

C1407

0201
33pF
L1402 0R 39 12

R1413
GPS_RX_IP [5]

0201
0201 50 Ohm GPS_RFIN GPS_IP

R1412

NC
0201
NC
NC AVDD18_GPS
40 AVDD18_GPS GPS_IN 11 GPS_RX_IN [5]
C1408

AVDD28_FSOURCE

CONN_TOP_DATA
4.7nF

CONN_TOP_CLK
41

CONN_HRST_B
DVSS
C1419

XO_OUT
WB_PTA

GPS_QN

GPS_QP
XO_IN
CEXT
GPS xLNA

10
MT6631
Close to ANT matching value depends on U1402
GPS_RX_QP [5]
LNA selected 1
GND RFOUT
6
GPS_RX_QN [5]
[5] CONN_RSTB
C1403

U1401 2 5 R1404 0R
0201

GND EN GPIO141 [5]

18pF
0201
1 4 L1401 10nH 3 4 [5]CONN_TOP_DATA
50 Ohm IN OUT RFIN VDD
2 5 R1403 0R 1.0uF 100pF
GND GND 0201 VCN28_PMU[6,14] [5]CONN_TOP_CLK
3 NC WS7916-6/TR
GND
1.0uF C1420 C1421
SAFFB1G56KB0F0A C1404 [5]CONN_WB_PTA
SAFFB1G56KB0F0A C1405

1
GND

GND
KT2016K26000ZAW18TAS

OUT

VCC
X1401

R1407 0R R1405 0R R1406 0R

4
[5] CONN_XO_IN_BB 0201 0201 0201 VCN28_PMU

C1406

B 1.0uF B

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 14
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

RGB LED
BlinkLED Driver
VSYS

D D
LED1501
I2C Address: 45H
BB CHAGER EMMC GPS NFC PA RF
C1507

100nF

SH1501 SH1502 SH1503 SH1505 SH1504 SH1506 SH1508

CM885_BB CM885_CHAGER CM885_EMMC CM885_GPS CM885_NFC CM885_PA CM885_RF

[6] CHARGE_LED_R 0201

R1507 0R
[6] CHARGE_LED_G 0201
T1508 0R
[6] CHARGE_LED_B 0201
R1509 0R
T1501 T1502 T1503

1
GND

C C

MOTOR DRIVER CIRCUIT

MOTOR CONTACT
AW1501 AW1502

B B
B1501 0R
0402 VIBR_PMU [6]
D1501

NC

T1505
FV2301 change to 0OHM when NOT USE IC
NC
GND
GND

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 15
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

MIC CE ÈÏ֤ʱ,Èç¹ûÓöµ½¹¤Æµ¸ÉÈÅÍƼö0B4015R-423G-XD9RAC-BD-0MIC REC Earphone MIC Main microphone

[6] MICBIAS1
MICBIAS2
Analog MIC
Route as differential pair
SPH0642HT5H-1 Close to MIC

R1611
SPH0642HT5H-1 Close to BB
2
N B1608
5 1 Close to BB Close to MIC
GND B1610 P Close to CON6001 Close to BB

0201
3 GND OUTPUT 4 AU_VIN2_P[6] C1629 AU_HSN [6]
2 REC6001 BLM15BD182SN1D
GND

C1610

1.0uF

C1613

100nF
B1609

1k¦¸
1 GND VDD 6 C1611 100pF AU_HSP [6] C1614 [8] MAIN_MIC_P AU_VIN0_P[6]
BLM15BD182SN1D

C1621
AU_VIN1_N1

1.0uF
[6]AU_VIN1_N
U1602 B1606
100pF
N
2 GND of C6018(10uF) and C1622
1 0R/4.7uF
AU_VIN2_N[6] P C1617 headset should tie 100pF

C1612
R1617

1.0uF
T1601 T1603 REC1
together and single via to

R1612
33pF [8] MAIN_MIC_N AU_VIN0_N[6]
C1618

C1623

1.0uF
0201

C1615 C1616
C1630 C1627 GND plane

T1605

0201
T1606
T1602 T1604 100pF
33pF 33pF C1624 C1625
33pF 33pF
C1619
0R

100nF tie together and single via to

1.5K
33pF 33pF

C1620

100nF
33pF GND plane
[6]AU_VIN1_P HP_MIC [16]

together then single via to main GND 1k¦¸

[6] ACCDET1 R1613
0201

Earphone Audio

nokia,L-R-MIC-GND

default Iphone,L-R-GND-MIC VIO18_PMU

C C
Note: 60-4 100nF

T1609
C1635

0201
R1604
R1619

470K
[6] ACCDET2 0201
47K
close to IC
Route the GND between L/R chanel
close to connector
Note: 60-1 Note: 60-3 R1605 J1601
[5] EINT15_HS_DET 0201
47K B1607
[6] EARPHONE_GND GND
B1605 HPH_R
[6] AU_HPR R1608 0R
0201

R1618 HS_DET
0201
B1603 1k¦¸
R1606 0R HPH_L
[6] AU_HPL 0201
B1601 MIC_IN
[16] HP_MIC
R1609

Note: 60-2
C1608 C1609
R1607
470R
0201

0201

T1608 C <= 1pF

33pF 33pF C1601 C1602
T1607

T1610
470R

NC 1nF

T1611
Single via to
C <= 1pF GND plane

Schematic design notice of "60_PERI_AUDIO_IO" page.

R1601 0R
0201 FM_ANT[14]
Note 60-1: Part # of BEAD6002, BEAD6003, BEAD6004 and BEAD6005
needs changed to "BLM18BD102SN1" for high THD
performance (-90dB) but this BOM change will results in FM B1611
RSSI 10dB degraded .
R1610 0R
0201 FM_RX_N_6631[14]

Note 60-2: optimize headphone pop noise. The recommended value of this resistor is 33R.
To reserve a resistor in HPL and HPR in series connection both in order to

Note 60-3: TO Reduce cross talk, Please route the Earhpone_GND between L/R chanel

Note 60-3: To eliminate Plug in and out Recognize issue C6049 should be 100nF

Speaker PA
B B

[6,7,8,15,18,19,20] VSYS

C1634 C1606

4.7uF 100nF

2.2uF

C1603
A3

D2

C1
B3
0201

100K
VDD

VDD

C1P

C1N

R1614

D1
C2P
2.2uF

C1605

[5] GPIO71_SPK_EN A4
SHDN
B1
C2N
C1604

B2
33nF

C2N
R1615 0R
[6]AU0_HPL 0201 U1601 R1602
B4 SPKR_OUT_P [8]
3K AW8738 VOP 0603
A2
INN
C1628
R1603
D4 0603 SPKR_OUT_M [8]
220pF VON
0R
C1607

A1
33nF

INP
R1616
[6]AU0_HPR D3 C1632
0201 PVDD C1633
3K
GND
GND
GND

C1631

1nF
4.7uF

1nF
C4
C3
C2

C836£ºwhen use AW8145 please use 1uF CAP;when use AW8155 or AW8155A please use 0 ohm res

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 16
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

Power Key
D D

NC NC NC NC
TP1704 TP1703 TP1702 TP1701

1
R1711 1K 2 7
[6] PWRKEY R1705 0201 GND

N21078821
1K 3
[6] HOMEKEY R1709 0201

N21078897
1K 4 8
[5] KPROW0 R1710 0201 GND
1K 5
0201
Note: 65-1 [5] KPCOL0 6

J1703
T1717 T1718 T1719 T1720
PF050-B06B-C09-A_6PIN_F
Note: 65-2

C1705

33pF

Schematic design notice of "65_PERI_Dual_SIM_ICUSB_KEYPAD" page.

Note 65-1: DO NOT put pull-up resistor on PWRKEY

Note 65-2: Volume Up : HOME Key / GND

Volume Down : (KPROW0/KPCOL0) or KPCOL0 / GND

C C

SIM1& T Card Switch

R1701
1K
[4] INT_SIM1 0201

R1702 1K
[5] INT_TCARD 0201 EINT

VSIM1_NFC [20]
T1701

J1702

21 7
DETECT VCC1
22 8
DE-LE RST1 SIM1_SRST [4]
B CLK1
9 SIM1_SCLK [4] B
13 11 SIM1_NFC_SWP1 [20]
[5] MSDC1_DAT2 DAT2 VPP1

[5] MSDC1_DAT3 14 12
CT-DAT3 IO1 SIM1_SIO [4]
15 10 T1702 T1703
[5] MSDC1_CMD CMD GND T1704 T1705 T1706
C1701
16 34
VMCH_PMU VDD GND 1.0uF ½áµçÈÝ<10PF
[5] MSDC1_CLK 17 35
CLK GND
18
VSS
19 1
[5] MSDC1_DAT0 DAT0 VCC2 VSIM2_PMU
[5] MSDC1_DAT1 20 2
DAT1 RST2 SIM2_SRST [4]
3
T1724 C1703 C1706 C1704 CLK2 SIM2_SCLK [4]
T1727 T1726 T1725 T1723 T1722 31
T1721 GND NC
5
VPP2 0201
2.2uF 100nF 2.2uF R1703
23 6
GND IO2 SIM2_SIO [4]
24
GND
25 4
GND GND
26 T1708
GND T1709 T1710
27 33 C1702
GND
T1707

28 GND
GND
29 32
GND GND 1.0uF
30
GND

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 17
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

Main Camera LCM

Main Camera A Main Camera AVDD

D D

27pF
C1817
B1801
1 30
[5] CAM_CLK0 MCLK DGND
2 29 CAM_D2P_A [18]
DGND MDP2
[18] CAM_D0P_A 3 28
MDP0 MDN2 CAM_D2N_A [18]
4 27
[18] CAM_D0N_A MDN0 DGND
5 26
DGND J1802 MDN3 CAM_D3N_A [18] EMI1809
[18] CAM_D1N_A 6 25
MDN1 MDP3 CAM_D3P_A [18] 3 2 TDN0_LCM [18]
[18] CAM_D1P_A 7 24 [5] TDN0
MDP1 DGND 4 1 TDP0_LCM [18]
8 23 [5] TDP0
DGND AF_EN
[18] CAM_CLKN_A 9 22
MCN VPP T1803 T1804
10 21 CAM_RST0 [5]
[18] CAM_CLKP_A MCP RESET EMI1810
11 20
DGND SIO_D MCAM_SDA2 [5]
12 19 3 2

41
VCAM_AF_PMU AF_POWER SIO_C MCAM_SCL2 [5] [5] TDN1 TDN1_LCM[18]
2.8V 13 18 4 1
AF_GND DGND 1.8V [5] TDP1 TDP1_LCM [18]
2.95V 14 17 1

GND
CAM_AVDD_3V0 AVDD DOVDD VCAM_IO_PMU GND
B1802 15 16 1.0V U1802 R1808 0R 2
AGND DVDD VCAMD_PMU [4] ID0 0201 LCM_ID
3
NC
EMI1811 4
4 1 [5] LCM_RST RST
[6,7,8,15,16,18,19,20] 5
C1820 C1818 C1838 VSYS IN OUT CAM_AVDD_3V0 [18] [5] TDN2 3 2 TDN2_LCM[18] [5] DSI_TE TE
DF37NC-30DS-0.4V(51) 4 1 TDP2_LCM [18] 6
[5] TDP2 NC
7
C1819 1.0uF 2.2uF 2.2uF GND
C1828 8
C1816

3 [18] TDP0_LCM D0+

[5] CAM_AVDD_EN EN 9

GND

GND
NC
1.0uF EMI1812 [18] TDN0_LCM 10
D0-
11
C1840 [5] TDN3 3 2 GND
1.0uF 10uF TDN3_LCM [18] 12

5
[5] TDP3 4 1 [18] TDP1_LCM D1+
R1816 TDP3_LCM [18] 13
NC

R2607
2.2uF 14
[18] TDN1_LCM D1-
0402 C1839 15
GND
0R

0201
EMI1813 16
CLK+

100K
3 2 [18] TCP_LCM 17
2.2uF [5] TCN TCN_LCM [18] NC
4 1 18
[5] TCP TCP_LCM [18] [18] TCN_LCM CLK-
19
GND
[18] TDP2_LCM 20
D2+
21
NC
22
[18] TDN2_LCM D2-
23
GND
24
[18] TDP3_LCM 25
D3+
C1826 C1825 NC
26
[18] TDN3_LCM D3-
27
GND
[18] LCD+ 100nF 1.0uF 28
+5.5V
29
[18] LCD- -5.5V
[3,4,5,6,7,8,9,10,13,16,19,20]VIO18_PMU 30
IOVCC
31
GND
32
LED1+
R1819 0R 33
VCAMA_PMU 0201 [18] LED+ LED2+
34
LED-
[18] LED1- 35
[18] LED2- LED2-
36
U1805 GND
37
[18] LED_PWM PWM
EMI1801 38
GND
4 1 39
4 1 [6,7,8,15,16,18,19,20] IN OUT VCAMA_SUB OTP/NC

GND
[5] RCN CAM_CLKN_A [18] VSYS [18] NC NC NC NC NC
3 2
[5] RCP CAM_CLKP_A [18]
J1801
C1808C1809 C1821

40
C1806 C1807
3
[5]
SUB_VCAMA_EN EN

GND

GND
EMI1803 C1843

5
4 1
[5] RDP0 CAM_D0P_A [18]

R1818
3 2 2.2uF
[5] RDN0 CAM_D0N_A [18]
C1841

0201
100K
2.2uF
EMI1802
4 1
[5] RDN1 CAM_D1N_A [18]
3 2
[5] RDP1 CAM_D1P_A [18]

C EMI1804
C
3 2
[5] RDN2 CAM_D2N_A [18]
4 1
[5] RDP2 CAM_D2P_A [18]

EMI1805
[5] RDP3 3 2
CAM_D3P_A [18]
4 1
[5] RDN3 CAM_D3N_A [18]

Front Camera Black Light Flash

VSYS

B1805 L1802 D1801 R1801 0R

0402 LED+ [18]
BLM18AG102SN1D 10uH
Back Light Driver for 12LEDs In 2Series 6 P

R1814
0201
10R
B B
25

26

C2

C3
U1808
1 2
I2C Address: 0x53

VIN

SW
3 4 VSYS
[18]CAM_D0N_A_F CAM_CLKN_A_F[18]
5 6 A3
[18] CAM_D0P_A_F 7 8 CAM_CLKP_A_F[18] C1 IFB1 LED1- [18] L/2016H1MM1/0.47/UH/20%/4.3A/SUNLORD
[5]GPIO50_RST EN
9 10 B1 A2
[5] MCAM_SCL3
11 12 CAM_D1N_A_F[18] [4] LCM_PWM 0201 PWM IFB2 LED2-[18] L1801 0.47uH
0R

1.0uF
[5] MCAM_SDA3 13 14 CAM_D1P_A_F [18] R1811

C1811
B2 A1 C1833

C1832
15 16 CAM_PDN1 [5] R1805 COMP ISET

GND
VCAM_IO_PMU

100nF
17 18 C1810
0201 CAM_RST1 [5] [18] LED_PWM 0201 C1834 C1835
VGP3_PMU 0R 19 20 33pF
NC

B1
R1820

0201
21 22 10uF

B3
J1803 100K C1836 R1815

0201
[18]VCAMA_SUB 23 24 CAM_CLK1[5] R1813 10uF 1.0uF
B1804 B1803

SW
62K
R1821 A2
[6,18] VCAMD_PMU 0201 330nF IN 10uF
27

28

U1801
C1823

NC C1
27pF

OUT
[5] GPIO255_TORCH_EN C3
GND TORCH/TEMP
[5] GPIO137_FLASH_EN B2 C1812
STROBE
C1815
1.0uF
C1824

C2 D3
10uF

C1822 [5] GPIO140_FLASH_CE HWEN LED1

C1814 R1806 0R D2
[5]GPIO60_FLASH_TX 0201 TX
1.0uF [5,7,8,18] SDA0 A3 D1
1uF SDA LED2
B3
[5,7,8,18] SCL0 SCL

GND
0201
100K

R1804
100K
100K

0201
R1802

0201
R1803

A1

HL1802
HL1801
T1802

T1801
VSYS

EMI1806
4 1
[5] RCN_A CAM_CLKN_A_F [18]
3 2
[5] RCP_A CAM_CLKP_A_F [18] 4.7uH
15mil L1803 15mil

EMI1807
3 2 C1801
[5] RDN0_A CAM_D0N_A_F [18] U1803
4 1
[5] RDP0_A CAM_D0P_A_F [18] 4.7uF C1 D1
R1810 0R VIN SW
0201
GND

HTCA5 E3 10mil 40ma

EMI1808 OUTP LCD+ [18]
[5] EINT10 B1
4 1 ENP E2
[5] RDN1_A CAM_D1N_A_F [18] [5]LCM_ENN A1 REG C1805
3 2 ENN D3
[5] RDP1_A CAM_D1P_A_F [18] REG GND

B2 A2 4.7uF 10mil 40ma

[5,7,8,18] SCL0 SCL OUTN LCD- [18]
C2 SDA
[5,7,8,18] SDA0
B3 C3
PGND CFLY1
E1 PGND
100K C1804
0201

A3 C1802 C1803
C1831 D2
0201

100K AGND CFLY2

R1812 R1809 2.2uF
1.0uF KTD2151 4.7uF 10V 10uF 10V
NOVTEK/KTD2151EUO-TR
C2313/C2314 and C2317 are
A GND
GND
GND GND

GND GND
suggested to use 10uF for A
component de-rating
consideration.

Schematic design notice of "63_PERI_CAMERA_KEYPAD" page.

Note 62-1: The VCC of I2C_0 is pulled to "VCAM_IO_PMU". COMPANY:
LC
Note 62-2: I2C control interface of front camera (with AF) must be assigned to I2C-2
TITLE:
bus when PIP/VIV feature be supported.
DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
Note 62-3: Reserve a capacitor (27pF) on camera's MCLK and shunt it to GND to prevent GPS de-sense.
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 18
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

Thermister / To sense board level temperature

C
M-Sensor P_SENSOR VIO18_PMU
VIO28_PMU
C
M-Sensor I2C Address: 0x0C VIO18_PMU

R1903
0201
0R
CAD

0201
100K

390K/1%
R1902
0201
R1905
C1911 4.7uF
VIO18_PMU VIO28_PMU
0 0X0C
1 0X0D [4] AUX_IN0_NTC
U1901 1 8 VSYS
[5,6,19] SDA1 SDA VDD
[5,6,19] SDA1 C3 SDA VDD A1 2 7
[5,6,19] B3 C1 ÓÃÓÚ±£»¤M-sensor£¬±ÜÃâѹ»µ [5] ALSP_INT_EINT11 INT SCL SCL1[5,6,19] C1915
SCL1 SCL VID NTC1901
3 6
A2 A3 LDR GND
CAD TST 0R 1.0uF
C1908 C1907
4 5

10uF
C2 B1 LED_K LED_A 0201
[5] MAG_RST_EINT3 RSTN VSS
100nF 100nF R1904
U1902
YAMAHA/AK09911C

T1903
LTR-579ALS-028WA C1912

C1910
4.7uF

INFRA-RED LED [6,7] VBUCK_BOOST

0R
0201 BOARD_ID
G+Gyro-Sensor
R1906

LED1901
IR VIO18_PMU
C1913
BMI160 I2C address : 0x68
LSM6DS3 I2C address : 0x6A 4.7uF
BMI160: R6314, R6315 = NC
LSM6DS3: R6314, R6315 = 0R
SDA1 [5,6,19]

SCL1 [5,6,19]
VIO18_PMU

VIO18_PMU

R1914
0201
10K
R1912
0201
10K
Q1901 C
R1907
PWM 38KHZ B

T1901
14

13

12

U1903 [5] GPIO135_IR_PWM0 0201

T1902
10K
R1908
0201
0201
R1909

SDX

SCX

CSB
NC
NC

1 11 R1910 0R [5]GPIO52_BOARD_ID0

E
SDO OSDO(GND) 0201
[5]GPIO53_BOARD_ID1
2 10 R1911 0R

0201
ASDX OSCB(GND) 0201 R1916
100K
3 9
ASCX INT2 GYRO_EINT2 [5]
VDDIO

4 8 VIO28_PMU [6,8,19]

R1913
0201
[5] ACCL_EINT1 INT1 VDD

10K

R1915
GND

GND

0201
B

10K
B BMI120 B
5

VIO18_PMU C1904

100nF
C1905

100nF

FingerPrint-Sensor
FV1905 FV1904 FV1903 FV1902

100nF
CON1901
SPI input output becare
C1903
[5] EINT9_FP_INT FV1901 1 10 [5] WILL 2.8v
IRQ RST_N GPIO143_FP_RST
2 9 FP_SPI1_MO [5]
GND_HOST MOSI U1904
3 8 SP_SPI1_MI [5]
GND_HOST MISO
4 7 FP_SPI1_CS
R1919 GND_HOST CS_N [5]
[3,4,5,6,7,8,9,10,13,16,18,19,20] 0R 5 6
VIO18_PMU 0201 VDD1.8V SCLK FP_SPI1_CK [5] 4 1
R1921 [6,7,8,15,16,18,19,20] VSYS IN OUT VFP_2.8V [19]
NC
[19] VFP_2.8V 0201
R1920 NC
[19] VFP_2.8V 0201 3
[5] EN
GND

GND

R1901 FP_LDO_EN
[6,8,19] VIO28_PMU NC
0201 C1902
R1918

C1901 0402
0201

FV1907 FV1908 2.2uF

100nF 0402
2.2uF
FV1906
100K

C1909

C1906

100nF
MARK POINT
M1001 M1002 M1003 M1004
1 1 1 1

A MARKD2MM MARKD2MM MARKD2MM MARKD2MM A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 19
OF 20
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

1uH
D L/0603HMM95/2.2/UH
D

B1

B2
L2003

SW

SW
A1 VDD_UP [20]
A3 VOUT
[6,7,8,15,16,18,19,20] VSYS VIN A2
VOUT
B3
[20] DCDC_EN EN

PGND
PGND

PGND
PCA9410
C2026 C2029

C2
C1

C3
U2010
22uF 22uF

NFC power
NC
VIO18_PMU 0201
R2010
VSYS

U2002

4 1
IN OUT PN547_1.8V [20]
3
[5] GPIO41_NFC_1.8V_EN EN
GND

GND
C2024
SGM2036-UTDFN
2

2.2uF
R2012 C2023
0201

100K
2.2uF

C C

VSIM1_NFC [17,20]
NFC

VSIM1_PMU [3,6,20]
I2C_ADR1

ÉÏÏÂ×óÓÒ°üµØ£¬Öص㱣»¤¡£
SIM1_NFC_SWP1 [17]
I2C_ADR0 WRITE

TEST2003

TEST2005
TEST2004

TEST2006
READ

C2010

470nF
NFC_SE_RESET [5]
SPI2_CK [5]
SPI2_MI [5]
SPI2_MO[5]
SPI2_CS [5]

0 0 0X50 0X51 R2004 R2005

NFC_SE_IRQ [5]

0201

0201
4.7K 4.7K

C2011
1.0uF
C2028 1.0uF

0 0X52 0X53

HB_177_XC_001_SP
1 C2014 1nF
0R
0201

A4

A5

D5

A7
A6
E6
C5
F4
B5
B4

E5

E3

B7
E4
U2001 R2041

SIM_SWIO

SIM_VCC

ESE_IO2
PMUVCC
EXT_SW_CTRL

ESE_SWP
ESE_SWIO
SMX_RST_N

ESE_IO1

ESE_VDD
SVDD
ESE_IO3
ESE_IO4
SMX_CLK
2.2uF

C2009
R2003 0R

R2006
[9] RFIC_CLK_NFC 0201

0201
NC

AW2002
1 0 0X54 0X55 [5] SCL5
A3
C3
B2
XTAL1
XTAL2
TVDD

ANT1
E7

G7
C2019 56pF

[5] SDA5 I2C_ADR0 F6 L2001

D2 RXP C2002
I2C_ADR1
[5] EINT16_NFC_IRQ G3 22pF
B1 TX1 160nH
I2C_SCL
C2004
[5] GPIO59 C1 G5 C2030 T2002
I2C_SDA TX2

TEST2001
C2020

TEST2002
D1 F5 180pF
IRQ RXN 100pF
R2001 100pF

0201
G6

0X56
E1

0X57
1M VEN ANT2 C2001 100nF

1 1 [5] DWL_REQ

[4] SRCLKENAI
A1

A2
DL_REQ

CLK_REQ
VMID
VDHF
F7
D7 C2005
C2021
C2031

B3 F1 180pF 100PF 100pF

SMX_IF_SEL C2008 470nF

HB_177_XC_001_SP
[5] NFC_SE_EN SVDD_PWR_REQ
[20] PN547_1.8V D3 F2 160nH
PVDD RFU DCDC_EN[20]
C2003 22pF
C7 G2
[20] NFC_VSYS VBAT VUP VDD_UP [20] L2002
C6 G1
VDD VBAT2 NFC_VSYS[20]

DCDC_VSS
C2022 56pF

R2007
0201
NC
TVSS
PVSS

VSS1

VSS2

VSS3

VSS4

VSS5
C2012 R2002

0201
C2017 1.0uF C2018 C2007 C2006

AW2001
1M

C2

B6

C4

D4

D6

F3

E2

G4
1.0uF 4.7uF C2013
B 10nF 100nF 100nF
C2015 1nF
0R
0201
B
R2040

T2001

R2011
0201 VDD_UP [20]
NC

R2015
0R
[6,7,8,15,16,18,19,20] VSYS 0201 NFC_VSYS [20]

R2020
[3,6,20] VSIM1_PMU 0201 VSIM1_NFC [17,20]
NC

A A

COMPANY:
LC
TITLE:

DRAWN: DATED:
CX880
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number>
<Revision>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 20
OF 20