PROGRAMMABLE 
LOGIC AND 
SOFTWARE 

NZUWERA GILBERT 
 

NATIONAL UNIVERSITY OF 
RWANDA 

www.ngoma84.8m.net

+25008730159
 PROGRAMMABLE LOGIC AND 
SOFTWARE 
 

PART I: PROGRAMMABLE LOGIC

CHAP 0: OVERVIEW

In the world of digital electronic systems, there are three basic kinds of devices:

• memory,
• microprocessors,
• And logic.

Memory devices store random information such as the contents of a spreadsheet or database.
Microprocessors execute software instructions to perform a wide variety of tasks such as running a word
processing program or video game. Logic devices provide specific functions, including device-to-device
interfacing, data communication, signal processing, data display, timing and control operations, and
almost every other function a system must perform. In this document we will focus on logic devices.

Fixed logic vs. Programmable logic

Logic devices can be classified into two broad categories - fixed and programmable. As the name
suggests, the circuits in a fixed logic device are permanent, they perform one function or set of
functions - once manufactured, they cannot be changed. On the other hand, programmable logic
devices (PLDs) are standard, off-the-shelf parts that offer customers a wide range of logic
capacity, features, speed, and voltage characteristics - and these devices can be changed at any
time to perform any number of functions.

During the design phase customers can change the circuitry as often as they want until the design
operates to their satisfaction. That's because PLDs are based on re-writable memory technology -
to change the design, the device is simply reprogrammed. Once the design is final, customers can
go into immediate production by simply programming as many PLDs as they need with the final
software design file.

CHAP I: PROGRAMMABLE LOGIC

I. SPLDs and CPLDs

Two major types of simple programmable logic devices are the PAL and the GAL. The PAL stands for
Programmable Array Logic, and the GAL stands for Generic Array Logic. Generally a PAL is one-time
programmable (OTP), and is a type of PAL that is reprogrammable; however, because some
reprogrammable SPLDs are still called PALs, the line between PALs and GALs is a little vague in
common usage. The term GAL is originally used by Lattice Semiconductors and later licensed to other
manufacturers.
The basic structure of PALs and GALs is a programmable AND array and a fixed OR array, which is
basic sum-of-product (SOP) architecture.

The complex programmable logic device (CPLD) is basically a single device with multiple SPLDs that
provides more capacity for larger logic designs

1. SPLDs OPERATION

a. PAL (Programmable Array Logic)

The PAL consists of a programmable array of AND gates that connect to a fixed array of OR gates.
Generally, PALs are implemented with the fuse processing technology and are therefore OTP
devices. The PAL structure allows any SOP logic expression with a defined number of variables to be
implemented.

Figure 1 – 01: basic AND/OR structure of a PAL

b. GAL (Generic Array Logic)

The GAL is essentially a PAL that can be reprogrammed. It has the type of AND/OR organization
that the PAL does. The basic difference is that a GAL uses a reprogrammable process technology,
such as EEPROM (E2CMOS), instead of fuse process technology.

Figure 1 – 02: (EPROM process technology)

 c. PAL/GAL General Block Diagram

The basic difference is that a GAL has a reprogrammable array and the PAL is OTP. The
programmable AND array outputs go to fixed OR gates that are connected to additional output logic.

Figure 1 – 03: PAL/GAL general block diagram

d. MACROCELLS

A macrocell generally consists of one OR gate and some associated output logic. The macrocells vary in
complexity, depending on the particular type of PAL or GAL. A macrocell can be configured for
combinational logic, registered logic, or a combination of both. Registered Logic means that there is a flip
– flop in the macrocell to provide for sequential logic functions.

Figure 1 – 03: combinational output (active-LOW)

Figure 1 – 04: combinational input/output (active-LOW)

Figure 1 – 05: program
mmable polarity output.

2. CPLDs
C

A CPLD consists
c of multiple
m SPLD
D array with prrogrammablee interconnecttions. We willl refer to eachh
SPLD arraay as a LAB (Logic Arrayy Block). The programmable interconnections are gennerally calledd PIA
mmable Intercconnection Array). The LA
(Program ABs and the interconnectio
i ons between LABs
L are
programm
med using soft ftware.

A CPLD can
c be prograammed for coomplex logic functions
f based on the SOP structure off the individuual
LABs. Inpputs can be co Bs, and their outputs can be
onnected to any of the LAB b interconneccted by any other
o
LAB via PIA.
P

Figure 1 – 06: Basic block

b diagram
m of CPLD.
 II. FPGAs

As we have seen, the classic CPLD architecture consists of PAL/GAL logic blocks with programmable
interconnections. Basically, the FPGA (Field Programmable Gate Array) differs in architecture does not
use PAL/GAL type array and has much greater densities than CPLD. A typically FPGA has many time
more equivalent gates than a typically CPLD, and there are many more of them. Also, the programmable
interconnections are generally organized in a row and column arrangement in FPGAs.

The three main elements in an FPGA are:

• The configurable logic block (CLB),

• The interconnections,
• And the input/output blocks.

Figure 2 – 01: basic structure of an FPGA.

1. CONFIGURABLE LOGIC BLOCK

Typically an FPGA logic block consists of several logic modules that are the basic building units,
somewhat analogous to macrocells in a CPLD. Each CLB is made up of multiple smaller logic modules
and a local programmable interconnect that is used to connect logic modules within the CLB.
Figure 2 – 02: basic configuration of logic blocks (CLB).

Logic modules: A logic module in an FPGA logic block can be configured for combinational logic,
registered, or a combination of both. A flip-flop is part of the associated logic and is used for registered
logic.

Figure 2 – 03: typical LUT-based logic module.

Generally, the organization of an LUT consists of a number of memory cells equal to 2n, where n is the
number of input variables.

2. SRAM –BASED FPGAs

FPGAs are either nonvolatile because they are based on antifuse technology or they are volatile because
they are based on SRAM technology. Therefore, SRAM – Based FPGAs, include either a nonvolatile
configuration memory embedded on the chip to store the program data and reconfigure the device each
time the power is turned back on or they use an external memory with data transfer controlled by a host
processor.
 (a) Volatile FPGA with on – the – chip nonvolatile configuration memory.

(b) Volatile FPGA with on – board memory and host processor

Figure 2 – 05: basic concept of volatile FPGA configurations (a) and (b).

3. FPGA Cores

FPGAs, as we have seen, are essentially like “blank slate” that the end user program for any logic design.
FPGAs are available that also contain hard – core logic. A hard – core is a portion of logic in an FPGA
that is put in by the manufacturer to provide a specific function and that can not be reprogrammed. If the
embedded function has some reprogrammable features, it is known as soft – core function.

An advantage of the hard – core approach is that the same design can be implemented using much less in
the available capacity of the FPGA than if the user programmed it in the field, resulting in less space on
the chip (“real estate”) and less development time for the user. The disadvantage of the hard – core is that
the specifications are fixed during manufacturing and the user must be able to use the hard – core logic
‘as is’. It can not be changed.
Figure 2 – 06: basic idea of a hard – core function embedded in an FPGA.

Those FPGAs containing either or both hard – core and soft – core embedded processors and other
functions are kwon as platform FPGAs because they can be used to implement an entire system without
the need for external support devices.

PART II: PROGRAMMABLE LOGIC SOFTWARE

I. PROGRAMMING PROCESS

In order to be useful, programmable logic must have both hardware and software components combined
into a functional unit. All manufactures of SPLDs, CPLDs, and FPGAs provide software support for each
hardware devices. These software packages are known in category of computer aided design (CAD).

1. PROGRAMMING PROCESS

An SPLD, CPLD, or FPGA can be thought of as a “Blank Slate” on which you implement a
specified circuit design or system design using a certain process. This process requires a software
development package installed on a computer to implement a circuit design in the programmable
chip. The computer must be interfaced with development board or fixture containing the device.

The programming process is generally referred as “design flow”. The device being programmed is
usually referred to as “Target device”. A basic design flow diagram for implementing a logic design
in a programmable device is shown in the above figure.

Figure 3 – 01: general design flow diagram for programming an SPLD, CPLD, or FPGA.

The design flow consists of several steps, which are the following:

• Design entry.

This is the first programming step. The circuit or system design must be entered into the design
application software using text-based entry:
Or graphic entry (schematic capture):

or state diagram description. Design entry is device independent. Text-based entry is accomplished using
a hardware description language (HDL) such as VHDL, Verilog, AHDL, or ABEL. Graphic (schematic)
entry allows prestored logic function from a library to be selected, placed on the screen, and then
interconnected to create a logic design. State diagram entry requires specification of both the states
through which a sequential logic circuit progresses and the conditions that produces each state change.

Once a design has been entered, it is compiled. The source code is created during design entry, and the
object code is the final code that actually causes the design to be implemented in the target device.
 • Functional simulation.

The entered and compiled design is simulated by software to confirm that the logic design function as
expected. The simulation will verify that correct outputs are produced for a specified set of inputs. A
device-independent software tool for doing this is generally called a “Waveform editor”.

Any flaws demonstrated by the simulation would be correct by going to the design entry and making
appropriate changes.

• Synthesis.

“Synthesis” is where the design translated into a netlist, which has a standard form and is device
independent.

• Implementation.

“Implementation” is where the logic structures described by the netlist are mapped into the actual
structure of the specific device being programmed. The implementation is called “fitting” or “place and
route” and results in an output called bitstream, which is device dependent.

• Timing simulation.

The timing simulation is basically used to confirm that there are no design flaws or timing problems due
to propagation delays.

• Device programming (Download).

Once a bitstream has been generated for a specific programmable device, it has to be downloaded to the
device to implement the software design in hardware. Some programmable devices have to be installed in
a special piece of equipment called a “device programmer” or on a development board. Other types of
devices can programmed while in a system – called “in-system programming (ISP)” – using a standard
JTAG (Joint Test Action Group) interface.