VLSI All Programs Assembly

TABLE OF CONTENT
1. Introduction to Hardware Descriptive Language & their software.

2. Write and simulate VHDL code for logic gates.
3. Implement Half Adder using VHDL.
4. Implement Full Adder using VHDL.
5. Implement Full Adder using two Half Adders.
6. Implement Half Subtractor and Full Subtractor using VHDL.
7. Implement Ripple Carry Adder usinf Full Adder in VHDL.
8. Implement 2x4 and 3x8 decoders using VHDL.
9. Implement 8x3 encoder using VHDL.
10. Implement 4x1 Multiplexer using VHDL.
11. Implement 4x2 Priority Encoder using VHDL.
12. Implement various Code Converters using VHDL.
1.Write a short note on Introduction to Hardware Descriptive
Languages and their softwares.
Hardware description language (HDL) is a specialized computer language used to program electronic
and digital logic circuits. The structure, operation and design of the circuits are programmable using
HDL. HDL includes a textual description consisting of operators, expressions, statements, inputs and
outputs. Instead of generating a computer executable file, the HDL compilers provide a gate map.
The gate map obtained is then downloaded to the programming device to check the operations of
the desired circuit. The language helps to describe any digital circuit in the form of structural,
behavioural and gate level.
The three common HDLs are Verilog, VHDL, and SystemC. The HDLs allow fast design and better
verification. In most of the industries, Verilog and VHDL are common. Verilog, one of the main
Hardware Description Language is used for designing all types of circuits. It consists of modules and
the language allows Behavioural, Dataflow and Structural Description. VHDL (Very High Speed
Integrated Circuit Hardware Description Language) is standardized by IEEE1164. The design is
composed of entities consisting of multiple architectures. SystemC is a language that consist a set of
C++classes and macros. It allows electronic system level and transaction modelling.
Need for HDLs

Complex digital circuit designs require more time for development, synthesis, simulation and
debugging. The arrival of HDLs has helped to solve this problem by allowing each module to be
worked by a separate team.
All the goals like power, throughput, latency (delay), test coverage, functionality and area
consumption required for a design can be known by using HDL. As a result, the designer can make
the necessary engineering tradeoffs and can develop the design in a better and efficient way.
HDL Structure & Design

Generally, HDL structure consist a textual description involving many inputs, outputs, signals
operators, components, multiple architectures, and comments. Concurrent and sequential way of
programming style is possible in HDL. Each and every HDL uses a different structure and design
method.
Different Types of HDLs

Different HDLs are available for describing analog circuits, digital circuits and PCBs.
HDLs for digital circuit design: Other than Verilog, VHDL and SystemC many HDLs are available for
digital circuits. Among them, `Advanced Boolean Expression Language (ABEL) is better for
programming PLDs (Programmable Logic Devices). Bluespec, a high level functional programming
HDL language is developed to handle chip design and automation systems. Bluespec System
Verilog(BSV) uses syntax similar to Verilog HDL. C-to-Verilog is generally a converter which helps to
convert C to Verilog language. Constructing Hardware in a Scala Embedded Language
(Chisel), MyHDL and HHDL are HDLs used to support advanced hardware design.
Compiler for Universal Programming Language (CUPL) is generally used for logic device
programming. Handel-C is used for programming FPGA’s. Hardware Join Java (HJJ) helps in
reconfigurable computing applications. Impulse C, subset of C supports parallel programming. Just-
Another Hardware Description Language (JHDL) uses an object oriented programming
approach. LavaHDL helps in specifying layout of circuits mainly. Lola HDL is basically used for
synchronous digital circuits. M, is another HDL from Mentor Graphics. PALASM is used as a HDL for
Programmable Array Logic (PAL) devices. Finally System Verilog is an extension to Verilog.
HDLs for analog circuit design: The HDLs used for analog circuits include Analog Hardware
Description Language (AHDL), Spectre High Level Description Language (SpectreHDL), Verilog for
Analog and Mixed Signal (Verilog – AMS), VHDL with analog and mixed signal extension (VHDL –
AMS) and finally HDL-A. AHDL is most commonly used as a HDL language for analog circuits.
SpectreHDL is a high level description language that uses functional description text files to model
the behaviour of the systems. Verilog-AMS is an industry standard modelling language that contains
continuous an event driven simulators for analog, digital and analog/digital circuits. VHDL-AMS is
good for verifying complex analog, mixed signal and RF (radio frequency) circuits. HDL-A is a
proprietary HDL for mixed and analog circuits.
HDL for Printed Circuit Design: PHDL (Printed Circuit Board HDL) is generally used for modeling text
based schematics for PCBs. It allows generating massive buses and re-uses device definitions easily.
Benefits of HDL
The major benefit of the language is fast design and better verification. The Top-down design and
hierarchical design method allows the design time; design cost and design errors to be reduced.
Another major advantage is related to complex designs, which can be managed and verified easily.
HDL provides the timing information and allows the design to be described in gate level and register
transfer level. Reusability of resources is one of the other advantages.
1. Write and simulate the VHDL code for logic gates.
And Gate :
entity aand1_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end aand1_gate;
architecture Behavioral of aand1_gate is
begin
c <= a and b;
end Behavioral;
OR GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity oor2_gate is
c : out STD_LOGIC);
end oor2_gate;
architecture Behavioral of oor2_gate is

begin
c <= a or b;
end Behavioral;
NOT GATE
library IEEE;
entity nnot3_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end nnot3_gate;
architecture Behavioral of nnot3_gate is
begin
b <= not a ;
end Behavioral;
NAND GATE
library IEEE;
entity nnand3_gate is
c : out STD_LOGIC);
end nnand3_gate;
architecture Behavioral of nnand3_gate is
begin
c <= a nand b;
end Behavioral;
NOR GATE:
library IEEE;
entity nnor1_gate is
Port ( a ,b : in STD_LOGIC;
c : out STD_LOGIC);
end nnor1_gate;
architecture Behavioral of nnor1_gate is
begin
c <= a nor b;
end Behavioral;
.
Xor Gate :
entity xxor1_gate is
c : out STD_LOGIC);
end xxor1_gate;
architecture Behavioral of xxor1_gate is
begin
c <= a xor b;
end Behavioral;
3.Write a program to implement Half adder using VHDL.
entity h_add is
c,s : out STD_LOGIC);
end h_add;
architecture Behavioral of h_add is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
2. Write a program to implement Full Adder using VHDL
library IEEE;
entity wwxfa is
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
car : out STD_LOGIC);
end wwxfa;
architecture Behavioral of hagd is
begin
s<=a xor b xor c;
car<= (a and b) or (b and c) or (c and a);
end Behavioral;
5.Implement Full Adder by using two half adders
entity full_adder1 is
Port ( x,y,z : in STD_LOGIC;
t,u : out STD_LOGIC);
end full_adder1;
architecture Behavioral of full_adder1 is

component half_adder is
port (a,b :in std_logic;
s,c : out std_logic);
end component;
component oor1_gate is
port (p,q : in std_logic;
r : out std_logic);
end component;
signal s1 ,s2,s3 : std_logic;
begin
HA1 : half_adder port map (x,y,s1,s2);
HA2 : half_adder port map (s1,z,t,s3);
OR1 : oor1_gate port map(s2,s3,u);
end Behavioral;
6. Write a program to implement Half subtractor and Full subtractor

using VDHL
library IEEE;
---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hs_hs1 is
b : in STD_LOGIC;
d : out STD_LOGIC;
bor : out STD_LOGIC);
end hs_hs1;
architecture Behavioral of hs_hs1 is
begin
d<= a xor b;
bor<= a and not b;
end Behavioral;
FULL SUBTRACTOR
library IEEE;
--library UNISIM;
entity de is
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC;
bor : out STD_LOGIC);
end de;
architecture Behavioral of de is
begin
d<= a xor b xor c;

bor<= (not a and b) or (b and c) or(c and not a);
end Behavioral;
7. Write a program to implement Ripple Carry Adder using Full adder
in VHDL
library IEEE;

--library UNISIM;
entity RCA is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : in STD_LOGIC_vector(3 downto 0);
ci : in STD_LOGIC;
sum : out STD_LOGIC_vector(3 downto 0);
carry : out STD_LOGIC);
end RCA;
architecture Behavioral of RCA is

component full_add
port (x:in STD_LOGIC;
y:in STD_LOGIC;
z:in STD_LOGIC;
s:out STD_LOGIC;
c:out STD_LOGIC);
end component;
signal s1,s2,s3: STD_LOGIC;
begin
FA1: full_add port map( A(0), B(0), ci, sum(0), s1);
FA2: full_add port map( A(1), B(1), s1, sum(1), s2);
FA3: full_add port map( A(2), B(2), s2, sum(2), s3);
FA4: full_add port map( A(3), B(3), s3, sum(3), carry);
end Behavioral;
8. Write a program to implement 2x4 and 3x8 Decoder using VHDL(
Structural,Behavioral and Dataflow modelling)
2x4 Decoder
Structural
library IEEE;
entity dec2x4 is
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
w : out STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC);
end dec2x4;
architecture Behavioral of dec2x4 is

component and_gt is
port( a,b: in std_logic;
c:out std_logic);
end component;
begin
k1:and_gt port map(not p,not q,w);
m1:and_gt port map(not p, q,x);
kk1:and_gt port map( p,not q,y);
p1:and_gt port map( p, q,w);
end Behavioral;
Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder1 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0) );
end decoder1;
architecture bhv of decoder1 is
begin
process(a)
begin
if (a="00") then
b <= "0001";
elsif (a="01") then
b <= "0010";
elsif (a="10") then
b <= "0100";
else
b <= "1000";
end if;
end process;
end behavioral;
Dataflow
library IEEE;
entity dec1 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b: out STD_LOGIC_VECTOR (3 downto 0));
end dec1;
architecture Behavioral of dec1 is

begin
b(0)<=(not a(0) and not a(1));

b(1)<=(not a(0) and a(1));
b(2)<=( a(0) and not a(1));
b(3)<=( a(0) and a(1));
end Behavioral;
3x8 DECODER
Structural
entity dec3x8 is
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
r : in STD_logic;
s: out STD_LOGIC;
t: out STD_LOGIC;
u: out STD_LOGIC;
v: out STD_LOGIC;
w : out STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC);
end dec3x8;
architecture Behavioral of dec3x8 is

component and_gt is
port( a,b,c: in std_logic;
d:out std_logic);
end component;
begin
k_1:and_gt port map(not p,not q,not r,s);
u_2:and_gt port map(not p, not q,r,t);
n_3:and_gt port map( not p, q,not r,u);
a_4:and_gt port map( not p, q,r,v);
l_5:and_gt port map( p, not q,not r,w);
kk_6:and_gt port map( p, not q,r,x)
p_6:and_gt port map( p, q,not r,y);
r_7:and_gt port map( p, q,r,z);
end Behavioral;
Behavioral
library IEEE;
entity decoder2 is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : out STD_LOGIC_VECTOR(7 downto 0) );
end decoder2;
architecture behavioral of decoder2 is
begin
process(a)
begin
if (a="000") then
b <= "00000001";
elsif (a="001") then
b <= "00000010";
b <= "00000100";
b <= "00001000";
b <= "00010000";
b <= "00100000";
b <= "01000000";
b <= "10000000";
end if;
end process;
end behvioral;
DATAFLOW
library IEEE;
entity dec2 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b: out STD_LOGIC_VECTOR (7 downto 0));
end dec2;
architecture Behavioral of dec2 is

begin
b(0)<=(not a(0) and not a(1) and not a(2));

b(1)<= (not a(0) and not a(1) and a(2));
b(2)<= (not a(0) and a(1) and not a(2));
b(3)<= (not a(0) and a(1) and a(2));
b(4)<= ( a(0) and not a(1) and not a(2));
b(5)<= (a(0) and not a(1) and a(2));
b(6)<= ( a(0) and a(1) and not a(2));
b(7)<= ( a(0) and a(1) and a(2));
end Behavioral;
9. Implement 8x3 encoder using VHDL (Structural,Behavioral and Dataflow
modelling)
Behavioural
library IEEE;
entity encoder8to3 is
port (din : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC_VECTOR(2 downto 0)
);
end encoder8to3;
architecture Behavioral of encoder8to3 is
begin
dout <= "000" when (din="10000000") else
"001" when (din="01000000") else
"010" when (din="00100000") else
"011" when (din="00010000") else
"100" when (din="00001000") else
"101" when (din="00000100") else
"110" when (din="00000010") else
"111";
end Behavioral;
DATAFLOW
library IEEE;
entity encoder8to3 is
port(
a : in.STD_LOGIC_VECTOR(7 downto 0)
b : out.STD_LOGIC_VECTOR(2 downto 0)
);
end encoder8to3;
architecture behavior of encoder8to3 is
begin
b(0) <= d(4) or d(5) or d(6) or d(7);
b(1) <= d(2) or d(3) or d(6) or d(7);
b(2) <= d(1) or d(3) or d(5) or d(7);
end behavioral;
STRUCTURAL
entity enc8x3 is
Port ( p : out STD_LOGIC;
q : out STD_LOGIC;
r : out STD_logic;
s: in STD_LOGIC;
t: in STD_LOGIC;
u: in STD_LOGIC;
v: in STD_LOGIC;
w : in STD_LOGIC;
x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC);
end enc8x3;
architecture Behavioral of enc8x3 is

component or_gt is
port( a,b,c,d: in std_logic;
e:out std_logic);
end component;
begin
w_1:or_gt port map(t,v,x,z,p);
w_2:or_gt port map(u,v,y,z,q);
w_3:or_gt port map(w,x,y,z,p);
end behavioural;
10. Write a program to implement 4x1 MUX using VHDL.
STRUCTURAL
entity mux4x1 is
Port ( i0,i1,i2,i3 : in std logic;
s1 : in STD_LOGIC;
s0: in STD_LOGIC;
o: out std_logic);
end mux4x1;
architecture Behavioral of mux4x1 is

component and_gt is
port( a,b,c: in std_logic;
d:out std_logic);
end component;
component or_gt is
port( a1,b1,c1,e1: in std_logic;
d1:out std_logic);
end component;
signal sig1,sig2,sig3,sig4 : std_logic;
begin
k_1:and_gt port map(i0,not s0,not s1,sig1);
k_2:and_gt port map(i1,not s0, s1,sig2);
k_3:and_gt port map(i2,s0,not s1,sig3);
k_4:and_gt port map(i3,s0,s1,sig4);
m_5:or_gt port mao(sig1,sig2,sig3,sig4,0);
end behavioral;
BEHAVIORAL
library IEEE;
entity mx41 is
Port ( o : in std_logic_vector(3 downto 0);
u : out std_logic;
b : in std_logic_vector(1 downto 0));
end mx41;
architecture mx of mx41 is
begin
process(o,b)
begin
case b is
when "00"=>
u<=o(0);
when "01"=>
u<=o(1);
when "10"=>
u<=o(2);
when others=>
u<=o(3);
end case;
end process;
DATAFLOW
library IEEE;
entity mux41 is
Port ( s : in STD_LOGIC_VECTOR (1 downto 0);
i : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC);
end mux41;
architecture Behavioral of mux41 is

begin
y<= (not s(1) and not s(0) and i(0)) or (not s(1) and s(0) and i(1)) or (s(1) and not s(0) and i(2)) or (s(1)
and s(0) and i(3));
end Behavioral;
11. Program to implement 4x2 Priority Encoder in VHDL.
library IEEE;

--library UNISIM;
entity prenc is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : out STD_LOGIC_vector(1 downto 0);
en : in STD_LOGIC);
end prenc;
architecture Behavioral of prenc is

begin
process (a,en)
begin
if en ='1' then
case a is
when "1000" => b <= "11";
when "0100" => b <= "10";
when "0010" => b <= "01";
when "0001" => b <= "00";
when others => b <= "00";
end case;
else
b <= "00";
end if;
end process;
end Behavioral;
12. Write programs to implement the following code converters in VHDL.
A) Binary code to Gray code converter
library IEEE;

--library UNISIM;
entity btg is
Port ( b : in STD_LOGIC_vector(3 downto 0);
g : out STD_LOGIC_vector(3 downto 0));
end gtb;
architecture Behavioral of btg is
begin
g(3)<= b(3);
g(2)<= b(3) xor b(2);
g(1)<= g(2) xor g(1);
g(0)<= g(1) xor g(0);
end Behavioral;
B)Gray code to Binary code coverter
library IEEE;

--library UNISIM;
entity gtb is
Port ( g : in STD_LOGIC_vector(3 downto 0);
b : out STD_LOGIC_vector(3 downto 0));
end gtb;
architecture Behavioral of gtb_2 is
begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(3) xor g(2)xor g(1);
b(0)<= g(3) xor g(2)xor g(1) xor g(0);
end Behavioral;
C) BCD to 7segment code converter
library IEEE;

--library UNISIM;
entity seven is
Port ( bcd : in STD_LOGIC_vector(3 downto 0);
seg7 : out STD_LOGIC_vector(6 downto 0));
end seven;
architecture Behavioral of seven is
begin
process(bcd)
begin
if(bcd="0000") then
seg7<="1111110";
elsif(bcd="0001") then
seg7<="0000110";
seg7<="1011011";
seg7<="1001111";
seg7<="0100111";
seg7<="1101101";
seg7<="1111101";
seg7<="1000110";
seg7<="1111111";
seg7<="1101111";
else seg7<="0000000";
end if;
end process;
end Behavioral;
D) BCD to Excess-3 code converter
library IEEE;

--library UNISIM;
entity xs3 is
Port ( bcd : in STD_LOGIC_vector(3 downto 0);
exst : out STD_LOGIC_vector(3 downto 0));
end xs3;
architecture Behavioral of xs3 is
begin
process(bcd)
begin
if(bcd="0000") then
exst<="0011";
exst<="0100";
exst<="0101";
exst<="0110";
exst<="0111";
exst<="1000";
exst<="1001";
exst<="1010";
exst<="1011";
exst<="1100";
end if;
end process;
end Behavioral;

VLSI All Programs Assembly

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VLSI All Programs Assembly

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TABLE OF CONTENT

1. Introduction to Hardware Descriptive Language & their software.

Need for HDLs

HDL Structure & Design

Different Types of HDLs

1. Write and simulate the VHDL code for logic gates.

architecture Behavioral of aand1_gate is

architecture Behavioral of oor2_gate is

architecture Behavioral of nnand3_gate is

architecture Behavioral of xxor1_gate is

architecture Behavioral of h_add is

architecture Behavioral of hagd is

architecture Behavioral of full_adder1 is

6. Write a program to implement Half subtractor and Full subtractor

---- Uncomment the following library declaration if instantiating

architecture Behavioral of hs_hs1 is

d<= a xor b xor c;

---- Uncomment the following library declaration if instantiating

architecture Behavioral of RCA is

architecture Behavioral of dec2x4 is

architecture Behavioral of dec1 is

b(0)<=(not a(0) and not a(1));

architecture Behavioral of dec3x8 is

architecture Behavioral of dec2 is

b(0)<=(not a(0) and not a(1) and not a(2));

architecture Behavioral of encoder8to3 is

architecture Behavioral of enc8x3 is

architecture Behavioral of mux4x1 is

architecture Behavioral of mux41 is

---- Uncomment the following library declaration if instantiating

architecture Behavioral of prenc is

A) Binary code to Gray code converter

---- Uncomment the following library declaration if instantiating

architecture Behavioral of btg is

---- Uncomment the following library declaration if instantiating

architecture Behavioral of gtb_2 is

---- Uncomment the following library declaration if instantiating

architecture Behavioral of seven is

---- Uncomment the following library declaration if instantiating

architecture Behavioral of xs3 is

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