EE332 Design Project

“Variable Gain Amplifier with Output Stage

Optimization for Audio Amplifier Applications”

Instructor: Nguyen Trung Kien

Students: Do Nam Son

Nguyen Ngoc Hoang

Nguyen Thi Ngoc Dieu

I. Introduction
The project mainly focuses on designing an audio amplifier that can take the input from a
CD player or portable music player and amplify the signal to drive a loudspeaker with
variable gain. We are going to use all useful knowledge of EE 332 class to finish the
acquired job. Discrete BJTs, resistors and balanced voltage source are chosen to build such a
OCL (Output Capacitor Less) power amplifier with 3 different stages. The circuit is
constructed on Pspice first, and then implemented on the real board. After doing the demo,
we conclude that the designed circuit meets most of requirements.

II. Architecture Design

1. Design specifications
a. Input signal specifications:
 Signal voltage: 100mV pkpk (min) – 5.6V pkpk (max)
 Signal source resistance 50 Ω
 Equipment available for testing:
 Hardware: Oscilloscope, DMM, Signal generator, power supply +/-10 V DC
 Software: PSPICE, HSPICE etc.
b. Minimum Design Specifications of the amplifier:
 Output power: 0.5W (minimum)
 Load Impedance (speaker): 8Ω
 Unity Gain Bandwidth: 20Hz – 20 kHz (-3dB)
 Idling power: < 1W
 Distortion: No audible distortion in casual listening

2. Block Diagrams
3. Discussion on the chosen architecture

Firstly, we review all needed knowledge of the course, find the references on the Internet
and other hard copies from former students. Then we decide to choose the suitable OCL
(Output Capacitor Less) architecture with 3 stages that related to the knowledge that we
obtain. The circuit has to be able to amplifier current, voltage and results in an overall power
amplifier. After finding appropriate architecture, we continue to study carefully all of the
materials and complete the chosen architecture step by step. During the process, we usually
check all the circuit components to make sure whether the designed circuit behaves as the
expected way.

4. Trade offs

There are a lot of discussion between members in our group during the project. Firsly is
whether we should choose OTL or OCL circuit, which one is better? Secondly is the class
stage, which is the most efficiency model. Protecting circuit such as Zobel is also considered
carefully. Morever, we try to manipulate the capacitors to obtain desired bandwidth (20-
20kHz). When we build real circuit, in the first steps, we choose the transistors that don’t
have enough ability to suffer heat, hence the board is melted. Fortunately, we fix this
problem soon and do quite well in the fixed circuit.

III. Circuit Design

1. Schematic
 2. Design equations and calculations

All of the equations and calcultations are attach by the excel table below

3. Simulation results: input signal amplitude 0.5V, output signal amplitude 5V, voltage gain
is 10 as expected.
IV. Results
a. Bandwidth
flow

fhigh

b. Maximum Output Power

- What is the largest Vpk-pk on output that is not distorted/clipping and greater than or equal
to .5W while achieving -3dB bandwidth of 20Hz-20KHz?

Idling power
- DC power used with no input
Cost/Parts Count
- How many BJTs did you use?
We use 11 BJTs in total, 5 for the first stage, 2 for the second stage and 4 for the third stage.
- Count up total parts and submit cost

20* LOG10(ABS(V(out)/V(in)))