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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 6: -
Problem Definition: - Design has 1 clock domain with DFFs and latches and insert 3 scan
chains
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue? We have to insert three scan chains
How resolved? insert test logic -number 3
Observations: -
1) Write block diagram with all DFT inputs?

FastClk

ProcClk
Reset
Input Scan channel Output Scan channel
Top Design: cntl2
Scan_En
Scan_chain Input1 chainout1
Scan_chain Input2 chainout2
Scan_chain input3 chain out3

2) How many clock domains? ProcClk, FastClk


3) How many resets? Reset
4) Number of scan chains 3 scan chains

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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

5) Clock mixing or not clock mixing? Not clock mixing


6) How many Lockup-latches are added during scan insertion? zero
7) Is it top-down or bottom up approach? Top-down approach
8) How many terminal lockup latches are added? zero
9) Number of scan flops and non-scan flops in the design? 102 scanable flops and 0 non-
scan elements
10) Chain length? 3(total 102 memory elements)
domain[0] #cells:34, #chains:1
domain[1] #cells:34, #chains:2
domain[2] #cells:34, #chains:3

11) Number of DRC violations? C8,C9 (warning only)

12) Log file: - please note your observations from the log file
Top module is cntl12
Number of shift registers =25
Longest have 3 flop
Shortest have 2 flop
No of no scan memory element =102
No of non scan memory element converted to scanable =102
Number of new Pins inserted= 7 (3 scan inputs, 3+ scan outputs, scan_en )

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