An event that causes processor to halt
What are interrupts? what it is doing, and execute an interrupt
service routine (ISR)
What is CSL and BSL?
Sources of interrupts include:
Using AD535 codec Timers
Output sine to DSK codec via serial port External interrupts
DMA (direct memory access)
Using Interrupts McBSP transmit or receive
Use serial port interrupt to synchronize
sinewave sample output
A master switch can be used to turn bsl_ad535.h Chip Support Library (CSL)
all interrupts on or off (Global Enable bsl_led.h Low-level routines supporting on-chip peripherals
sineGen °±²
AD535 sineGen McBSP °±²
AD535
· (AD535
)*'?3 ('
Codec McBSP Block Diagram
McBSP0
¸¹º ³´µ ¶ RINT
DXR
XSR XINT
¹¸º ³´µ ¶
RSR
DRR CPU
D R
Fs = 8KHz R Expand B RSR DR
P (optional)
e R R 32
CLKR
r
CLKX i
p D Compress
clock h X (optional) XSR DX
4 .#3(*(' e R
AD535 BSL r
0 4RS*Rf (+ U»= 9 E()* E(9 '.E =*'- ;)((+ U E(9 '.0 4¼RS*R & 9 :;'* '9 = a
=E)3?=? (&E( 7 E( &E( U =g*' )½ l CLKR
0 4RS*Rf !(-( '¾E='-? 9 '<+ '9 '*()*'. 3 '?0 4¼RS*R ) -(' B
u
CLKX
0 4RS*Rf (&Sample
'*(e j29 '=*'rate
9 /*'=.9 '<is=hard-wired
E(9 )'.(-9 ' E(9 to
=.3*8(-(kHz
' s McBSP Control
CLKS
0 4RS*Rf )((+ U(e j¿)(+ U E(9 '<=?0 4#R<SR (- 8 )F¼$GÀ DMA Registers
FSR
REVT
0 4RS*Rf 9 '*-e jÁ9 '- =.+ 9 (:V0 4¼RS*R 0 4 W 3(9 E 8 )F#G$À.9 ')*' /*' FSX
XEVT
0 4RS*Rf LM9 'e jaLM9 '=. ;0 4#R*SR.4 0#Â 39 E 8 )F¼$GÀ? 9 (=:
" '9 9 E&(h'9 / )'_C#(E( ' " ( '9 9 E(&(G'9 / )'_CE( ('
)//
(-('*) f (E e j )//
-('*) f (E( e j
à 0 4RS*Rf LM9 'e 3 (- 'g*= 'ÄM' e j j Å Ã 0 4RS*Rf LM9 'e 3 -( 'g*= 'ÄM' e j j Å Note underscore
Æ Æ before C function
name