SREENIVASA INSTITUTE of TECHNOLOGY AND MANAGEMENT STUDIES

AUTONOMOUS: CHITTOOR
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
III Year B.Tech. II semester L T P C
0 0 3 2
16ECE317 DIGITAL DESIGN THROUGH VERILOG HDL LAB

Course Educational Objectives:

CEO1: To gain the knowledge and analyze the steps involved in synthesis and simulation of verilog
HDL code.
CEO2: To design and developing testbenches to verify the functionality of combinational logic
designs using various levels like
 To construct basic building blocks using Data flow modeling
 To construct adders ann subtractors , MUX and DEMUX in structural and behavioral
modfeling styles.
CEO3: To design and developing testbenches to verify the functionality of sequential logic designs
using various levels like
 To construct flipflops and latches, counters and shift registers using structural and
behavioral modfeling styles.
CEO4: To understand the basic knowledge of FPGA and implementation on it.

LIST OF EXPERIMENTS
Minimum 10 experiments to be conducted:
Design of Combinational Circuits:
1. Design and simulation of basic gates and universal gates: NOT, AND, OR, NAND, NOR,
XOR and XNOR using data flow modeling.
2. Design and simulation of Half Adder and 1 - bit Full Adder using structural and behavioral
modelings.
3. Design and simulation of Half Subtractor and 1 - bit Full Subtractor using structural and
behavioral modelings.
4. Design and simulation of 8-bit Ripple Carry Adder using structural and behavioral elements.
5. Design and simulation of 8:1 MUX and 1:8 DEMUX using structural and behavioral (using
Case Statement) modelings.
6. Design and simulation of 3to 8 Decoder and 8 to 3 Encoder using data flow and structural
modelings.
Design of Sequential Circuits:
7. Design and simulation of D-Latch (single-if statement) and D-flip-flop (if-else statement)
8. Design and simulation of 4 bit upcounter and downcounter using nested if-else-if statements.
9. Design and Simulation of 4-bit Shift Register.
10. Design of 4 bit ALU with addition, subtraction, multiplication, division, AND, OR, XOR and
XNOR operations.
FPGA Implementation:
11. Implementation of Universal Gates using FPGA.
12. Implementation of D-flip-flop using FPGA.

Course Outcomes:
On successful completion of the course the student will be able to,
Course Outcomes POs related to COs

CO1 Ability to design any basic building blocks and simulate any digital PO1, PO2, PO3,PO5
function in verilog HDL.
CO2 Get practical experience on how to design combinational logic designs PO1, PO2, PO3, PO4,
with the help of Verilog HDL PO5
CO3 Get practical experience on how to design sequential logic designs with the PO1, PO2, PO3, PO4,
help of Verilog HDL PO5
CO4 Test the functionality of any digital systems by implementing it on FPGA PO1, PO2, PO3, PO4,
Board. PO5