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Analysis and Design of Regenerative Comparators

for Low Offset and Noise
Hao Xu , Member, IEEE, and Asad A. Abidi , Fellow, IEEE

Abstract— We make the case that in most comparators, offset

and noise are determined by a dynamic preamplifier always
embedded ahead of a regenerative latch. An analysis of this
amplifier follows, from which simple expressions are obtained
for input-referred offset and noise bandwidth. Practical circuit
methods to compensate offset and lower noise become evident.
We compare the StrongArm comparator with the double tail
topology, and identify requirements for correct operation.
Index Terms— Latches, circuit noise, analog-digital conversion,
analog-digital integrated circuits, coupled mode analysis, circuit
theory. Fig. 1. Conceptual dynamic amplifier.
I. I NTRODUCTION
noise and offsets contributed by the regenerative latch that fol-
C OMPARATORS are used everywhere in electronic cir-
cuits. Regenerative comparators guarantee a binary out-
put (except for inputs in a very small window) and low power
lows. If offsets and noise in the regenerative sub-circuit cannot
be overcome, then [2] gives a framework for their analysis.
consumption. Comparators based on a cascade of high gain A. Gain
amplifiers [1, Ch. 8] are seldom found any longer in mixed-
For our purposes, the simplest model of a balanced dynamic
signal IC’s that contain clocked circuits. Instead, compact
amplifier is a differential pair biased with current I0 , with
circuits that consume zero static power are almost universally
equal grounded capacitors C attached to the drains (Fig. 1).
in use.
Two switches pre-charge the capacitors to the supply volt-
Despite a large number of publications, offsets and noise
age V D D . While a static differential input voltage v id =
in the regenerative comparator have not been systematically
VG1 − VG2 is being applied, the switches are opened and
analyzed in ways that give direct insights immediately useful
amplification starts. This phase lasts for a time window tw
for design. In this paper we present a systematic design-
usually defined by the time required for the average (common-
oriented analysis for regenerative comparators. This work
mode) voltage 12 (VO1 + VO2 ) at the two drains to fall by some
builds on and extends our previous work [2].
predetermined amount Vt . Thus,
II. DYNAMIC A MPLIFIERS C Vt
tw = 1
. (1)
To analyze the class of comparators in widespread use today 2 I0
we must first understand the properties of a dynamic amplifier.
All modern comparators use implicit dynamic preamplification Suppose each FET is sized so that it needs a minimum
before they regenerate, except for special cases like the mem- voltage V D S AT to operate in saturation. Then gm /I0 =
ory sense amplifier which for reasons of extreme compactness 1/V D S AT , where gm is associated with a single FET. Over tw ,
eliminates a preamplifier. the differential current 12 gm v id integrates on the differen-
A dynamic amplifier is a low-power circuit that amplifies tial capacitance 12 C to create a differential output voltage
a static input voltage by converting it into a current, then [3, Eq. (40)]
integrates that current on a capacitor over a well-defined time gm 21 v id tw 2Vt
window [3, Sec. 5]. Since a comparator detects only the sign v od = 1
= v id (2)
of a (small) input voltage, the preamplifier need not be linear, 2C
V D S AT
only that its output should preserve the sign of the input. This
We assume that the FETs operate in saturation throughout.
means that its own offset and noise should be small, and that
This simple model requires that by some means, I0 will cease
it should scale up the input voltage sufficiently to overcome
to flow for t > tw , when the amplification phase is complete.
Manuscript received September 3, 2018; revised December 21, 2018, Then from (2) the voltage gain of the dynamic amplifier is
March 3, 2019, and March 24, 2019; accepted March 25, 2019. This paper the ratio of two bias voltages, one of which, V D S AT , may be
was recommended by Associate Editor E. Bonizzoni. (Corresponding author: selected by design.
Hao Xu.)
H. Xu was with the Electrical and Computer Engineering Department,
University of California at Los Angeles, Los Angeles, CA 90095-1594 USA. B. Circuit Unbalances
He is now with Broadcom, Irvine, CA 92618 USA (e-mail: haoxu@ucla.edu). We will show that in a well-designed comparator, transistor
A. A. Abidi is with the Electrical and Computer Engineering Department, mismatches in the input stage of the dynamic preamplifier
University of California at Los Angeles, Los Angeles, CA 90095-1594 USA.
Color versions of one or more of the figures in this paper are available
determine the overall offset. To calculate these offsets, we must
online at http://ieeexplore.ieee.org. develop models of small mismatches between the symmetric
Digital Object Identifier 10.1109/TCSI.2019.2909032 pairs of elements making up the balanced circuit of a dynamic
1549-8328 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 2. Modeling mismatch pair of FETs as balanced circuit with internal
differential current.
Fig. 3. Modelling capacitor mismatch in a balanced circuit.
amplifier. Each source of mismatch can be analyzed separately
and, as long as they are small, their effects on the output
added algebraically; in other words, superposition applies.
We follow Middlebrook [4] in modelling unbalances due
to mismatch with differential-mode currents inserted into an
otherwise perfectly balanced circuit free of mismatch. The
threshold voltage and current scaling factor of each MOSFET
are random variables, with mean value Vt 0 and β and standard
deviations σV t and σβ . Let the threshold voltages of M1,
M2 be Vt 1, Vt 2 (Fig. 2). Then 12 (Vt 1 + Vt 2 )  Vt 0 , and
Vt 1 = Vt 0 + 12 Vt ; Vt 2 = Vt 0− 12 Vt ; Vt = Vt 1 −Vt 2
Modelling the MOSFET with the square law,
I = β2 (VG − Vt 0 − VS )2 = β2 V D2 S AT
⇒ gm = β (VG − Vt 0 − VS )
it follows that if the same VG is being applied to the FET pair
M1, M2, then owing to mismatch in Vt ,
I (M1) = 12 (I0 − gm Vt )
I (M2) = 2 (I0
1
+ gm Vt )
These expressions are captured by an equivalent circuit
(Fig. 2(b)) consisting of a perfectly matched differential pair
with VG applied to both gate terminals, each FET conduct-
ing 12 I0 , and a current source of − 12 gm Vt attached to
the two drain terminals. In this way, mismatch is modelled
by a balanced circuit with no differential stimulus applied
to its input, that is, driven in common mode only, and an
independent differential current interpolated into the circuit
that is proportional to mismatch Vt . In other words, in a
balanced circuit topology that is biased purely in common
mode, unbalance due to component mismatch can be thought
of as creating a current that arises from “cross-coupling” [4]
of the common-mode input into a differential-mode stimulus
that models mismatch or unbalance.
Along the same lines, the mismatch β = β1 − β2 induces
another component in the differential current, whose value
is + 12 (β/β)I0 (Fig. 2(b)).
Now suppose that the FETs are perfectly matched, but
only the load capacitors are mismatched as C ± 12 C. When
the differential pair is biased with equal VG , the two FETs
will carry equal currents 12 I0 ; but these two currents flowing
into mismatched load capacitors will create voltage ramps of
unequal rates, thus a differential voltage that grows with time.
This is the same as if the capacitors are perfectly matched,
but are charged by a differential current source − 12 (C/C)I0
Fig. 4. Noise in a balanced differential pair.
between the drains of the FETs (Fig. 3). Since I0 /C described
the rate of change of drain bias, a dynamic offset is observed
that is characteristic of regenerative latches [5, Sec. 4.14] [6].
The three contributions to the differential current, all
assumed small, will superpose as
I = −12 gm Vt + 12 (β/β)I0 − 21 (C/C)I0 (8)
(8) suggests immediately that offset as captured by I may
be nulled through adjusting the fractional unbalance in capac-
itance, consistent with [6]. C, however, can take on any value.
We will show that C determines the RMS noise in the dynamic
amplifier. Thus the circuit can be designed to null offset and
independently to meet specifications on noise.
C. Noise in Dynamic Amplifier
Noise in the balanced dynamic amplifier originates in the
two FETs. We will ignore flicker noise for now, which can
be modelled as a small but slowly time-varying offset, and
(3) that sometimes can be calibrated satisfactorily along with DC
offset.
White noise occupying a very wide bandwidth is modelled
(4) by an independent current source i n between the source and
drain of a noiseless FET, with spectral density Sin = 4kTγ gm .
(5) With two FETs connected as a differential pair, noise appears
as a differential current i n,d = 12 (i n1 − i n2 ) inserted into the
same circuit branch as the differential current that models mis-
match (Fig. 4). Noting that i n1,2 are independent, the spectral
(6) density of this differential current is Sin,d = 2kTγ gm .
(7) The dynamic amplifier operates over some time window tw ,
whereupon its amplified output is passed to the next circuit
stage. While the signal current is being integrated, so is
wideband white noise. But the signal is usually static over
this window, whereas the noise current can fluctuate rapidly.
Since the amplifier starts from reset, the classic integrate-and-
dump receiver describes how it processes signal and noise.
At the end of one window, the noise will have integrated on
the capacitor to some random voltage. The integrated noise
voltage sampled at the end of many such windows will follow
a distribution whose variance, or mean square value, is given
by [7, p. 331]
Sin,d tw
v 02  = ·  2 [V2 ] (9)
2 1
2C
This shows how the capacitance C determines the mean-square
noise voltage.
III. T HE S TRONG A RM L ATCH
The widely used latching comparator circuit of Fig. 5 was
originally developed as part of a suite of low-power digital
circuits [8]. It may appear that it operates by introducing a
small differential analog current via series connection into a
pair of cross-coupled inverters. But there is more to it, as we
now explain.
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XU AND ABIDI: ANALYSIS AND DESIGN OF REGENERATIVE COMPARATORS FOR LOW OFFSET AND NOISE
Fig. 5. The StrongArm latch [8].
Fig. 6. Differential and common-mode equivalent circuits of the StrongArm
latch during (a) reset state; (b) sampling phase; (c) propagation phase;
(d) regeneration phase.
A. Overall Operation
The difference between two input voltages, each measured
with respect to ground, is coupled into the latch M3∼M6
through the NMOS pair M1-M2 biased at a gate voltage VI C
(Fig. 5). The pair is activated by the tail FET, which for now
is assumed to act like a switch. The input common-mode VI C
lies above the threshold voltage of M1, M2, and it sets the
bias current.
In due course, but not right away, this bias current will also
flow through the cross-coupled inverters M3-M5 and M4-M6
that are stacked in series. Differential current produced by
M1-M2 “unbalances” the inverters, causing them to regenerate
on this unbalance. Regeneration forces one FET in each
inverter to turn OFF, thus choking off a current flow path
through both M1 and M2. This forces M1, M2, and any tail
current FET into deep triode with V D S = 0 where they no
longer conduct current. Following this self-actuated sequence,
the comparator consumes no static power in its regenerated
state.
B. Operational Phases
The circuit’s operation should be divided into three dis-
crete phases (Fig. 6), with regeneration taking place in the
last phase [9], [2]. Over the first two phases, sampling and
propagation, the circuit amplifies the applied input voltage and
stores it onto internal nodes as an analog quantity, as we will
now explain.
3
1) Reset State: The phases are clearly identified when the
comparator is released from a well-defined initial state. The
circuit has four state variables, the voltages on two grounded
capacitors CC and on two load capacitors C L . But it is a time-
varying circuit, and when in the second and third phases the
capacitors exchange charge, the number of states collapses to
two. The circuit must be initialized with all four states at a
predetermined and fixed value so as to erase memory of the
previous regeneration. FET switches are used to precharge all
four capacitor voltages to V D D (Fig. 5). Thus the source and
drain terminals of M3∼M6 all start off at the same potential.
2) Sampling Phase: When the tail FET is initialized, the
average input voltage sets the bias current ( 12 I0 ) in M1 and M2.
This common-mode current will discharge CC1 and CC2 from
their initial voltage of V D D . M3 and M4 remain OFF until
each capacitor has discharged by the threshold voltage Vt N
(Fig. 6(b)). This interval defines the sampling phase:
CC · Vt N
Ts = 1
(10)
2 I0
Over Ts the difference in the input voltages v id is dynamically
amplified on CC . This amplified voltage serves as the initial
condition for the next phase, propagation.
3) Propagation Phase: In the propagation phase, M3 and
M4 have turned ON, and by the end of this phase the common
mode (bias) current flowing through them will have discharged
the output voltages VO1 and VO2 by |Vt P | to turn on the cross-
coupled PMOS pair M5, M6. Over this phase M1, M2 and
M3, M4 carry currents. The voltages on capacitors CC and C L
ramp down together, separated by a constant voltage difference
of VG S3(= VG S4) (Fig. 6(c)). This phase lasts for
(C L + CC )|Vt P |
Tp = 1
(11)
2 I0
Although the gates of M3, M4 are cross-connected to the
drains, in common-mode the pair of gates follows the voltage
waveform at the pair of drains, acting as if each FET is diode-
connected. The cross-coupling is evident only in differential
mode.
Differentially, the cross-connected NFET pair M3, M4 oper-
ates as a charge-transfer amplifier between CC and C L . Refer-
ence [10] shows that voltage on a capacitor can be amplified
by transferring its charge on to a smaller capacitor through
a unilateral device, such as a saturated FET connected in
common-gate. Reference [11] uses this as an explicit low-
power preamplifier whose voltage output drives a latch in
cascade. In the StrongArm circuit, in contrast, the preampli-
fication is implicit. What is different here is the unilateral
device responsible for charge transfer (FET M3 or M4) is
cross-connected in a balanced circuit. In the equivalent half
circuit (Fig. 6(c)) this appears as a voltage-controlled current
source connecting the two capacitors, which depends on the
sum of the voltages at its terminals measured with respect to
ground.1 When the loop comprising CC , C L and the controlled
source is stable —we will show below that it may not be—it
reaches steady-state when current ceases to flow through the
controlled source. Then VC D = −VO D , that is, capacitor CC
is not merely discharged but acquires charge in the opposite
polarity, thus placing a larger charge on C L than was present
1 Referring to Mason’s catalog [12] of non-reciprocal elements, in [10]
charge is transferred through a unistor, but during propagation in the
StrongArm latch through a gyristor.
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

originally on CC . When accounted for algebraically, charge 1) C L  2CC . For a dynamic amplifier with large gain,
is still conserved since the two capacitors are connected by a s p T p is large and negative, so the exponential in (17) is
two-terminal device; and also energy, after taking into account negligible.
that both capacitors were pre-charged to the supply voltage. 2) C L ∼ CC . This is rare. Here s p T p is very small,
To determine whether the charge transfer is over a stable so e+s p T p  1 + s p T p in (17), and (C L − CC ) cancels a
or a regenerative transient, we examine the sign of the real term in the numerator.
pole that characterizes the loop formed by CC , C L and the 3) C L  2CC . This might be true if a large number of cal-
controlled source. It is sufficient for a check on stability to ibration capacitors are attached at CC . This will reverse
assume that the controlled source is linear. Then this pole is the sign of s p T p in (18), so a growing exponential
C L − CC term will dominate the parentheses in (17). The sign
s p = −gm3,4 (12) of VO D (Ts + T p ) will not change.
C L CC The final voltage then simplifies to:
When C L > CC , the pole is a negative real quantity and ⎧
the charge transfer will decay to a well-defined final value. ⎪ Ts + T p
⎪
⎪ if CC  C L /2
But when the pole is positive, the charge transfer will grow ⎪
⎪ C −C
⎪
⎨ T L+ 1 TC
exponentially for the duration that the FET behaves as a linear
v O D (Ts + T p ) = i I D ×
s 2 p Tp
element: when it enters into a different regime such as triode · if CC ≈ C L
⎪
⎪ C L − CC τ p
region, regeneration will be clamped. We are interested in ⎪
⎪
⎪
⎪ τ p − Ts
the voltage on C L at the end of the time window T p , when ⎩ · e+s p T p if CC  2C L
propagation concludes and regeneration starts. Then, even a C L − CC
growing exponential waveform will deposit a well-defined (19)
voltage on C L . Voltage gain ( A V ) is found by using i I D = gm1,2 v I D to obtain
Thus there are two contributions to VO D . First there is v O D /v I D
the charge integrated on CC that redistributes to C L through ⎧
charge transfer that we have just described. As well, there is ⎪ C L + 2CC 2Vt
⎪
⎪ · if CC  C L /2
the fraction of i I D through M3, M4 that integrates on C L . ⎪
⎪ C − C V
⎪ L
⎨ C + 3C C D S AT 1,2
We will calculate these two components below using the L C Vt2
transfer function, AV = · if CC ≈ C L
⎪
⎪
⎪ 2V C+CV
⎪
V D S AT 1,2 V D S AT 3,4
 2V 
1 ⎪
⎪ t D S AT 3,4 t
 ⎩ · exp if CC  2C L
VO D (s) = I I D (s) s  (13) V D S AT 1,2 V D S AT 3,4
s(C L − CC ) 1 −
sp (20)
From (2), the charge on CC at the end of the sampling With typical values, we may conclude that in all reasonable
phase is cases the voltage gain VO (Ts + T p )/v id ≈ 5 ∼ 10. It covers
CC Vt N all cases of C L /CC ; and gives a meaningful expression when
Q C (Ts ) = CC VC D (Ts ) = 2 vI D (14) CC  C L , in contrast to [13, Eq. (5)] which implies that
V D S AT 1,2 preamplification gain would then be infinite. A useful way
In propagation phase this charge defines an impulse current of understanding it is that with this capacitive inequality,
i 1 (t) = Q C (Ts )δ(t − Ts ) that is applied to the zero-state the source degeneration on the cross-coupled pair M3,4 is
network whose transfer function is (13). After the inverse lowered enough that the pair develops sufficient loop gain to
transform, regenerate, but that the regenerating waveform is sampled at
Q C (Ts )   the end of a prescribed time window.
v O D1 (Ts + T p ) = 1 − e+s p T p (15) 4) Regeneration Phase: At the end of the propagation
C L − CC phase, the cross-coupled PMOS pair, M5, M6, turns ON and,
Meanwhile, a fraction of i id keeps integrates over the period since its sources are connected together, it always regenerates
T p and adds to VO the voltage the voltage (19) at the output nodes (Fig.6(d)). At start of
regeneration the PMOS pair is governed by a pole that lies in
i id · T p i id · τ p  
the right-half s-plane sreg = +gm5 /C L .
v O D2 (Ts + T p ) = − 1 − e+s p T p (16)
C L − CC C L − CC
C. FET Mismatch
The net output is the algebraic sum of the two Estimation of the net offset arising from FET mismatches
T + T − τ τ p − Ts  requires knowledge of the transfer functions from each mis-
· e+s p T p
s p p
v O D (Ts + T p ) = i id + match source to the comparator output. Shown in Fig.7 are the
C L − CC C L − CC
equivalent differential mode circuits during sampling and prop-
(17)
agation phases, including independent current sources mod-
To calculate the term in parentheses we must know the elling mismatch. These circuits apply while M1∼M4 operate
magnitude and sign of in saturation.
These circuits show that Vt and β mismatch in the input
2|Vt P | C L − CC pair M1, M2 appear at the comparator input as an effective
s p Tp = · (18)
V D S AT 3,4 CC differential offset voltage.
Consider three cases, where the factor of two in the inequalities I M1,2 β1,2 V D S AT 1,2
is to indicate an approximate boundary between the three v os | M1,2 = = Vt 1,2 + · (21)
gm1,2 β1,2 2
cases.
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XU AND ABIDI: ANALYSIS AND DESIGN OF REGENERATIVE COMPARATORS FOR LOW OFFSET AND NOISE 5

Fig. 7. Equivalent differential circuit model of StrongArm latch with

mismatch sources during (a) sampling phase and (b) propagation phase.

Because of internal preamplification, mismatch in the PMOS

cross-coupled pair M5,6 will contribute negligibly to the input-
referred offset.
Threshold mismatch between M3,4 is modelled by a con-
Fig. 8. Comparison between theoretical calculation and simulation of
stant current I M3,4 that appears in parallel to the controlled dynamic offset introduced by C L : (a) Vary C L ; (b) Vary CC ; (c) Vary
source during propagation phase (Fig.7(b)). This current does V DS AT 1,2 ; (d) Vary V D D .
not change the total charge on CC and C L , and does not
contribute significantly to the output voltage. As currents
through M3,4 are determined by M1,2, β mismatch between
M3,4 does not produce a differential current. Thus, while M1,
M2 operate in saturation, M3,4 contribute negligibly to the
input-referred offset.
In summary, we have proved that the internal gain amplifies
the imbalances in the input differential pair the largest, to
the point that they will dominate all other FET imbalances
in the circuit. This identifies the principal source of offset,
and design can focus on its mitigation. In a well-designed
StrongArm comparator, input-referred offset is largely deter-
mined by M1,2 provided FETs remain in saturation through
the propagation phase.

D. Capacitor Mismatch
CC and C L , both grounded capacitors, are also subject
to mismatch. Indeed following (8) we advocate their delib-
erate unbalance to compensate FET mismatches. Capacitor
mismatch is modelled by a differential current (Fig.7(b)).
Through the sampling and propagation phases, the common-
mode to differential-mode coupling current due to CC mis-
match integrates charge onto CC and C L . The total charge
induced by CC mismatch is CC (Vt N + |Vt P |). The input-
referred offset that results is the differential input voltage
(v os = Vin1 − Vin2 ) that will counter this mismatch by driving
the differential voltage across C L to zero. From (10) and (11)
gm1,2 v os × (Ts + T p ) = CC (Vt N + |Vt P |)
2CC V D S AT 1,2
⇒ v os  · (22)
C L + 2CC 2 conditions. The input-referred offset remains independent of
Mismatch in CC appears through both sampling and prop-
agation phase, whereas mismatch in C L matters only during
propagation phase. The input-referred offset voltage due to C L
mismatch must counter the charge injected by C L into CC
and C L (Fig. 7(b)). Thus
gm1,2 v os × (Ts + T p ) = C L |Vt P |
C L V D S AT 1,2
⇒ v os  · (23)
C L + 2CC 2
Comparing (22) with (23), we see that CC unbalance induces
twice the offset of C L imbalance because CC undergoes a
Fig. 9. Comparison between theoretical calculation and simulation of
dynamic offset introduced by CC : (a) Vary CC ; (b) Vary CC ; (c) Vary
V DS AT 1,2 ; (d) Vary V D D .
common-mode voltage excursion of Vt N + |Vt P |, which is
almost twice the excursion of the voltage on C L . Eqs. (22)
and (23) show that the offsets introduced by CC , C L are,
contrary to the expressions in [14], both independent of V D D .
This is important for design.
Fig. 8 and Fig. 9 compare the simulated dynamic offsets
against predictions from (22) and (23) in a StrongArm latch
designed in 28 nm FD-SOI CMOS (FET sizes in Fig. 20).
The predictions match simulated results well across different
V D D until it is as low as 850 mV, below which there is no
longer the voltage headroom required to maintain M1, M2 in
saturation.
E. Offset Compensation
With this background, we can explain satisfactorily how
the offset calibration strategy first proposed in [15] and now
widely used works in latched comparators. We have estab-
lished that mismatch in the threshold voltage and β of the pair
M1, M2 will dominate. Now if the capacitances CC and C L
are fine tuned in closed-loop under digital control to create an
almost equal offset as given by (22) and (23) but opposite
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
in sign, the algebraic sum of the static offset from FET
mismatch will cancel the dynamic mismatch from capacitor
mismatch (recall (8)). The comparator appears offset-free at
its input port.
If the internal nodes at the drains of M1, M2 are left floating,
they will be pulled up to V D D − Vt N when the output nodes
are reset. It may seem like a bad idea to reset the CC nodes
to V D D because it prolongs the delay before regeneration by
Ts (see (10)). But (22) reveals that as a result of this delay,
CC is twice as effective in compensating offset. Thus, at the
expense of a larger latency, offset is nulled with a lighter
compensation capacitance.
But doesn’t the greater latency delay counteract the benefit
of a lighter capacitor loading in typical use? To answer
this question, we examine the critical comparator in an A/D
converter. A comparator is said to be critical when it is
resolving an input so close to a threshold that it may not even
complete regeneration in the allotted clock interval; that is,
the converter would make a metastability error. But metastable
error rate is determined by the regeneration time constant,
not latency (see Sec. III-H later). In the StrongArm latch it
is the PMOS pair M5, M6 that initiates regeneration, and in
the initial part of the regeneration transient it is loaded by C L
only. When CC shoulders the burden of compensating latch
offset, the latch regeneration time constant remains essentially
the same whether or not its offsets are nulled. But for large
offsets, it may be advantageous to distribute calibration arrays
between CC and C L . If in its eventual use the comparator is
embedded in a tight feedback loop such as in a self-timed
successive approximation A/D converter, its latency may also
matter. Otherwise it does not.
F. Importance of Input Common-Mode Voltage
A poorly chosen input common mode voltage can degrade
offset and noise considerably. This was observed experimen-
tally in an early use of the StrongArm latch as an SRAM
sense amplifier [16] and subsequently recognized in [2], [17],
and [13].
The input common-mode voltage (VI C ) (Fig.5) sets the bias
current through M1-M4, but also determines whether or not
these FETs will operate in saturation over the sampling and
propagation phases. This is best understood in the hypothetical
instance of a perfectly balanced, offset-free latch with zero
differential input, which upon release from reset will decay
Fig. 10. Equivalent differential circuit model for noise calculation.
voltage on CC : indeed, we assume that they will do so rapidly,
and 2) the deeper in triode region that M1,2 operate, the lower
their transconductance during the propagation phase, raising
the comparator’s input-referred offset and noise.
Possible erasure of the amplified voltage afflicts all com-
parators with dynamic pre-amplification; we will show that
new comparator topologies announced in the literature offer a
partial remedy.
G. Thermal Noise
In ADC’s that operate at low supply voltages, thermal noise
in the comparator can dominate other sources of noise in the
signal path and usurp random offset as the most important
concern, because offset can be nulled but not noise.
Some published work [9], [18] models noise in the Stron-
gArm latch, but does not offer closed-form expressions or
addresses the importance of biasing M1,2 in saturation region.
We provide a noise analysis that is simple, accurate, yields
closed-form expressions that estimate noise, and guides prac-
tical design.
Analysis of thermal noise is on the same lines as of offsets
(Fig. 10). But first we must explain how noise randomly trig-
gers regeneration around the metastable point. In a perfectly
balanced StrongArm comparator with zero input applied,
the noise current in the input pair M1, M2 will integrate
on CC during the sampling phase, and continue to integrate
and amplify on C L . At the end of the propagation phase,
the voltage integrated on C L will trigger regeneration to ‘0’ or
‘1’ with equal likelihood. When reasonable preamplification
is present, then as described in Section III-B noise from
M3∼M6 will not contribute significantly.
Using the method in Section II-C, the mean square voltage
on CC at the start of propagation phase is
 
into its metastable equilibrium. It is sufficient to examine the Sin Ts 1 2 Sin Ts
v c  =
2
dt = · (25)
state of the circuit when the regenerative PMOS pair M5, M6 2 0 CC 2 CC2
starts to conduct, i.e. when VO1 (= VO2 ) falls from V D D
to V D D − |Vt P |. Since this excursion is purely in common where Sin = 8kTγ gm1,2 (A2 /Hz) is the density of differential
mode, M3, M4 will behave as if they are diode connected and noise current in M1,2 and γ is a process technology dependent
therefore they operate in their saturation region. But for the constant, usually between 2/3∼1. With the coefficient of 8
input pair M1, M2 to remain in saturation up to this time, in Sin , the circuit elements do not have to be divided by
VI C must not exceed an upper limit 2 as they were in Sec. II-C. At the end of propagation phase,
 the mean square voltage on C L due to charge sharing from
Vt
VI C −  N < V D D − VG S (M3, M4) −  |V
t P| (24) v c is
where Vt N = |Vt P |.
2
Sin Ts CC 
When the internal nodes are precharged to V D D , the input v o,1
2
= · 2 1 − e+s p T p (26)
pair will remain in saturation over the entire sampling phase 2 CC C L − CC
for any VI C , even when it is as large as V D D . This ensures
full dynamic amplification of the input voltage v id on to the During propagation phas, the noise current from M1, M2 also
capacitors CC over the sampling phase Ts . Problems may integrates on C L . Its contribution to mean square output
arise in the propagation phase, when M1,2 might be forced voltage is
into the triode region. There are two consequences to this:

 2
Sin T p 1
1) M1,2 behaving like resistors can discharge the amplified v o,2
2
= 1 − e+s p t dt (27)
2 0 C L − CC
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XU AND ABIDI: ANALYSIS AND DESIGN OF REGENERATIVE COMPARATORS FOR LOW OFFSET AND NOISE 7

regeneration and C L sets the regeneration time constant, there

is a tradeoff between noise and speed. As (29) reveals, it is
2× more effective to lower noise by raising CC than by
raising C L .
Equation (29) also offers a straightforward estimation for
noise. It enables the circuit designer to decide whether offset
might be calibrated with an auxiliary FET differential pair
[3, Sec. 3.2] and if those FETs would add an unacceptable
noise of their own; or if it should be calibrated with a capacitor
array. In ADCs with low-to-moderate resolution, the noise of
a StrongArm comparator without added capacitance may be
low enough compared to one LSB so that offsets should be
Fig. 11. A simplified equivalent circuit of the StrongArm latch to predict corrected with auxiliary differential pairs since they do not
noise, preamplification gain, and speed. penalize latency and speed: [17] employs this approach. But
in high resolution ADCs with an exacting noise specification,
The input-referred current noise (Fig.10) is calculated by capacitor arrays may be the only viable method to correct
dividing the total output noise power v o2  = v o1
2  + v 2  by
o2 offsets and to limit NBW.
the transconductance in (19):
⎧ H. Comparator Speed
⎪
⎪
1
if CC < C L /2
⎪
⎪ The net delay of a StrongArm latch consists of two parts:
⎪
⎪ Ts + Tp
Sin ⎨ Ts + T p /3 1) the latency of the sampling and propagation phases, which
i id
2
= × if CC ≈ C L (28) is determined by the common mode bias current, and 2) the
2 ⎪
⎪ (T s + T p /2)
2
delay of regeneration, which is mainly specified by the accept-
⎪
⎪ Ts − τ p /2
⎪
⎪ if CC > 2C L able metastability error rate. First we explain what the latter
⎩
(Ts − τ p )2 means. In any regenerative waveform, the final value at the
end of a certain time window is proportional to the initial
Thus, in the StrongArm latch when CC is smaller than C L /2, voltage. Since the input to a comparator is a random voltage
the equivalent noise bandwidth (NBW) [7, Sec. 7.10] is deter- uniformly distributed over some well-defined interval, there
mined entirely by the duration of sampling and propagation exists a (usually very small) sub-interval around zero where the
phase. As we noted earlier, when charge is transferred through input drive is too small for the comparator output to regenerate
M3, M4 via a stable transient the process resembles a single within the clock window to a logic threshold. The bit-error rate
integration spanning Ts + T p . On the other hand, when CC is given by the ratio of this sub-interval to the full interval
is substantially larger than C L , the equivalent NBW is deter- [22, Sec. 8.1.3]. A specification on the error-rate dictates the
mined roughly by the time window of the sampling phase minimum clock period as a multiple (n) of the regeneration
(defined by a common-mode discharge) and the regeneration time constant, plus latency.
time constant τ p = −1/s p in propagation phase (determined
by a cross-connected differential circuit). tdelay = (Ts + T p ) + nτreg (30)
By comparing the voltage gain and the NBW of a Stron-
gArm latch and a simple integrator, an equivalent circuit While both C L and CC in Fig. 5 will determine the latency
for noise may be formed as in Fig.11, consisting of a sim- for common-mode discharge, the regeneration time constant
ple integrator followed by a negative resistance that mod- depends essentially on C L : τreg ≈ C L /G m , where G m is
els comparator regeneration. This simplified circuit captures the net transconductance of the cross-coupled inverters. In
both voltage preamplification and equivalent NBW. Current the initial part of regeneration, only the cross-coupled pair
is integrated over the sampling phase, followed by charge M5, M6 drives C L , while M3, M4 in saturation shield loading
sharing and continued integration over the propagation phase. by CC . Later, when M1 and M2 are pushed into triode,
Reference [19] uses a similar model to study comparator M3, M4 will contribute to G m their own transconductance
circuits where, however, preamplifiers and regenerative latches degenerated by M1, M2. M1, M2 will short CC . Thus,
are explicitly in voltage cascade. G m is raised without additional capacitance, and regeneration
The input-referred noise voltage is of final interest. It is speeds up.
obtained as v id
2  = i 2 /g 2
ID m1,2 Expressions (22), (23), (29) and (30) together offer a
quantitative guide to the optimum design of a StrongArm latch
V D S AT 1,2 for offset, noise and error-rate.
v id
2
 = 4kTγ ·
Vt
⎧ I. Kickback
⎪ 1 1
⎪
⎪ · if CC  C L /2
⎪ 2 C L + 2CC
⎪ When the tail switch in Fig. 5 is actuated, the gates of M1,
⎨ 1 M2 absorb a pulse of current to support inversion layers. In the
× if CC ≈ C L (29) critical comparator with near-zero differential input, this is
⎪
⎪ C L + 3CC
⎪
⎪ 1 essentially a common-mode current pulse extracted from the
⎪
⎩ if CC  2C L
CC (2 + V D S AT 3,4 /Vt ) circuit driving the comparator input. But β mismatch [23] in
M1, M2 will convert it into a small differential current pulse.
Unlike dynamic offset that depends on fractional capacitor Since the driving circuit is never a perfect voltage source,
imbalance, the input-referred noise depends inversely on the the source impedance converts this into a differential voltage
total capacitance. Since CC increases the latency before final at the comparator’s input. When the source impedances driving
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 12. (a) The original double-tail latch from [20]; (b) The improved double-tail latch from [21].
the two comparator inputs are themselves unequal, the pulse of
common-mode input current converts into a larger differential
voltage. For example, in flash ADCs one input may be
connected to a resistor reference ladder, which is modelled by
a distributed RC circuit. The input current impulse, referred
to as ‘kickback’ [24], can induce transients on all tap voltages
[22, Ch. 8]. This produces a signal-dependent reference error.
When all comparators share the same reference ladder and
its RC settling is slow, kickback from one decision interferes
with the next decision.
Another kickback appears during regeneration, when the
latching of the cross-coupled inverters M3∼M6 perturbs the
sources driving the comparator input through capacitive cou-
pling via M1, M2. This effect is different in its origin from
the common-mode kickback and its effect can sometimes be
quite benign. In the StrongArm latch this kickback appears
when regeneration is almost completed and therefore cannot
interfere with that decision. Charge-redistribution SAR ADCs,
where one comparator makes every decision, are a special
case. [25, Appendix D-D] shows that any differential-mode
kickback causes no harm as long as the comparator is reset
before every decision.
IV. D OUBLE TAIL C OMPARATOR
The “double tail” comparator preserves the benefits of
internal dynamic amplification in the StrongArm circuit at
low supply voltages, or when the input common-mode bias is
unsuitable. Originally developed to buffer the driving circuit
from charge kickback during regeneration [20], its circuit
structure (Fig. 12(a)) also enforces zero static power dissi-
pation. A dynamic preamplifier precedes a latch in voltage
cascade, that is, in shunt.2 When CLK goes high, the differ-
ential input is amplified and appears superposed on the output
common-mode (bias) voltage that, in this circuit, ramps down
from an initial voltage of V D D to 0. This changing common-
mode voltage will eventually drive the preamplifier differential
pair MP1, MP2 into triode, which will then discharge the
amplified differential voltage stored on capacitors C pre . Then
the preamplifier will shut off its own bias current. The pro-
gressively amplified input is available over the time window
between when the clock turns on, and before the amplifier
shuts itself off and erases the amplified voltage.
The FETs M1a, M2a couple the dynamic preamplifier’s
output to a static latch. They are key to correct operation.
2 As opposed to the StrongArm latch, where the dynamic amplifier is in
series cascade.
Initially these FETs are biased into deep triode by the large
voltage V P1 , V P2 applied to their gates. Their β is much
larger than of M3, M4 to suppress any inclination of the
cross-connected pair M5, M6 to regenerate. As V P1 , V P2 ramp
down, MP1, MP2 amplify the differential input; at some point
on this ramp M1a, M2a release their hold on M3, M4, enabling
the latch M3∼M6 to regenerate. It is intended that the sign of
the amplified differential voltage coupled into the latch through
M1a, M2a, will determine the regenerated binary output. Only
the preamplifier is clocked in this circuit; everything else
follows by self-timing, concluding in regeneration of the latch
circuit.
Reference [26] points out with simulations that this arrange-
ment performs poorly. We will explain why. Consider the
dynamics of the coupling FETs M1a, M2a. They turn on in
deep triode with a large VG = V D D and V D ≈ 0. As VG
ramps down, their V D rises, until VG crosses below Vt 0 to
turn them off. This describes a time trajectory on the FET
I D -V D S plane which starts in deep triode when M1a, M2a’s gm
is low; then they enter saturation, when V D rises to 1/2V D D
but at that point VG → Vt 0 , so again their gm is low. Over
this trajectory the transconductance is weak for most of the
time, so M1a, M2a are ineffective in coupling the preamplified
voltage at their gates into the latch. Offset and noise in the
latch M3∼M6 may now have a pronounced effect.
A. Details of Operation
Reference [26] goes on to offer a better circuit (Fig. 12(b)).
We recognize this as a dynamic amplifier MP1, MP2 driving
a StrongArm latch in voltage cascade. Why does this not
suffer the same fate as the circuit of Fig. 12(a)? It has to
do with the direction of the ramping bias that the comple-
mentary (folded) amplifier applies to the StrongArm latch.
The preamplifier drives the input pair M1a, M2a of the
StrongArm latch with a positive-going ramp, on which is
superposed the continuously growing differential signal. This
ramp turns on the input pair of the StrongArm latch and softly
releases the reset switches M1b, M2b, M1c, M2c. M1a, M2a’s
transconductance rises with the ramp because the pair is in
saturation, while its differential input grows continuously. The
StrongArm goes through its self-timed phases of sampling,
propagation, and regeneration. Since everything operates as
expected, the dynamic amplification is strong and the com-
parator’s input-referred offset and noise will now be deter-
mined almost entirely by the preamplifier’s input pair MP1,
MP2.
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XU AND ABIDI: ANALYSIS AND DESIGN OF REGENERATIVE COMPARATORS FOR LOW OFFSET AND NOISE
Fig. 13. Offset degradation when M B is removed and C pre is reduced
in Fig.12(b).
The dynamic preamplifier will work correctly over a large
range of input bias while the FETs MP1, MP2 in its input
pair remain in saturation. However, once triggered, this ampli-
fier will some time later drive itself into the off condition.
Meanwhile in sampling phase, the StrongArm itself will
dynamically amplify the differential input further on CC
. But
if the gate of the pair M1a, M2a is ramped to too large a
voltage, or if the supply voltage is too low, then these FETs
can discharge the amplified voltage stored on CC
. We have
shown previously that if this happens, the StrongArm will
display a large offset and noise. The preamplification is of
little value if M1a and M2a, which act as coupling FETs in this
circuit, enter triode and effectively disconnect the preamplifier
from the StrongArm before the latching pair M5, M6 starts to
regenerate.
This reveals that there exists within this cascade of two
dynamic amplifiers [3, Sec. 5.2] a race condition that can
undermine offset and noise. The dynamic preamplifier offers
gain over a certain time window while its FET pair MP1,
MP2 is in saturation. But when this FET pair enters triode,
it effectively wipes out the amplified voltage stored on C pre .
That window is
VI C + |Vt 0|
Tw, pre = C pre 1
(31)
2 I pre
where, in Fig. 12(b), the voltages are measured with respect
to ground. The StrongArm has its own window, (Ts + T p )
determined by a bias current that changes with the ramping
voltage, and by the capacitances CC
and C L
that it will of the first; meanwhile the first continues to integrate (Fig. 15).
discharge.
The amplifier cascade will work well as long as Tw, pre >
(Ts + T p ). But if this inequality is reversed, the preamp will
have erased its amplified voltage before the StrongArm reaches
regeneration, resulting in a significant rise in input-referred
offset. In reality the erasure is, of course, gradual. This is seen
in simulations of the input-referred offset (Fig. 13), with the
offsets from MP1, MP2 only as the baseline for comparison.
The race condition, when not accounted for in design by
proper choice of C pre /I pre , is clearly damaging to the desired
operation.
Comparator offset can be no lower than the input-referred
offset of its input stage. The simplest method to calibrate this
offset is with a digitally controlled array of capacitors inserted,
as explained in Sec. II, at C pre in the dynamic preamp. When
realized correctly, this compensation will not be affected by
changes in the supply voltage.
B. Noise in Double Tail
The classic StrongArm and the double tail latch will likely
display a comparable offset before calibration, determined by
mismatch in the preamplifying input pair; but one might
9
Fig. 14. gm1,2 (t) as a time-dependent parameter in a double-tail comparator.
Fig. 15. Equivalent differential circuits of the double-tail comparator
Fig.12(b) during (a) reset phase; (b) first integration from dynamic preampli-
fier; (c) double integration from the dynamic amplifier and the second stage
StrongArm latch; (d) regeneration phase.
surmise that noise in the double tail should be lower because
of the cascaded integration: that is, if a windowed integrator
bandlimits white noise, then a cascade of two such integrators
should limit it even more. A close look shows that this is
not so: all else being the same, the noise in a double tail
comparator is slightly higher than it is in the StrongArm alone.
Suppose that the output of one windowed integrator drives,
in tandem, another windowed integrator. After the first inte-
grator has been active for a period T pre , the second integrator
is enabled with zero initial condition and driven by the output
The output of this second integrator is sampled after an inter-
val Ts . Then it can be shown (Appendix IX) that the net effect
is one of sampling a white noise current that is bandlimited
to 1/(T pre + 12 Ts )[Hz] . This means that over a certain time
window Tw = (T pre + Ts ), a single integration bandlimits
the input noise more effectively than do two integrations in
tandem, when the second integration takes place over the
sub-window Ts .
This calculation assumes time-invariant integrators, whose
time constants are fixed. For proper autonomous (self-timed)
operation in a double-tail (Fig. 12(b)), the sources of the
input FET pair of the StrongArm latch should be grounded.
This means that as the preamp’s output voltage ramps up,
the current through the StrongArm input stage rises quadrat-
ically with time and its transconductance linearly (Fig. 14).
Therefore, its integration bandwidth also grows linearly with
time. Since this time-varying circuit remains linear for small
signals such as noise and offset, it may be analyzed using
the time-dependent impulse response [27, p. 79]. A com-
plete analysis (Appendix IX) shows that the input-referred
mean square noise is set by the preamplifier’s constant
input spectral density (either voltage or current) limited to a
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10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

 
NBW of 1/ T pre + 23 (Ts + T p ) [Hz] . Thus the input-referred
mean-square noise voltage is
4kTγ 1
v id
2
= · (32)
gmp1,2 T pre + 23 (Ts + T p )

Prior to the onset of regeneration, the total latency of the

double tail is T pre + (Ts + T p ). If a simple StrongArm is
designed for the same latency, it will bandlimit the input
pair’s noise to 1/(Ts + T p )[Hz] , numerically equal to the
inverse of the latency above but without the factor of 2/3
in (32); its noise, therefore, will be slightly lower. This is Fig. 16. (a) Input referred RMS noise of a StrongArm latch and a double-
tail comparator under different power supply levels; (b) Power and delay of a
because in the StrongArm, the charge integrated over Ts StrongArm latch and a double-tail comparator under different power supply
is transferred from CC to C L , so the process resembles a levels. Clock frequency f C L K = 2 GHz and delay tdelay is simulated with
single, uninterrupted integration. On the other hand in a double 2 mV differential input.
tail cascade, the charge integrated by the preamplifier is not
transferred to the integrator in the cascaded stage. falls below 550 mV. At that point the input differential
A good comparator design might trade off the slightly pair of the StrongArm latch is pushed into triode during
higher noise in the double tail against its robustness at low propagation, resulting in erasure of dynamic amplification
supply voltages or large range of input common-mode levels. and rapid rise in input-referred noise. The predicted noise
But in view of the analysis so far, it is difficult to see what assuming M1,2 remain in saturation serves as a baseline
further advantage in noise and offset that a third integrator in for comparison. Although the double-tail’s input-referred
a triple tail cascade might offer. noise is somewhat higher, it does remain supply-independent.
At VI C = 400 mV, noise in the StrongArm latch worsens even
V. D ISCUSSION : S TRONG A RM VS . D OUBLE TAIL earlier, at V D D = 700 mV, while the double-tail comparator
maintains its noise.
For the optimum trade-off between noise, offset and speed
The double tail also offers a shorter regeneration time.
in the StrongArm latch, the input common mode must lie in
We have described above how in the StrongArm circuit regen-
a specified voltage interval. If too high, the input differential
eration is actuated by the transconductance of the common
pair enters triode region prematurely, erasing the dynamically
source pair M5, M6. As regeneration proceeds, the cross-
amplified input voltage during propagation phase; if too low,
connected pair M3, M4 gradually adds its own transcon-
it stretches out both latency and regeneration. In practical
ductance to speed up regeneration. This transconductance is
designs, the previous circuit determines the input common
degenerated by the series resistance of M1, M2 in triode.
mode voltage which may not lie in the range of preferred
Whereas in the classic StrongArm this resistance is determined
bias. Level shifting may be difficult. For example, in certain
by the fixed gate bias at M1, M2, in the double tail that gate
successive approximation ADCs the input common-mode level
voltage is ramping up which continuously lowers the degen-
changes at every conversion step [28]. There the double-tail
erating resistance. This raises the effective regeneration G m .
comparator is more suitable [29] because its dynamic amplifier
In practice, this shortens regeneration time by ∼20%. Because
can operate predictably well across a wider range of input
the double-tail comparator decouples latency and regeneration,
common mode. Ultimately this range will limited by the onset
each can be individually optimized. Noise is lowered by
of the race condition described above.
stretching out the integration window (latency) without affect-
The expected noise filtering can only be obtained with
ing regeneration, whereas in a StrongArm latch the stacked
careful design. The first stage MP1, MP2 should provide
FETs will couple regeneration time constant weakly to latency.
sufficient amplification so that noise currents from M1a-c,
The design trade-off is clear. Conceptually, the most effi-
M2a-c (Fig. 12(b)) do not contribute significantly. Switches
cient comparator architecture is a single-windowed integrator
M1b-c, M2b-c when softly actuated by a ramp will inject noise
followed by a regenerative unit. Departure from this structure,
of their own. Usually this is small. The bias to the second
such as more stages of integration in the dynamic amplifiers,
stage latch is time-varying: M1a-c, M2a-c must be correctly
tends to worsen noise slightly. Although the StrongArm latch
sized to avoid the race condition—this may be the most
is the most compact regenerative comparator, it requires a
important design step, which requires a proper constant current
well-controlled input common-mode voltage and a minimum
supplied by MB and a C pre [30]. On the other hand, in the
supply voltage. This runs counter to the trend in scaled CMOS.
classic StrongArm latch, FET sizing is much easier: a simple
At low supplies or when the input biasing is not suitable,
1:1:1 size ratio of input differential pair, cross-coupled NMOS
the double-tail comparator is better. Its folded complementary
and PMOS pair is usually good enough.
preamplifier offers a very useful built-in level shift.
Fig.16 compares the input-referred noise, power consump-
tion and delay of a StrongArm latch and a double-tail compara- VI. C ASE S TUDIES : C OMPARISON W ITH M EASURED DATA
tor. The two circuits are sized to give the same delay when All the expressions found from analysis relating to static
the differential input is 1 mV, and consume equal power at and dynamic offsets are shown to closely match the offset
nominal 0.9V supply with VI C = 300 mV in the StrongArm obtained from transient simulations of the StrongArm latch.
latch and VI C = 100 mV in the double-tail comparator. The We now compare this against measurements.
input differential pairs realize the same gm at 0.9V supply.
Solid lines represent input-referred RMS noises calculated A. Input-Referred Offsets of StrongArm Latch
using (29) and (32). As an outcome of its smaller NBW, Among the many publications on this comparator, it is
the StrongArm latch displays 15% lower input-referred noise surprisingly difficult to find complete data: as the excep-
than a double-tail comparator; that remains so until V D D tion, [16] gives histograms measured across 45 samples of
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XU AND ABIDI: ANALYSIS AND DESIGN OF REGENERATIVE COMPARATORS FOR LOW OFFSET AND NOISE 11

Fig. 17. Test circuit in [16]. All dimensions in μm, V D D =1.5 V.

TABLE I
M EASURED RMS O FFSET VS . C ALCULATED . FET M ISMATCH
PARAMETERS : A V t = 3.5mV·μm, Aβ = 2.5%·μm

a latch realized in 130-nm CMOS (Fig. 17). It shows, notably,

that measured offset grows by more than 2× when the input
common-mode exceeds the limit specified by (24).
In Table I the measured RMS offset at two values of input
common-mode voltage agrees well with predictions from
our analysis. Although Infineon fabricated the circuit being
measured, we use mismatch coefficients from a generic 130 nm
CMOS process.3
For VI C = 0.7 V D D which lies within the range specified
Fig. 18. (a) A StrongArm latch preceded by a differential preamp and
by (24), we assume that offset arises from mismatch in Vt loaded by a cross-coupled NAND latch, V D D = 1.05V , all dimensions in
and β of M1, M2 only. Since our prediction is very close to μm; (b) Measured input referred offset distribution; (c) Unbalanced capacitive
the total measured offset, it verifies the statement that due to load to StrongArm latch from cross-coupled NAND gates.
internal amplification, M3∼M6 do not contribute appreciably
to offset. When VI C rises to V D D the analysis is more stores ’0’ and ’1’ at its outputs that do not reset with the clock.
complicated; although it is left out of this paper for brevity, When VO1 ,VO2 are reset to V D D , one of the NMOS transistors
it shows the rising contribution of M3,4 (Table I). In spite of (MN1A) will be in strong inversion whereas the other (MN1B)
the lower internal amplification, mismatch in the regenerating will be in weak inversion as shown in Fig.18(c). The effective
pair M5, M6 still does not contribute to offset. It is clear that gate capacitance to ground of MN1A is therefore larger than
too large a VI C worsens comparator offset considerably. of MN1B. This presents an unbalanced capacitive load on the
StrongArm latch, which will introduce an offset (recall (8)).
B. StrongArm Latch With Preceding Static The offset’s polarity flips with the state of the NAND latch:
Preamplifier and Loading NAND Latch in other words there is hysteresis in the comparator offset.
With V D D = 1.05 V and driven by Vin,C M = 900 mV ,
Fig.18(a) shows a comparator fabricated in 90 nm CMOS as
the output of the preamplifier biases at 900 mV. This pushes
part of a commercially developed test chip. It consists of three
M1, M2 in the StrongArm latch into triode during propa-
distinct blocks in cascade: a static preamplifier biased with a
gation. It lowers the dynamic voltage amplification within
constant tail current source, a clocked StrongArm comparator,
the StrongArm latch from 10× to about 1.5×. Preceded by
and a latched output buffer comprising two cross-coupled
a voltage gain of 2× from the preamplifier, we calculate
NAND gates. The preamplifier is there to isolate the previous
an input-referred hysteresis of ±3.6 mV, arising from the
stage from comparator kickback. The cross-coupled NAND
unbalanced capacitive load presented by the NAND latch.
latch holds the comparator decision while the latter is being
Offset was measured experimentally by driving the comparator
reset. Ideally the comparator offset should be determined by
with a slow ramping input voltage always of the same slope.
mismatch between MP1, MP2.
This produced a negative mean offset across all comparators.
The measured offset in Fig.18(b) shows two unexpected
A CMOS inverter inserted as a buffer between the comparator
features. First, the mean of the measured offsets is non-zero.4
and NAND latch will eliminate the hysteresis.
Second, σ of the measured offset is larger than expected,
Table II breaks out calculated contributions of mismatch
implying contributions beyond those from MP1, MP2. Our
analysis can explain them both. sources. As well as Vt and β mismatch between MP1, MP2,
threshold mismatch between M3, M4 contributes significantly
Each output of the StrongArm latch is loaded by two NMOS
to the comparator input. Again, this is due to the high common
and two PMOS FETs in the NAND latch. The NAND latch
input voltage to the StrongArm latch. The calculated net input-
3 This is consistent with the findings that mismatches in a given CMOS referred offset matches well with measurement.
technology node are essentially the same at every foundry [31], [32]. Most valuably, the analysis suggests a simple remedy to
4 Based on sample size, this is statistically significant. lower offset without altering the circuit topology or raising its
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
TABLE II
M EASURED RMS O FFSET VS . C ALCULATED . FET M ISMATCH
PARAMETERS : A V t = 2.3mV·μm, Aβ = 1.5%·μm
Fig. 19. (a) Test circuit in [17]. All dimensions in μm, V D D =1 V;
(b) Calculated input-referred noise versus simulation results in [17].
power consumption. First, increasing W/L of MP1, MP2√by
2× lowers the dominant source of mismatch right away by 2.
Second, raising R P in the preamplifier from 3 k to 8 k
boosts the preamplifier gain, but also lowers the preamplifier’s
output bias from 900mV to 650mV, restoring the StrongArm’s
dynamic voltage gain to about 10× and suppressing the offset
contributed by M3, M4. The higher voltage gain also shields
the StrongArm latch from the hysteresis effect. Table II shows
the predicted improvement with this remedy. Simulations
verify quantitatively that the offsets are lowered to an extent
close to what analysis predicts.
C. Input-Referred Noise of StrongArm Latch
Reference [17] reports on simulated input-referred RMS
noise of a StrongArm latch versus the input common mode
voltage as gm /I of the input differential pair changes
Fig. 19(a). Using our (29), we can predict this noise accurately
as shown in Fig. 19(b). However, the predicted noise deviates
from the simulated value at an input common mode voltage
of more than 600 mV. This is because of the increasing noise
contribution from M3, M4 as M1, M2 are pushed deeper
into triode; the calculations are left out for brevity. This
underscores once again the importance in the StrongArm
circuit of choosing the correct common mode voltage in order
to avail internal dynamic amplification.
VII. D ESIGN G UIDE
Since offset can be suppressed with calibration capacitors
at relatively low overhead except for a small penalty in speed,
the focus of comparator design shifts to lowering noise. Noise
reduction is expensive as it usually requires greater dissipation
of power, yet it is critical in applications such as ADCs without
residue amplification or in decision feedback equalizers.
We have designed the comparators in a 2.5 GS/s 10 bit
time-interleaved charge redistribution SAR ADC, fabricated
in 28 nm FD-SOI process. With 1 LSB=1.5 mV, considerations
of comparator noise drove the trade-off in power and speed.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 20. (a) StrongARM comparator with calibration capacitors. All dimen-
sions in μm, V D D =1 V; (b) Offsets, noise, latency and regeneration constant
before/after calibration.
The 1 V supply is adequate for proper operation of a Stron-
gArm latch, which we chose (Fig. 20(a)) for its higher noise
filtering efficiency as discussed in Sec. IV-B. Its input common
mode voltage is set as 550 mV for the optimum trade-off
between noise and speed, as described in Sec. V. Sizing of
the FETs in the StrongArm latch is straightforward.
The loading on the comparator output is determined by the
logic gates realizing the successive approximation algorithm.
The size of the input differential pair is limited by the ability
of the previous stage to drive it. The remaining FETs in
the StrongArm latch are sized for fast regeneration with no
regard to offsets (Fig.20(a)), which will be suppressed with
calibration capacitors. The next step in design is to decide
how to allocate calibration capacitors between CC and C L to
cover process spreads.
Without calibration, σ of the comparator offset is 8 mV,
dominated by the input differential pair. Using (22) and (23)
for calculation, we decided to place most of the calibration
capacitance at CC for coarse offset calibration that covers
the expected spreads in FET mismatch Fig.20(b). In total,
6 bits of binary-weighted MOS capacitors are used for coarse
calibration, with an MSB capacitor of 16 fF. This leaves 5 bits
for fine calibration, entailing a total capacitance of 2.4 fF. This
array is placed at C L , adding to the fixed load of 10 fF. The
regeneration time constant τ and therefore metastable error
rate are not much affected, but the RMS offset after calibration
is tightened to ±0.4 mV (Fig. 20(b)).
The total calibration capacitance at CC and C L is deter-
mined by specifications on thermal noise from (28) and (29).
These expressions offer straightforward estimation of noise
without resort to time-consuming transient noise simulations
of regenerative comparators and iterative optimization. Includ-
ing the calibration capacitors, the input-referred noise is
lowered to 0.35 mV RMS.
The process of designing the optimum StrongArm com-
parator is now clear. Transistors are first sized to maximize
speed given the load constraints imposed by the preceding and
subsequent circuits. Calibration capacitors are then applied for
both offset calibration and noise filtering. The key idea in noise
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

XU AND ABIDI: ANALYSIS AND DESIGN OF REGENERATIVE COMPARATORS FOR LOW OFFSET AND NOISE 13

filtering is to stretch the latency, but preserve the regeneration

time constant.
The design of a double-tail comparator follows the same
steps. As discussed in Sec. V, besides being more accommo-
dating of input common mode voltage and lower power supply, Fig. 21. (a) Single integrator; (b) Two integrator cascade.
the double-tail comparator inherently decouples the latency
and regeneration time constant. However the circuit designer When CC > 2C L , exp(s p T p )  1 (because s p > 0) and the
must be aware of the race condition. total output noise power is found by
Sin Ts − τ p
VIII. D ISCUSSION v 2O  = · · e+2s p T p if CC  2C L (36)
2 (C L − CC )2
We have developed a simple, physically-based analysis for
the internal workings of a regenerative comparator. It leads A PPENDIX B
us to the key role of the dynamic preamplifier that is present NBW OF A C ASCADE OF T WO I NTEGRATORS
in most comparators. We present what we believe is the most The impulse response of a single-stage windowed integrator
comprehensive discussion so far of this dynamic amplifier, Fig.21(a) is
including how, when improperly biased, it can erase the
amplfied signal. We prove through simulation and measure- 1
h(t) =
[u(t) − u(t − T )] (37)
ment that when this amplifier operates correctly, its offset and C
noise determine that of the entire comparator. This also leads Its input referred noise and NBW are then calculated as
to clear insights into methods of offset calibration.  +∞
We compare the widely used StrongArm comparator with 2 Sin 0 h 2 (t)dt Sin 1
i I D  =  2 = ·
the evolved version of the double tail topology for their relative 2  +∞ 2 T
merits of noise, speed, and operation at low supply voltages. 0 h(t)dt
1
IX. C LASSIFICATION OF A MPLIFIER T YPES ⇒ NBW = (38)
T
While the stable linear amplifier is most familiar in circuits, In a two-stage cascading windowed integrator Fig.21(b),
in this paper we have examined at length two other types its impulse response is
of amplifiers: 1) The dynamic (integrator) amplifier, and
1 gm t
2) the regenerative amplifier, as in M3, M4 of the StrongArm h
(t) =
· [u(t) − u(t − T )] (39)
during propagation mode when CC > C L . If we assume that C1 C2
all amplifiers behave as linear circuits whose dynamics are Its input referred noise and NBW are then calculated as
described by a single pole, they may be classified by the  +∞
location of this pole in the s-plane, as follows: the pole of
2 Sin 0 h
2 (t)dt Sin 1
i I D  =  2 = · 3 
the stable amplifier lies in the left-half plane, of the dynamic 2  +∞
2 4T
0 h (t)dt
amplifier at the plane’s origin, and of the regenerative amplifier
in the right-half plane. The step response of the last two is 4 1
unbounded, so for the amplifier output to be useful it must be ⇒ NBW = · (40)
3 T
read off at the end of some well-defined time window. Indeed, cascading more integrators widens the NBW, which
is undesirable. We offer a simple explanation. First, these
A PPENDIX A are circuits with finite impulse response, where it is best to
O UTPUT NOISE POWER IN A S TRONG A RM LATCH derive their frequency response with the Fourier transform. In a
The complete expression of total output noise power at the single windowed integrator, the rectangle impulse response
end of propagation phase is the summation of (26) and (27), transforms into the well-known sinc() function in frequency
thus, v 2O  = v 2O1  + v 2O2  with nulls at the inverse of the integration time window and its
multiples. But the impulse response of the integrator cascade is
Sin  Ts + T p − τ p 2(Ts − τ p )
· e+s p T p
a single sawtooth triangle, whose more complicated transform
v 2O  = −
2 (C L − CC )2 (C L − CC )2 [33, Fig. 10–16] is lowpass but with no nulls. This is why it
Ts − τ p  transmits a larger mean-square noise.
+ · e +2s p T p (33)
(C L − CC )2 A PPENDIX C
With CC < C L /2 and exp(s p T p )  1 (because s p < 0), N OISE IN THE D OUBLE -TAIL C OMPARATOR
the total output noise power can be approximated as Because one of the circuit parameters, gm1 (t) varies with
Sin Ts + T p CL time, LTV analysis must applied to quantitatively describe the
v 2O  = · if CC  (34) noise within the double-tail comparator. Impulse response of
2 (C L − CC ) 2 2 an LTV system describes the system response at time t to
With CC ≈ C L , τ → ∞ and exp(s p T p ) → 1 (because s p ≈ an impulse arriving at time τ . With superposition, the output
0), using exp(x) ≈ 1 + x + x 2 /2, the total output noise power response is5
is approximated as
+∞
 2 y(t) = h(t, τ ) · x(τ )dτ (41)
Sin Ts + 13 T p Tp −∞
v 2O  = · if CC ≈ C L (35)
2 (C L − CC ) 2 τp 5 In an LTI system, h(t, τ ) = h(t − τ )
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

14 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

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1 β1 I 0 1
h(t, τ ) = VO (t) = ·t
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Hao Xu (S’14–M’18) received the B.S. degree in
mircoelectronics from Fudan University, Shanghai,
China, in 2010, and the M.S. and Ph.D. degrees in
electrical engineering from the University of Califor-
nia at Los Angeles, in 2012 and 2018, respectively.
He has been with Broadcom, Inc., Irvine, since
2017.
His research interests include mixed-signal, radio
frequency, and analog integrated circuit design.
Asad A. Abidi (S’75–M’80–SM’95–F’96) received
the B.Sc. degree (Hons.) from Imperial College,
London, U.K., in 1976, and the M.S. and Ph.D.
degrees in electrical engineering from the University
of California at Berkeley, Berkeley, in 1978 and
1981, respectively. From 1981 to 1984, he was
with Bell Laboratories, Murray Hill, NJ, USA, as a
Member of the Technical Staff with the Advanced
LSI Development Laboratory. Since 1985, he has
been with the Electrical Engineering Department,
University of California at Los Angeles, Los Ange-
les, where he is currently a Distinguished Chancellor’s Professor. He also
holds the Abdus Salam Chair at LUMS, Lahore, Pakistan. His research
interests span fundamentals of circuit design, RF CMOS circuits, high-speed
analog circuits, and data conversion.
He has been elected Fellow of IEEE, a member of the U.S. National Acad-
emy of Engineering, and a fellow of TWAS-the world academy of sciences.
He received an IEEE Millennium Medal, the 1988 TRW Award for Innovative
Teaching, the 1997 IEEE Donald G. Fink Award, the 2007 Lockheed-Martin
Award for Excellence in Teaching, and the 2008 IEEE Solid-State Circuit
Society’s Donald O. Pederson Award. He was named one of the top ten
contributors to the ISSCC in its first 50 and 60 years. From 1992 to 1995,
he was an Editor-in-Chief of the IEEE J OURNAL OF S OLID -S TATE C IRCUITS .