Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-1

LECTURE 03 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY

LECTURE ORGANIZATION
Outline
• Characteristics of a deep submicron CMOS technology
• Typical deep submicron CMOS technology
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
New material

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-2

CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGY

Isolation of Transistors
The use of reverse bias pn junctions to isolate transistors becomes impractical as the
transistor sizes decrease.

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-3

Use of Shallow Trench Isolation Technology

Shallow trench isolation (STI) allows closer spacing of transistors by eliminating the
depletion region at the surface.

Substrate Salicide Substrate Salicide

Well Salicide Decreased
spacing

ion h
Trench Isolation

lat nc
ow

Iso Tre
all

ow
Sh

a ll
Sh
n+ p+ p+ nn++ nnn+++

Shallow Shallow Shallow

Trench n-well Trench Trench
Isolation Isolation p-well Isolation

Substrate 070330-03

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-4

Comparison of STI and LOCOS

What are the differences between a LOCOS and STI technology?

Comments:
• If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniques
such as poly buffered LOCOS
• At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads to
undesirable stress effects in the transistor.
• An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+
isolation compared to LOCOS. This is a significant advantage for any process where
there are implants before STI.

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-5

Shallow Trench Isolation (STI)

Nitride
1.) Cover the wafer with pad oxide and silicon nitride. (1) Silicon

2.) First etch nitride and pad oxide. Next, an anisotropic

(2)
etch is made in the silicon to a depth of 0.4 to 0.5 microns.

(3)
3.) Grow a thin thermal oxide layer on the trench walls.

(4)
4.) A CVD dielectric film is used to fill the trench.

(5)
5.) A chemical mechanical polishing (CMP) step is used to
polish back the dielectric layer until the nitride is reached.
The nitride acts like a CMP stop layer. (6)

6.) Densify the dielectric material at 900°C and strip the 060203-01

nitride and pad oxide.

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-6

Illustration of a Deep Submicron (DSM) CMOS Technology

Metal Layers
0.8mm M8
NMOS PMOS
Transistor Transistor M7
M6
Polycide 0.3mm M5 7mm
Polycide Sidewall Spacers
M4
Salicide Salicide M3
Salicide M2
M1
n+ n+ p+ p+
STI Source/drain STI Source/drain STI
extensions extensions
Deep p-well Deep n-well p-substrate
031211-02

In addition to NMOS and PMOS transistors, the technology provides:

1.) A deep n-well that can be utilized to reduce substrate noise coupling.
2.) A MOS varactor that can serve in VCOs
3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-7

Transistors
fT as a function of gate-source overdrive, VGS-VT (0.13µm):
Typical, 25°C
70
60 NMOS
Slow, 70°C
50
fT (GHz)

40 Typical, 25°C

30 PMOS Slow, 70°C

20
10

0
0 100 200 300 400 500
|VGS-VT| (mV) 030901-07

The upper frequency limit of the transistors varies with overdrive and process corners.
The NMOS transistor has an fT of 40GHz at low overdrives and increases to above
60GHz at the slow-high temperature corner with 0.5V overdrive.

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-8

Resistors
1.) Diffused and/or implanted resistors.
2.) Well resistors.
3.) Polysilicon resistors.
4.) Metal resistors.

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-9

Capacitors
Polysilicon-polysilicon
capacitors:

Metal-metal capacitors:
Protective Insulator Layer

Metal Via
Top
Vias connecting top Metal
Capacitor plate to top metal
dielectric Capacitor Top Metal Second level
Inter-
Vias connecting bottom from top metal
mediate
Capacitor bottom plate plate to lower metal Third level
Oxide
Layers Vias connecting bottom from top metal
plate to lower metal Fourth level
from top metal

060530-01
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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-10

Inductors
Top view and cross-section of a planar inductor:
Top Metal
Top Metal
W

S Next Level
Metal
Vias Oxide
Next Level Oxide
Metal
D

Silicon Substrate

N turns
030828-01
D

Enhanced inductor removing the substrate†:

†
M. Raieszadeh, Integrated Inductors on Trenched Silicon Islands, MS Thesis, School of Electrical and Computer Engineering, Georgia Institute of Technology, April 2005

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-11

TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS

Major Fabrication Steps for a DSM CMOS Process
1.) p and n wells
2.) Shallow trench isolation
3.) Threshold shift and anti-punch through implants
4.) Thin oxide and gate polysilicon
5.) Lightly doped drains and sources
6.) Sidewall spacer
7.) Heavily doped drains and sources
8.) Siliciding (Salicide and Polycide)
9.) Bottom metal, tungsten plugs, and oxide
10.) Higher level metals, tungsten plugs/vias, and oxide
11.) Top level metal, vias and protective oxide

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-12

Starting Material
The substrate should be highly doped to act like a good conductor.

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 060118-02

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-13

Step 1 - n and p wells

These are the areas where the transistors will be fabricated - NMOS in the p-well and
PMOS in the n-well.
Done by implantation followed by a deep diffusion.

n well implant and diffusion p well implant and diffusion

p+ n+

n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 060118-03

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-14

Step 2 – Shallow Trench Isolation

The shallow trench isolation (STI) electrically isolates one region/transistor from
another.

p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 060118-04

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-15

Step 3 – Threshold Shift and Anti-Punch Through Implants

The natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An
p-implant is used to make the NMOS harder to invert and the PMOS easier resulting in
threshold voltages balanced around zero volts.
Also an implant can be applied to create a higher-doped region Source Drain
beneath the channels to prevent punch-through from the drain
Punch-through
depletion region extending to source depletion region.
120521-02

n+ anti-punch through implant p+ anti-punch through implant

p threshold implant p threshold implant

n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 060118-05

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-16

Step 4 – Thin Oxide and Polysilicon Gates

A thin oxide is deposited followed by polysilicon. These layers are removed where they
are not wanted.

p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 060118-06

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-17

Step 5 – Lightly Doped Drains and Sources

A lightly-doped implant is used to create a lightly-doped source and drain next to the
channel of the MOSFETs.

Shallow p- Shallow p- Shallow n- Shallow n-

Implant Implant Implant Implant

p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 070321-01

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-18

Step 6 – Sidewall Spacers

A layer of dielectric is deposited on the surface and removed in such a way as to leave
“sidewall spacers” next to the thin-oxide-polysilicon-polycide sandwich. These sidewall
spacers will prevent the part of the source and drain next to the channel from becoming
heavily doped.

Sidewall Sidewall
Spacers Spacers

p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 070321-02

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-19

Step 7 – Implantation of the Heavily Doped Sources and Drains

Note that not only does this step provide the completed sources and drains but allows for
ohmic contact into the wells and substrate.

n+ p+ p+ n+ n+ p+
implant implant implant implant implant implant

n+ p+ p+ n+ nn++ p+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 070321-03

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-20

Step 8 – Siliciding (Salicide and Polycide)

This step reduces the resistance of the bulk diffusions and polysilicon and forms an
ohmic contact with material on which it is deposited.
Salicide = Self-aligned silicide

Polycide Polycide

Salicide Salicide Salicide

Salicide
n+ p+ pp++ n+ nn++ p+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well

Substrate

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 070321-04

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Step 9 – Intermediate Oxide Layer

An oxide layer is used to cover the transistors and to planarize the surface.

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Step 10- First-Level Metal

Tungsten plugs are built through the lower intermediate oxide layer to provide contact
between the devices, wells and substrate to the first-level metal.

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Step 11 – Second-Level Metal

The previous step is repeated for the second-level metal.

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Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker top-
level metal and a protective layer to hermetically seal the circuit from the environment.
Note that metal is used for the upper level metal vias. The chip is electrically connected
by removing the protective layer over large bonding pads.

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Scanning Electron Microscope of a MOSFET Cross-section

Tungsten Plug

TEOS

SOG

Polycide
Sidewall
TEOS/BPSG Spacer

Poly
Gate

Fig. 2.8-20

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Scanning Electron Microscope Showing Metal Levels and Interconnect

Metal 3
Aluminum
Vias
Metal 2
Tungsten
Plugs
Metal 1

Transistors Fig.180-11

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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-27

SUMMARY
• DSM technology typically has a minimum channel length between 0.35µm and 0.1µm
• DSM technology addresses the problem of excessive depletion region widths in
junction isolation techniques by using shallow trench isolation
• DSM technology may have from 4 to 8 levels of metal
• Lightly doped drains and sources are a key aspect of DSM technology

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