Lecture22 150128

Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-1
LECTURE 22 – INTRODUCTION TO OP AMPS

LECTURE OUTLINE
Outline
• Op Amps
• Categorization of Op Amps
• Compensation of Op Amps
• Miller Compensation
• Other Forms of Compensation
• Op Amp Slew Rate
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 261-286
CMOS Analog Circuit Design © P.E. Allen - 2016

OP AMPS
What is an Op Amp?
The op amp (operational amplifier) is a high gain, dc coupled amplifier designed to
be used with negative feedback to precisely define a closed loop transfer function.
The basic requirements for an op amp:
• Sufficiently large gain (the accuracy of the signal processing determines this)
• Differential inputs
• Frequency characteristics that permit stable operation when negative feedback is
applied
Other requirements:
• High input impedance
• Low output impedance
• High speed/frequency

Why Op Amps?
The op amp is designed to be used with single-loop, negative feedback to accomplish
precision signal processing as illustrated below.
Single-Loop Negative Feedback Network Op Amp Implementation of a Single-Loop
Negative Feedback Network
Feedback Network
Vf(s) Vf(s)
F(s) F(s)
- Vout(s) Vout(s)
Vin(s) + -
S A(s) Vin(s)
+
Av(s)
Op Amp 060625-01
Vout(s)
The voltage gain, V (s) , can be shown to be equal to,
in
Vout(s) Av(s)
Vin(s) = 1+Av(s)F(s)
If the product of Av(s)F(s) is much greater than 1, then the voltage gain becomes,
Vout(s) 1
The precision of the voltage gain is defined by F(s).
Vin(s) ≈ F(s)

OP AMP CHARACTERIZATION
Linear and Static Characterization of the CMOS Op Amp
A model for a nonideal op amp that includes some of the linear, static nonidealities:
where
Rid = differential input resistance
Cid = differential input capacitance
Ricm = common mode input resistance
Ricm = common mode input capacitance
VOS = input-offset voltage
CMRR = common-mode rejection ratio (when v1=v2 an output results)
en2 = voltage-noise spectral density (mean-square volts/Hertz)
Linear and Dynamic Characteristics of the Op Amp

Differential and common-mode frequency response:
V1(s)+V2(s)
Vout(s) = Av(s)[V1(s) - V2(s)] ± Ac(s)  
 2 
Differential-frequency response:
Av0 Av0 p1p2p3···
Av(s) = s = (s -p )(s -p )(s -p )···
  s  s  1 2 3
p - 1p - 1p - 1···
 1  2  3 
where p1, p2, p3,··· are the poles of the differential-frequency response (ignoring zeros).

Other Characteristics of the Op Amp

Power supply rejection ratio (PSRR):
VDD Vo/Vin (Vdd = 0)
PSRR = Av(s) = V /V (V = 0)
VOUT o dd in
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary
without influence the differential performance
Slew rate (SR):
SR = output voltage rate limit of the op amp
Settling time (Ts):

OP AMP CATEGORIZATION
Classification of CMOS Op Amps
Conversion Hierarchy
Voltage Classic Differential Modified Differential

to Current Amplifier Amplifier
First
Voltage
Stage
Current Differential-to-single ended Source/Sink MOS Diode
to Voltage Load (Current Mirror) Current Loads Load
Current
Voltage Transconductance Transconductance Stage
to Current Grounded Gate Grounded Source
Second
Voltage
Current Class A (Source Class B Stage
to Voltage or Sink Load) (Push-Pull)
Table 110-01

Two-Stage CMOS Op Amp

Classical two-stage CMOS op amp broken into voltage-to-current and current-to-voltage
stages:

Folded Cascode CMOS Op Amp

Folded cascode CMOS op amp broken into stages.

COMPENSATION OF OP AMPS
Compensation
Objective
Objective of compensation is to achieve stable operation when negative feedback is
applied around the op amp.
Types of Compensation
1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage.
• Miller capacitor only
• Miller capacitor with an unity-gain buffer to block the forward path through the
compensation capacitor. Can eliminate the RHP zero.
• Miller with a nulling resistor. Similar to Miller but with an added series resistance
to gain control over the RHP zero.
2. Self compensating - Load capacitor compensates the op amp (later).
3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can
be less than unity.
Because compensation plays such a strong role in design, it is considered before design.

Single-Loop, Negative Feedback Systems

Block diagram:
A(s) = differential voltage gain of the op amp
F(s) = feedback transfer function
Definitions:
• Open-loop gain = L(s) = -A(s)F(s)
Vout(s) A(s)
• Closed-loop gain = V (s) = 1+A(s)F(s)
in
Stability Requirements for a Single-Loop, Negative Feedback System:
At the frequency where the phase-shift of the loop is 0°, the magnitude of the loop must
be less than 1. This is expressed as,
A(j0°)F(j0°) = L(j0°)  1
where 0° is defined as
Arg[-A(j0°)F(j0°)] = Arg[L(j0°)] = 0°
Alternately, at the frequency where the loop gain is unity, the phase shift must be greater
than 0°. This expressed as,
Arg[-A(j0dB)F(jw0dB)] = Arg[L(j0dB)]  0°
where 0dBis defined as
A(j0dB)F(j0dB) = L(j0dB) = 1
Illustration of the Stability Requirement using Bode Plots

|A(jw)F(jw)|
-20dB/decade
Note that the loop phase

0dB w
-40dB/decade shift starts at ±180°. We
180° have chosen +180° for
Arg[-A(jw)F(jw)]
this analysis. If we had

135° selected -180°, then the
90°
vertical axis would
be -180°, -225°, -270°,
45° -315°, and finally -360°.
FM
0° w0dB w
Frequency (rads/sec.) 150128-01
A measure of stability is given by the phase when |A(j)F(j)| = 1. This phase is called
phase margin.
Phase margin = M = Arg[-A(j0dB)F(j0dB)] = Arg[L(j0dB)]

Why Do We Want Good Stability?

Consider the step response of second-order system that closely models the closed-loop
gain of the op amp connected in unity gain.
A “good” step response is one that quickly reaches its final value.
Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.
(A rule of thumb for satisfactory stability is that there should be less than three rings.)
Note that good stability is not necessarily the quickest rise time.
Uncompensated Frequency Response of Two-Stage Op Amps

Two-Stage Op Amps: VDD VCC
M3 M4 Q3 Q4
M6 Q6
vout vout
- M1 M2 - Q1 Q2
vin vin
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-04
Small-Signal Model:
D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7)

+ + +
g v
gm1vin R1 C1 v1 m2 in v2 R3 C3 vout
gm4v1 R2 C2
- gm6v2
2
2 - -
Fig. 120-05
Note that this model neglects the base-collector and gate-drain capacitances for purposes
of simplification.

Uncompensated Frequency Response of Two-Stage Op Amps - Continued

For the MOS two-stage op amp:
1 1
R1  g ||rds3||rds1  g R2 = rds2|| rds4 and R3 = rds6|| rds7
m3 m3
C1 = Cgs3+Cgs4+Cbd1+Cbd3 C2 = Cgs6+Cbd2+Cbd4 and C3 = CL +Cbd6+Cbd7
For the BJT two-stage op amp:
1 1
R1 = g ||r3||r4||ro1||ro3g R2 = r6|| ro2|| ro4  r6 and R3 = ro6|| ro7
m3 m3
C1 = C3+C4+Ccs1+Ccs3 C2 = C6+Ccs2+Ccs4 and C3 = CL+Ccs6+Ccs7
Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives,
+ + + +
gm1vin v2 R3 C3 vout gm1Vin VI RII CII Vout
R2 C2 RI CI
- gm6v2 - - gmIIVI -
Fig. 120-06
The locations for the two poles are given by the following equations
-1 -1
p’1 = R C and p’2 = R C
I I II II
where RI (RII) is the resistance to ground seen from the output of the first (second) stage
and CI (CII) is the capacitance to ground seen from the output of the first (second) stage.

Uncompensated Frequency Response of an Op Amp (F(s) = 1)

Avd(0) dB
-20dB/decade
|A(jw)|
GB
0dB log10(w)
Phase Shift -40dB/decade
-45/decade
180°
Arg[-A(jw)]
135°
-45/decade
90°
45°
0° log10(w)
|p1'| |p2'| w0dB 150128-02
If we assume that F(s) = 1 (this is the worst case for stability considerations), then the
above plot is the same as the loop gain.
Note that the phase margin is much less than 45° (≈ 6°).
Therefore, the op amp must be compensated before using it in a closed-loop
configuration.
MILLER COMPENSATION
Miller Compensation of the Two-Stage Op Amp
VDD VCC
M3 M4
Q3 Q4
CM M6 CM Q6
Cc vout Cc vout
M1 M2 Q1 Q2
- -
vin CI CII vin CI CII
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-08
The various capacitors are:

Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage

Compensated Two-Stage, Small-Signal Frequency Response Model Simplified

Use the CMOS op amp to illustrate:
1.) Assume that gm3 >> gds3 + gds1
gm3
2.) Assume that C >> GB
M
Therefore,
Cc
v1 v2
+
-gm1vin vout
1 gm2vin
2
rds1||rds3 CM gm3 2 gm4v1 C1 rds2||rds4 gm6v2 rds6||rds7 CL -
Cc
v2
+ +
vin gm1vin CI CII vout
rds2||rds4 gm6v2 rds6||rds7
- -
Fig. 120-09
Same circuit holds for the BJT op amp with different component relationships.

General Two-Stage Frequency Response Analysis

Cc where
V2
+ + gmI = gm1 = gm2, RI = rds2||rds4, CI = C1
Vin gmIVin Vout and
CI RI gmIIV2 RII CII
- -
Fig.120-10
gmII = gm6, RII = rds6||rds7, CII = C2 = CL
Nodal Equations:
-gmIVin = [GI + s(CI + Cc)]V2 - [sCc]Vout and 0 = [gmII - sCc]V2 + [GII + sCII + sCc]Vout
Solving using Cramer’s rule gives,
Vout(s) gmI(gmII - sCc)
Vin(s) = GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII]
Ao[1 - s (Cc/gmII)]
= 1+s [R (C +C )+R (C +C )+g R R C ]+s2[R R (C C +C C +C C )]
I I II II 2 c mII 1 II c I II I II c I c II
where, Ao = gmIgmIIRIRII
 s s 1 1  s2 s s2
In general, D(s) = 1-p  1-p  = 1-s p + p +p p → D(s) ≈ 1-p + p p , if |p2|>>|p1|
 1  2  1 2 1 2 1 1 2
-1 -1 gmII
 p1 = R (C +C )+R (C +C )+g R R C ≈ g R R C , z= C
I I II II II c mII 1 II c mII 1 II c c
-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc] -gmIICc -gmII

p2 = ≈C C +C C +C C ≈ C , CII > Cc > CI
R R (C C +C C +C
I II I II c I c II
CMOS Analog Circuit Design
C ) I II c I c II II © P.E. Allen - 2016
Summary of Results for Miller Compensation of the Two-Stage Op Amp

There are three roots of importance:
1.) Right-half plane zero:
gmII gm6
z1= C = C
c c
This root is very undesirable- it boosts the magnitude while decreasing the phase.
2.) Dominant left-half plane pole (the Miller pole):
-1 -(gds2+gds4)(gds6+gds7)
p1 ≈ g R R C =
mII I II c gm6Cc
This root accomplishes the desired compensation.
3.) Left-half plane output pole:
-gmII -gm6
p2 ≈ C ≈ C
II L
p2 must be ≥ unity-gainbandwidth or satisfactory phase margin will not be achieved.
Root locus plot of the Miller compensation:

Compensated Open-Loop Frequency Response of the Two-Stage Op Amp
Avd(0) dB Uncompensated
|A(jw)F(jw)| -20dB/decade
F(jw)=1
Compensated
GB
0dB log10(w)
Phase Shift -40dB/decade
Uncompensated
180°
Arg[-A(jw)F(jw)|
-45°/decade
135°
F(jw)=1
90° -45°/decade
Compensated Phase
45°
No phase margin Margin
0° log10(w)
|p1| |p1'| |p2'| |p2|
150128-04
Note that the unity-gainbandwidth, GB, is

1 gmI gm1 gm2
GB = Avd(0)·|p1| = (gmIgmIIRIRII)g R R C = C = C = C
mII I II c c c c
Conceptually, where do these roots come from?

1.) The Miller pole:
1
|p1| ≈ R (g R C )
I m6 II c
2.) The left-half plane output pole:
gm6
|p2| ≈ C
II
3.) Right-half plane zero (One source of zeros is from multiple paths from the input to
output): VDD
 gm6  RII
-RIIsC - 1 Cc
-gm6RII(1/sCc)  RII   c  vout
   
vout = R + 1/sC v’ + R + 1/sC v’’ = R + 1/sC v
 II c   II c II c v''
M6
v'
where v = v’ = v’’. Fig. 120-15

Further Comments on p2
The previous observations on p2 can be proved as follows:
Find the resistance RCc seen by the compensation capacitor, Cc.
Cc VDD
vx
RCc RII
RCc
ix ix
M6 +
RI RI vgs6 RII
- gm6vgs6
060626-02
vx = ixRI + (ix + gm6vgs6)RII = ixRI + (ix + gm6ixRI)RII

Therefore,
vx
RCc = i = RI + (1 + gm6RI)RII ≈ gm6RIRII
x
The frequency at which Cc begins to become a short is,
1 1
< gm6RIRII  > gm6RIRII Cc ≈ |p1|
Cc or
Thus, at the frequency where CII begins to short the output, Cc is acting as a short.
Influence of the Mirror Pole

Up to this point, we have neglected the influence of the pole, p3, associated with the
current mirror of the input stage. A small-signal model for the input stage that includes
C3 is shown below:
i3 +
gm1Vin gm2Vin Vo1
2 1 i3
rds1 rds3 gm3 C3 2 rds2 rds4 -
Fig. 120-16
The transfer function from the input to the output voltage of the first stage, Vo1(s), can be
written as
Vo1(s) -gm1  gm3+gds1+gds3  -gm1 sC3 + 2gm3
Vin(s) = 2(gds2+gds4) gm3+ gds1+gds3+sC3 + 1  2(gds2+gds4)  sC3 + gm3 
   
VDD
We see that there is a pole and a zero given as
gm3 2gm3
p3 = - C and z3 = - C gmvin
3 3 C3 gmvin
2
Normally, the mirror pole will have negligible + 2
vin
influence on the stability of the op amp. -
VBias
140521-01
Summary of the Conditions for Stability of the Two-Stage Op Amp

• Unity-gainbandwith is given as:
 1  gmI
GB = Av(0)·|p1| =(gmIgmIIRIRII)·g R R C  = C =
 mII I II c c
 1  gm1
(gm1gm2R1R2)· =
gm2R1R2Cc Cc
• The requirement for 45° phase margin is:
  
±180° - Arg[Loop Gain] = ±180° - tan-1|p | - tan-1|p | - tan-1 z  = 45°
 1  2  
Let  = GB and assume that z  10GB, therefore we get,
GB
GB  GB
±180° - tan-1|p | - tan-1|p | - tan-1 z  = 45°
 1  2  
GB GB
135°  tan (Av(0)) + tan |p | + tan (0.1) = 90° + tan |p | + 5.7°
-1 -1 -1 -1
 2  2
GB GB
39.3°  tan-1   = 0.818  |p2|  1.22GB
|p2| |p2|
• The requirement for 60° phase margin: |p2|  2.2GB if z  10GB
• If 60° phase margin is required, then the following relationships apply:

gm6 10gm1 gm6 2.2gm1

 
Cc > Cc gm6 > 10gm1 and C > C Cc > 0.22C2
2 c

OTHER FORMS OF COMPENSATION

Feedforward Compensation
Use two parallel paths to achieve a LHP zero for lead compensation purposes.
RHP Zero Cc LHP Zero Cc LHP Zero using Follower
A -A Cc
Vi Vout Vi Vout Vi Vout

+1
Inverting Inverting
High Gain CII RII High Gain CII RII
Amplifier Amplifier
Cc
A
+ +
Vi gmIIVi CII RII Vout
s + gmII/ACc
- -
Vout(s) ACc   Fig.430-09
Vin(s) = Cc + CII s + 1/[RII(Cc + CII)]

 
To use the LHP zero for compensation, a compromise must be observed.

• Placing the zero below GB will lead to boosting of the loop gain that could deteriorate
the phase margin.
• Placing the zero above GB will have less influence on the leading phase caused by the
zero.
Note that a source follower is a good candidate for the use of feedforward compensation.
Self-Compensated Op Amps
Self compensation occurs when the load capacitor is the compensation capacitor (can
never be unstable for resistive feedback)
Voltage gain:
vout
vin = Av(0) = GmRout
Dominant pole: Stability:
-1 Large load capacitors simply reduce
p1 = R GB but the phase is still 90° at GB.
outCL
Unity-gainbandwidth:
Gm
GB = Av(0)·|p1| = C
L
FINDING ROOTS BY INSPECTION

Identification of Poles from a Schematic
1.) Most poles are equal to the reciprocal product of the resistance from a node to ground
and the capacitance connected to that node.
2.) Exceptions (generally due to feedback):
a.) Negative feedback:
C3
C2 C2
-A -A
R1 C1 R1 C1 C3(1+A)
RootID01
b.) Positive feedback (A<1):

C3
C2 C2
+A +A
R1 C1 R1 C1 C3(1-A)
RootID02

Identification of Zeros from a Schematic

1.) Zeros arise from poles in
the feedback path.
1
If F(s) = s ,
+1
p1
s 
A(s) +1
Vout A(s) A(s) p1 
then V = 1+A(s)F(s) = =s
in 1
1+A(s) s p1 +1+ A(s) VDD
p1 +1 Cc
RII
vout
2.) Zeros are also created by two paths from the input to the M6
output and one or more of the paths is frequency dependent. v''
v'
3.) Zeros also come from simple RC networks. 070425-01
C1
+ + Vout s + 1/(R1C1)
Vin R1 R2 Vout =
Vin s + 1/(R1||R2)C1
- -
070425-02
CMOS OP AMP SLEW RATE

Slew Rate of a Two-Stage CMOS Op Amp
Remember that slew rate occurs when currents flowing in a capacitor become limited
and is given as
dvC
Ilim = C dt where vC is the voltage across the capacitor C.
 I5 I6-I5-I7 I5  I5 I7-I5 I5
SR = minC , C  = C because I6>>I5
+ SR = minC , C  = C if I7>>I5.
-
 c L  c  c L  c
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew
rate of the two-stage op amp should be, I5/Cc.
SUMMARY
• Op amps achieve accuracy by using negative feedback
• Compensation is required to insure that the feedback loop is stable
• The degree of stability is measured by phase margin and is necessary to achieve small
settling times
• A compensated op amp will have one dominant pole and all other poles will be greater
than GB
• A two-stage op amp requires some form of Miller compensation
• A high output resistance op amp is compensated by the load capacitor
• Poles of a CMOS circuit are generally equal to the negative reciprocal of the product of
the resistance to ground from a node times the sum of the capacitances connected to
that node.
• The slew rate of the two-stage op amp is equal to the input differential stage current
sink/source divided by the Miller capacitor

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Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-1

LECTURE 22 – INTRODUCTION TO OP AMPS

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

Linear and Dynamic Characteristics of the Op Amp

CMOS Analog Circuit Design © P.E. Allen - 2016

Other Characteristics of the Op Amp

CMOS Analog Circuit Design © P.E. Allen - 2016

Voltage Classic Differential Modified Differential

CMOS Analog Circuit Design © P.E. Allen - 2016

Two-Stage CMOS Op Amp

CMOS Analog Circuit Design © P.E. Allen - 2016

Folded Cascode CMOS Op Amp

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

Single-Loop, Negative Feedback Systems

Illustration of the Stability Requirement using Bode Plots

Note that the loop phase

this analysis. If we had

CMOS Analog Circuit Design © P.E. Allen - 2016

Why Do We Want Good Stability?

Uncompensated Frequency Response of Two-Stage Op Amps

D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7)

CMOS Analog Circuit Design © P.E. Allen - 2016

Uncompensated Frequency Response of Two-Stage Op Amps - Continued

CMOS Analog Circuit Design © P.E. Allen - 2016

Uncompensated Frequency Response of an Op Amp (F(s) = 1)

The various capacitors are:

CMOS Analog Circuit Design © P.E. Allen - 2016

Compensated Two-Stage, Small-Signal Frequency Response Model Simplified

CMOS Analog Circuit Design © P.E. Allen - 2016

General Two-Stage Frequency Response Analysis

-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc] -gmIICc -gmII

Summary of Results for Miller Compensation of the Two-Stage Op Amp

CMOS Analog Circuit Design © P.E. Allen - 2016

Compensated Open-Loop Frequency Response of the Two-Stage Op Amp

Note that the unity-gainbandwidth, GB, is

Conceptually, where do these roots come from?

2.) The left-half plane output pole:

CMOS Analog Circuit Design © P.E. Allen - 2016

vx = ixRI + (ix + gm6vgs6)RII = ixRI + (ix + gm6ixRI)RII

Influence of the Mirror Pole

Summary of the Conditions for Stability of the Two-Stage Op Amp

CMOS Analog Circuit Design © P.E. Allen - 2016

gm6 10gm1 gm6 2.2gm1

CMOS Analog Circuit Design © P.E. Allen - 2016

OTHER FORMS OF COMPENSATION

Vi Vout Vi Vout Vi Vout

Vin(s) = Cc + CII s + 1/[RII(Cc + CII)]

To use the LHP zero for compensation, a compromise must be observed.

FINDING ROOTS BY INSPECTION

b.) Positive feedback (A<1):

CMOS Analog Circuit Design © P.E. Allen - 2016

Identification of Zeros from a Schematic

CMOS OP AMP SLEW RATE

CMOS Analog Circuit Design © P.E. Allen - 2016

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