(IJCNS) International Journal of Computer and Network Security, 21

Vol. 2, No. 8, August 2010

Adaptive Dual Threshold Multi-Class Scheduling

for Packet Switch
A. A. Abdul Rahman1, K. Seman2, K. Saadan3 and A. Azreen4
1
Telekom Research & Development, System Technology Unit,
TM Innovation Center, Lingkaran Teknokrat Timur,
63000 Cyberjaya, Selangor, Malaysia
abd_aziz@tmrnd.com.my
2, 3
Universiti Sains Islam Malaysia,Faculty of Science & Technology,
Bandar Baru Nilai, 71800 Nilai, Negeri Sembilan, Malaysia
2
drkzaman@usim.edu.my
3
kamarudin@usim.edu.my
4
Universiti Putra Malaysia, Multimedia Department, Faculty of Computer Science and Information Technology,
43400 Serdang, Selangor
azreen@fsktm.upm.edu.my
\

in heavy load. Scheduling algorithm for a single priority

Abstract: Multimedia applications such as video conferencing,
VoIP and data streaming require specified QoS to guarantee
their performance. Multi-class switch has been introduced to
handle different QoS requirement. In this research, a new way
of handling multi-class traffic is presented. The analysis is done
on N × N switch with two traffic classes; high priority for delay
sensitive cells (class 1) and low priority for loss sensitive cells
(class 0). In order to avoid starvation problem and to improve
total mean delay in loss sensitive class, a novel approach has
been introduced in the scheduling technique. The controller in
the scheduler will adjust the threshold value adaptively based on
the mean queue length and traffic load condition. By adjusting
these parameters adaptively the best possible mean delay and
throughput for class 0 can be achieved without degrading the
QoS requirement for class 1.The proposed method has been
simulated to show the performance of adaptive threshold as
compared to priority queue(PQ) and Weighted Fair
Queue(WFQ) in term of total mean delay and throughput. The
results show that the proposed architecture has achieved better
performance as compared to PQ and WFQ.
Keywords: multi-class switch, Quality of Service (QoS),
adaptive threshold, switching.
1. Introduction
In modern communication network, the desire of having
multiple traffic services in a single stream has created
problem especially in achieving the desired QoS
requirement for each services. The multi-class switch [1]-
[5], [8]-[11] is used to classify the multiple traffic streams
based on QoS requirements. The use of priority provides the
means to give different classes of service a different type of
traffic [4]. This requires new scheduling algorithms for
packet transmission.
Scheduling algorithm plays a key role in obtaining a
high performance in multi-class switch. Unfortunately, most
of the existing scheduling algorithm [1],[3]-[5] only strive to
maximize the QoS level in delay sensitive class for each
arrival cell without considering the adaptability, which may
result in poor QoS for lost sensitive class when the system is
class may not perform well when it is applied to a multi-
class scheduling [3]. Scheduling algorithm that is normally
used in two traffic classes only considers one parameter,
either only in priority packet setting or only on probability
of serving loss sensitive classes.
Priority buffer in multi-class switch will give more
priority to delay sensitive packets such as video, voice and
online game as compared to loss sensitive packet. In other
words, by using the priority buffer, real time applications
will be served first while non-real time applications will be
queued in the buffer waiting to be served. Many studies have
been done to reduce the waiting time for the loss sensitive
cells with less consideration on the degradation of
performance for the delay sensitive cells [1]-[4].
In [4], the performance of packet switch with two
priorities has been evaluated using heuristic adjustment.
Then it is improved by using the approximation technique of
the flow conservation rule [1]. Both techniques are using
priority buffer without any threshold control on the loss
sensitive class. This will lead to the starvation problem in
the loss sensitive class during high traffic load condition.
In [3], a reservation based scheduling approach has been
proposed to handle the QoS requirements for the delay
sensitive class and the loss sensitive class. This method uses
input-output queue that requires internal speedup which will
increase the complexity.
In Weighted Fair Queue (WFQ), traffic classes are
served based on the fixed weight assigned to the related
queue [10, 11]. The weight is determined according to the
QoS parameters, such as service rate or delay. This
technique is not suitable under high traffic load because of
the fixed weight that is assigned to the queue.
Designing a high speed packet switching with classes
will create a few problems such as starvation in the loss
sensitive class (class 0) and packet dropped due to long
waiting time in class 0. This research is expected to
minimize the waiting time in class 0 without affecting QoS
requirements for delay sensitive cells in class 1.
22
To achieve the stated objective, separate buffer for each
individual class is used to accommodate different traffic
classes. This will eliminate the head of line (HoL) of
different classes blocking effects. For different port, Virtual
Output Queue (VOQ) [6] [7] is used in order to eliminate
the HoL of different destination port blocking.
In this paper, we propose adaptive hybrid scheduling
method by combining two thresholds setting and able to
adjust the priority level of scheduling according to the mean
queue length of the delay sensitive class. In addition, the
scheduling technique is non-preemptive, which is more
efficient and less complex than preemptive approaches due
to reducing the overhead needed for switching among cells.
2. Proposed Model
The proposed multi-class switch and the scheduling
technique used in controlling the flows of the cells in the
switch is described below.
2.1 System model
The proposed multi-class switch architecture with N
ports serving C-1 classes of traffics is shown in Figure 1.
Priority switch is used to forward delay sensitive packet
(class C-1) faster than loss sensitive packet (class 0).
Figure 1. Multi-class switch architecture
The delay requirement for class j cells is defined by Dj
where j = 0, 1, 2… C-1 and D0 > D1 > D2 >……> DC-1. In
other words, the delay requirement for Class 1 is more
stringent than Class 0 for system shown in Figure 1. Thus,
cells that queue in Class 0 have the lowest priority and cells
that queue in Class C-1 have the highest priority. These
delay requirements are set based on the QoS requirement for
different type of applications.
Time slot is used to represent the time of one cell arrival
at the input port or cell departure at the output port. The
period of time slot Ts, where s = 0, 1, 2, … is set to be equal
to the time to process a single cell when the server is idle.
The class j cells arrive at the input port in every time slot
according to Bernoulli distributions with mean λj. The cell
is classified based on its delay requirement. In this
architecture the class of the cell is stored in the header. An
(IJCNS) International Journal of Computer and Network Security,
Vol. 2, No. 8, August 2010
arrival cells for Class j (λj) is queued in First-In-First-Out
(FIFO) buffer while waiting to be served.
Low priority
HoL
High priority
HoL Sch
Figure 2. Head of Line Scheduler.
At each time slot, the switch attempts to serve the cells at
Head of Line (HoL) of each input queue as shown in Figure
2. In the case when there are cells from different classes are
waiting at HoL, the HoL scheduler (HoL Sch) will select the
cell with high priority to be served. The losing cells in the
contention must wait in the queue. The numbers of queue
cells will increase when there are new incoming cells to the
queue.
The threshold setting is introduced in order to give some
privileges to cells in lower priority class. The threshold
parameter used in this architecture are the number of queue
cell, Nbj and the probability of serving low priority cell,
P TSCj; j = 0, 1, 2, …., C-1. Nbj parameter is chosen because
of the limited buffer size available in practical design. The
need to adjust the Nbj parameter is necessary to reduce the
packet loss due to buffer full. This parameter is adjusted
based on the size of buffer used to store cells in Class j. P TSCj
is the probability to serve the Class j when the Nbj parameter
threshold is met. The P TSCj parameter is chosen in order to
control the variation of delay between high priority and low
priority cells based on the high priority QoS requirements.
This is necessary in order to achieve better performance for
Class j cells. In the case where both threshold values are
met, the switch will select the cell from the class which the
threshold is triggered even in the present of higher priority
cells.
2.1 Simulation model
A simulation model is developed to simulate the
performance of the proposed switch under dual thresholds
setting. In this simulation, the architecture uses 16 x 16
switch with two classes for every input port. Class 0 is used
to classify the low priority buffer for non-real-time data. At
the same time, Class 1 represents high priority buffer for
real-time data.
The design of the switch architecture for input queue
multi-class switch is using separate buffer for each class.
Arrival cells are stored in different FIFO based on their
classes. The HoL scheduler will choose one cells from HoL
FIFO classes at every port to be forwarded to switch fabric.
The cells will contend with each other to gain access for
departure.
The proposed switch operates in time slotted transmission
to process each cells. Each time slot consists of three phases
which are arrival, scheduler and departure.
In the arrival phase, the incoming packet are segmented
into fixed size packet called cells and are aligned for
synchronization. The number of maximum cells, P max which
is generated in one time slot depends on the traffic load, λ
 (IJCNS) International Journal of Computer and Network Security, 23
Vol. 2, No. 8, August 2010

and the number of port, N, used. The relationship is shown

in (1). The traffic load is the total of λHi and λLi.
(1)
The cells are generated randomly and uniformly for all
destination port. For uniform traffic, the maximum arrival
rate at any queue is always less than 1/N of the traffic load.
Figure 3 shows the address packet generation in arrival
process.
FOR (port = 1 to N) DO
{ HoL Scheduler is used to select HoL cell from delay
IF (random number < traffic load) THEN
Destination address = random number * N;
ELSE
No destination address;
ENDIF
} if there are no cell in FIFOH or when both thresholds setting
Figure 3. Address Packet Generation in Arrival Process
Figure 4 shows the packet format for input buffer multi-
class switch. There are 20 bits in this cell. The first 8 bits is
the header which contains the destination address (7 bits)
and class (1 bit). The others 12 bits are for data.
After HoL is selected, it will compete with other cells
from the other input port. The scheduler is using round
robin policy with priority to select the cell in HoL for
departure.
In departure phase, delays for Class 1 and Class 0 cells
are calculated to measure the switch performance.
2.1.1 HoL scheduler with fixed thresholds value
sensitive class (FIFOH) and/or loss sensitive class (FIFOL).
Figure 6 shows the HoL scheduler design for two class
switch. Mux1 will transfer cell from FIFOH if dual threshold
setting (Nb0 and P TSC0) does not meet its limit and there are
cells in FIFOH. Cell from FIFOL will be transfered by Mux1
reach its limit. Mux2 will transfer cell from FIFOL when the
destination address for high class (Addr H) is different than
destination address for low class (Addr L). Mux2 will
eliminate the HoL blocking effect for loss sensitive class and
will increase the switch performance.

Figure 4. Cell format

In the class segment, bit ‘1’ indicates that the cell belongs
to the delay sensitive class and bit ‘0’ is for the loss sensitive
class. This bit is classified based on the type of packet
received and the QoS requirement for its applications. Each
generated cell is classified either to the delay sensitive class
or the loss sensitive class based on the traffic type. High
priority cell is tagged with 1 and low priority cell with 0. Figure 6. HoL scheduler design
Then, the cell is sent to FIFO waiting to be served. The Figure 7 illustrates the cell flow at the HoL scheduler under
Class 1 cell is sent to FIFO_H1 and Class 0 cell to three situations which are based on threshold condition and
FIFO_L1. The HoL for Class 1 and Class 0 must wait until destination address of class 1 and class 0.
it is served. In general, the HoL scheduler will choose the
cell in Class 1 since it has the high priority cells. In the case
when both threshold values are achieved, the HoL scheduler √ Different
will choose the Class 0 cells even in a presence of Class 1 √ destination
cells. address
The pseudo code for the input buffer with HoL output Class1 Same
scheduling is shown in Figure 5. When HoL for class 1 is √ destination
not empty and the threshold value setting is applicable for
HoL
× address, Nb &
PTSC0 = 0
both parameters, the HoL output will choose HoL packet Class0 WAIT
from class 0 instead of class 1. scheduler

WAIT Same
If (HoL class1 not empty) × destination
If (Nb0 > TN) && (PTSC0 >TP) √ address, Nb &
HoL_out = HoL class0; PTSC0 = 1
else
HoL_out = HoL class1;
else Figure 7. Example of success and failure of cell flow at
HoL_ out = HoL class0; HoL Scheduler

Figure 5. Pseudo code for HoL scheduler

24 (IJCNS) International Journal of Computer and Network Security,
Vol. 2, No. 8, August 2010

2.2.2 HoL scheduler with adaptive thresholds

value.
In order to improve the mean delay of the delay sensitive
class traffic in high traffic load condition, a HoL scheduler
with adaptive thresholds value is introduced. The idea is to
give absolute priority to the delay sensitive class in high
traffic load condition so that the high priority cell can be
transfer efficiently and meet its QoS requirements.
Meanwhile, when the traffic load is low or moderate, some
level of priority is given to the loss sensitive class. Figure 8
shows the architecture of HoL scheduler with adaptive
threshold.

Class 0
λ0 HoL Sch 1

16 X 16
Nonblocking
Switch
λ1 Class 1 Fabric

Figure 9. Example of the optimal threshold setting under

uniform traffic.
Thresholds
value
Controller
Under a uniform traffic condition, the measurement of
traffic load classification is defined as in Table 1 for VoIP
and video conferencing.
Figure 8. Architecture of HoL scheduler with adaptive
threshold.
Table 1: Traffic load classification for VoIP and video
conferencing.
The controller is used to set the threshold value based on the
traffic load condition. The controller uses the class 1 HoL
waiting time to determine the traffic condition. Under a Traffic load Waiting time
uniform traffic condition the best possible setting of the (time slot)
threshold value P TSC0 is based on the average of minimum
different waiting time (DW) in HoL between class 1 (WB1) LOW < 20
and class 0 (WB0), and QoSclass1 and WB1. The WB0 and WB1
values are normalized based on the QoS value for class 1. MODERATE 20 - 50
The relationship is shown in (2) and (3). Meanwhile Nb0
value is based on the average of occupied buffer in class 0 HIGH > 50
(FIFO0, i ) with number of ports in the switch (N) at the
border of classified traffic load (low, moderate or high). The Figure 10 shows the pseudo code for controller threshold
relationship is shown in (4). setting. The different level of serving probability is given
based on the percentage of QoS requirement of class 1.
(2)
If (waiting time <20% of QoS)
(3) Equal probability of serving class 1 and class 0
by not setting any thresholds or priority for both
classes.
(4) Else if (20% of QoS < waiting time <50% of QoS)
Increase probability of serving class1 to 75% by
increasing the threshold level setting of serving
Equation (2), (3) and (4) are graphically shown in Figure 9,
class0.
where the graphs of waiting time under uniform traffic
Else if (waiting time > 50% of QoS)
without any threshold setting for class 1 and class 0, noted Increase probability of class1 to 100% by giving
WB1 and WB0 respectively are used to obtain the optimum absolute priority to class1.
threshold setting.

Figure 10. Pseudo code for controller threshold setting.

 (IJCNS) International Journal of Computer and Network Security, 25
Vol. 2, No. 8, August 2010

Hardware design is developed to evaluate the performance equal distribution of λ1 and λ0.
of the proposed architecture. Figure 11 shows the hardware Total Mean
Delay
timing simulation of incoming and outgoing cells in multi- (time slot)
class switch. It can be seen that there are new incoming cell (i) Class 0 (PQ)
(ii) Class 0 (adaptive threshold)
at every time slots. After the cells have been processed, only (iii) Class 0 (WFQ) (i)
10
3 (iv) Class 1 (WFQ) (iii)
the successful cell is allowed to depart. The rest of the cells (v) Class 1 (adaptive threshold) (iv)
(vi) Class 1 (PQ) (ii)
must waiting for their turns. The output cell timing is used
to calculate the total means delay for Class 1 and Class 0. 10
2

(v)
1
10

(vi)
0 0.9 1
10
0.2 0.3 0.4 0.5 0.6 0.7 0.8
Ratio (r)

Figure 14. Ratio versus Mean delay in multi-class switch

with λ1 fixed to 0.5

These graphs show the performance of multi-class switch in

term of throughput and total mean delay. Figure 12 shows
Figure 11. Timing simulation of multi-class switch the throughput of cell in the switch under three
environments for both classes.
3. Performance Results a) Priority buffer.
b) WFQ.
In order to compare switching capabilities, the following c) Adaptive threshold.
performance metrics are considered:
• Throughput: a normalized value of the cell As shown in Figure 12, throughput with adaptive threshold
delivered correctly to its destination. for class 0 increases at load 0.8 and then decreases as the
load increases to 1. The class 1 throughput with adaptive
• Total Mean delay: the average end-to-end delay of threshold remains near to the class 1 throughput in PQ. But
cells, including the waiting time and serving time. the class 1 in WFQ tends to drop as the load increase to 1.
Figure 13 shows the total mean delay with equal distribution
• Cell arrival ratio: the ratio of cell class 0 over class of λ1 and λ0. The mean delay for adaptive threshold for class
1. This will measure the efficiency of the switching 1 is better as compared to mean delay in WFQ at high traffic
technique as the input of class 0 increase. load. Figure 14 shows the mean delay of ratio distribution of
λ1 and λ0. The mean delay for class 1 adaptive threshold is
Throughput lower as compared to class 1 in WFQ as the load increases.
0.50 (i)
(ii)
(ii) This effect is because of the adaptive controller threshold
(iii)
0.45
setting, which decrease the class 0 serving properties as the
load increases.
(i) Class 1 (PQ)
0.40 (ii) Class 1 (WFQ)
(iii) Class 1 (adaptive threshold)

0.35
(iv)
(v)
Class 0 (adaptive threshold)
Class 0 (WFQ) (iv)
4. Conclusions
(vi) Class 0 (PQ)
(v) In this paper, the multi-class switch with adaptive dual
0.30 (vi)
threshold is proposed to optimize the performance of class 0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Load
traffic without affecting the QoS requirement for class 1.
The simulation results show that the mean delay and
Figure 12. Throughput in multi-class switch with equal
throughput using adaptive threshold is better than WFQ. In
distribution of λ1 and λ0. adaptive threshold, the P TSC0 and Nb parameter are adjusted
Total Mean
Delay automatically based on condition of the traffic load. By
(time slot)
adjusting these parameters adaptively the optimum of mean
(i) Class 0 (PQ)
(ii) Class 0 (adaptive threshold) (i) delay and throughput for class 0 can be achieved without
(iii) Class 0 (WFQ) (ii)
10 2 (iv) Class 1 (WFQ)
(iii)
degrading the QoS requirement for class 1.
(v) Class 1 (adaptive threshold) (iv)
(vi) Class 1 (PQ)

10
1 References
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Figure 13. Total mean delay in multi-class switch with
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Authors Profile
A. A. Abdul Rahman received
Bachelor of Engineering (Electrical –
Electronics) and Master of Engineering
(Electrical) from Universiti Teknologi
Malaysia, Johor in 2002 and 2004. He is
currently pursuing the PhD degree at
Universiti Sains Islam Malaysia (USIM).
He is also an Associate Senior Researcher
in Telekom Research and Development. His
research interests are in hardware system
design, high speed switching, networking and software
engineering.
(IJCNS) International Journal of Computer and Network Security,
Vol. 2, No. 8, August 2010
K. Seman obtained B.Elec.Eng (2nd Class
Upper) from Universiti Teknologi Malaysia
(UTM) in 1985, MSc in Telematics from
Essex University, UK 1986, and PhD in
Electrical Engineering (Communication
Networks) from Strathclyde University UK
in 1994. He served as an academician at the
Faculty of Electrical Engineering, UTM
from 1985 till 2002. He was promoted as a
full professor in Telecommunication Engineering in 2000. From
2003 till 2005, he worked at Telekom Malaysia R&D working in
numerous network research projects. In Dec 2005 he joined
Universiti Sains Islam Malaysia as Professor in Network
Technology and Security. His research interests are network
performance modeling and analysis, cryptography, and switching
technology.
K. Saadan is a Senior Fellow (Computer
Science) in Information Security and
Assurance Programme in the Faculty of
Science, Universiti Sains Islam Malaysia.
Currently he is the Director of Centre for
Information Technology in USIM. He holds
a Bachelor of Science degree in
Mathematics, Master of Science in
Computer Science and PhD in Systems
Science Management. His areas of research
interest are in Intelligent Decision Support Systems, Software
Quality Assurance and Knowledge Management. His expertise is
in Software Engineering and Software Quality Assurance. So far
he has published more than 35 papers and technical reports in the
area of Computer Science and Information Technology. In the last
fifteen years he has been actively involved in various systems
development activities and research; and ICT project planning and
management.
A. Azman received his B.IT from Universiti
Multimedia in 1999, PhD in Information
Retrieval form University of Glasgow in
2007.From 1999 till 2002; he worked as
System Engineer at ON Semiconductor (M)
Sdn. Bhd. From 2008 till 2009, he worked as
lecturer in Universiti Sains Islam Malaysia
(USIM). In May 2009, he joins Universiti
Putra Malaysia as Senior Lecturer. His
research interests are in information retrieval, relevance feedback
his learning, data mining and knowledge discovery.