A Single-Phase Cascaded Multilevel Inverter

Based on a New Basic Unit

With Reduced Number of Power Switches

 CHAPTER 1

INTRODUCTION

1.1 POWER ELECTRONICS:

Power electronics is the application of solid-state electronics to the control and

conversion of electric power. It also refers to a subject of research in electronic and electrical
engineering which deals with the design, control, computation and integration of nonlinear, time-
varying energy-processing electronic systems with fast dynamics.

The first high power electronic devices were mercury-arc valves. In modern systems the
conversion is performed with semiconductor switching devices such as diodes, thyristors and
transistors, pioneered by R. D. Middle brook and others beginning in the 1950s. In contrast to
electronic systems concerned with transmission and processing of signals and data, in power
electronics substantial amounts of electrical energy are processed. An AC/DC converter
(rectifier) is the most typical power electronics device found in many consumer electronic
devices, e.g. television sets, personal computers, battery chargers, etc. The power range is
typically from tens of watts to several hundred watts. In industry a common application is the
variable speed drive (VSD) that is used to control an induction motor. The power range of VSDs
start from a few hundred watts and end at tens of megawatts.

The power conversion systems can be classified according to the type of the input and
output power

AC to DC (rectifier)

DC to AC (inverter)

DC to DC (DC-to-DC converter)

AC to AC (AC-to-AC converter)

1.2 DC/AC converters (Inverters):

 DC to AC converters produce an AC output waveform from a DC source. Applications
include adjustable speed drives (ASD), uninterruptable power supplies (UPS), active filters,
Flexible AC transmission systems (FACTS), voltage compensators, and photovoltaic generators.
Topologies for these converters can be separated into two distinct categories: voltage source
inverters and current source inverters. Voltage source inverters (VSIs) are named so because the
independently controlled output is a voltage waveform. Similarly, current source inverters (CSIs)
are distinct in that the controlled AC output is a current waveform.

Being static power converters, the DC to AC power conversion is the result of power
switching devices, which are commonly fully controllable semiconductor power switches. The
output waveforms are therefore made up of discrete values, producing fast transitions rather than
smooth ones. The ability to produce near sinusoidal waveforms around the fundamental
frequency is dictated by the modulation technique controlling when, and for how long, the power
valves are on and off. Common modulation techniques include the carrier-based technique, or
Pulse-width modulation, space-vector technique, and the selective-harmonic technique.

Voltage source inverters have practical uses in both single-phase and three-phase
applications. Single-phase VSIs utilize half-bridge and full-bridge configurations, and are widely
used for power supplies, single-phase UPSs, and elaborate high-power topologies when used in
multicell configurations. Three-phase VSIs are used in applications that require sinusoidal
voltage waveforms, such as ASDs, UPSs, and some types of FACTS devices such as the
STATCOM. They are also used in applications where arbitrary voltages are required as in the
case of active filters and voltage compensators.

Current source inverters are used to produce an AC output current from a DC current
supply. This type of inverter is practical for three-phase applications in which high-quality
voltage waveforms are required.

A relatively new class of inverters, called multilevel inverters, has gained widespread
interest. Normal operation of CSIs and VSIs can be classified as two-level inverters, due to the
fact that power switches connect to either the positive or to the negative DC bus. If more than
two voltage levels were available to the inverter output terminals, the AC output could better
approximate a sine wave. It is for this reason that multilevel inverters, although more complex
and costly, offer higher performance.

Each inverter type differs in the DC links used, and in whether or not they require
freewheeling diodes. Either can be made to operate in square-wave or pulse-width modulation
(PWM) mode, depending on its intended usage. Square-wave mode offers simplicity, while
PWM can be implemented several different ways and produces higher quality waveforms.

Voltage Source Inverters (VSI) feed the output inverter section from an approximately
constant-voltage source. The desired quality of the current output waveform determines which
modulation technique needs to be selected for a given application. The output of a VSI is
composed of discrete values. In order to obtain a smooth current waveform, the loads need to be
inductive at the select harmonic frequencies. Without some sort of inductive filtering between
the source and load, a capacitive load will cause the load to receive a choppy current waveform,
with large and frequent current spikes.

There are three main types of VSIs:

 Single-phase half-bridge inverter

 Single-phase full-bridge inverter
 Three-phase voltage source inverter

1.2.1 Single-phase half-bridge inverter:

The single-phase voltage source half-bridge inverters, are meant for lower voltage
applications and are commonly used in power supplies. Figure 1.2 shows the circuit schematic of
this inverter.

Fig 1.1: The AC input for an ASD.

 Fig 1.2: Single-Phase Half-Bridge Voltage Source Inverter

Low-order current harmonics get injected back to the source voltage by the operation of the
inverter. This means that two large capacitors are needed for filtering purposes in this design. As
Figure 1.2 illustrates, only one switch can be on at time in each leg of the inverter. If both
switches in a leg were on at the same time, the DC source will be shorted out.

Inverters can use several modulation techniques to control their switching schemes. The
carrier-based PWM technique compares the AC output waveform, vc, to a carrier voltage signal,
vΔ. When vc is greater than vΔ, S+ is on, and when vc is less than vΔ, S- is on. When the AC
output is at frequency fc with its amplitude at vc, and the triangular carrier signal is at frequency
fΔ with its amplitude at vΔ, the PWM becomes a special sinusoidal case of the carrier based
PWM. This case is dubbed sinusoidal pulse-width modulation (SPWM).For this, the modulation
index, or amplitude-modulation ratio, is defined as ma = vc/v∆ .

The normalized carrier frequency, or frequency-modulation ratio, is calculated using the

equation mf = f∆/fc .

If the over-modulation region, ma, exceeds one, a higher fundamental AC output voltage will
be observed, but at the cost of saturation. For SPWM, the harmonics of the output waveform are
at well-defined frequencies and amplitudes. This simplifies the design of the filtering
components needed for the low-order current harmonic injection from the operation of the
inverter. The maximum output amplitude in this mode of operation is half of the source voltage.
If the maximum output amplitude, ma, exceeds 3.24, the output waveform of the inverter
becomes a square wave.

As was true for PWM, both switches in a leg for square wave modulation cannot be turned
on at the same time, as this would cause a short across the voltage source. The switching scheme
requires that both S+ and S- be on for a half cycle of the AC output period.[8] The fundamental
AC output amplitude is equal to vo1 = vaN = 2vi/π .

Its harmonics have an amplitude of voh = vo1/h.

Therefore, the AC output voltage is not controlled by the inverter, but rather by the magnitude of
the DC input voltage of the inverter.

Using selective harmonic elimination (SHE) as a modulation technique allows the

switching of the inverter to selectively eliminate intrinsic harmonics. The fundamental
component of the AC output voltage can also be adjusted within a desirable range. Since the AC
output voltage obtained from this modulation technique has odd half and odd quarter wave
symmetry, even harmonics do not exist. Any undesirable odd (N-1) intrinsic harmonics from the
output waveform can be eliminated.

1.2.2 Single-phase full-bridge inverter:

Fig 1.3: Single-Phase Voltage Source Full-Bridge Inverter

 Fig 1.4: Carrier and Modulating Signals for the Bipolar Pulse width Modulation
Technique

The full-bridge inverter is similar to the half bridge-inverter, but it has an additional leg
to connect the neutral point to the load. Figure 1.3 shows the circuit schematic of the single-
phase voltage source full-bridge inverter.

To avoid shorting out the voltage source, S1+ and S1- cannot be on at the same time, and
S2+ and S2- also cannot be on at the same time. Any modulating technique used for the full-
bridge configuration should have either the top or the bottom switch of each leg on at any given
time. Due to the extra leg, the maximum amplitude of the output waveform is Vi, and is twice as
large as the maximum achievable output amplitude for the half-bridge configuration.

States 1 and 2 from Table 2 are used to generate the AC output voltage with bipolar
SPWM. The AC output voltage can take on only two values, either Vi or –Vi. To generate these
same states using a half-bridge configuration, a carrier based technique can be used. S+ being on
for the half-bridge corresponds to S1+ and S2- being on for the full-bridge. Similarly, S- being
on for the half-bridge corresponds to S1- and S2+ being on for the full bridge. The output voltage
for this modulation technique is more or less sinusoidal, with a fundamental component that has
an amplitude in the linear region of ma less than or equal to one vo1 =vab1= vi • ma.

Unlike the bipolar PWM technique, the unipolar approach uses states 1, 2, 3 and 4 from
Table 2 to generate its AC output voltage. Therefore, the AC output voltage can take on the
values Vi, 0 or –Vi. To generate these states, two sinusoidal modulating signals, Vc and –Vc, are
needed, as seen in Figure 1.4.
 Vc is used to generate VaN, while –Vc is used to generate VbN. The following
relationship is called unipolar carrier-based SPWMvo1 =2 • vaN1= vi • ma.

The phase voltages VaN and VbN are identical, but 180 degrees out of phase with each
other. The output voltage is equal to the difference of the two phase voltages, and do not contain
any even harmonics. Therefore, if mf is taken, even the AC output voltage harmonics will appear
at normalized odd frequencies, fh. These frequencies are centered on double the value of the
normalized carrier frequency. This particular feature allows for smaller filtering components
when trying to obtain a higher quality output waveform.

As was the case for the half-bridge SHE, the AC output voltage contains no even
harmonics due to its odd half and odd quarter wave symmetry.

1.2.3 Three-phase voltage source inverter

Fig 1.5: Three-Phase Voltage Source Inverter Circuit Schematic

 Fig 1.6: Three-Phase Square-Wave Operation a) Switch State S1 b) Switch State S3 c) S1
Output d) S3 Output

Single-phase VSIs are used primarily for low power range applications, while three-phase
VSIs cover both medium and high power range applications. Figure 5 shows the circuit
schematic for a three-phase VSI.

Switches in any of the three legs of the inverter cannot be switched off simultaneously
due to this resulting in the voltages being dependent on the respective line current's polarity.
States 7 and 8 produce zero AC line voltages, which result in AC line currents freewheeling
through either the upper or the lower components. However, the line voltages for states 1
through 6 produce an AC line voltage consisting of the discrete values of Vi, 0 or –Vi.

For three-phase SPWM, three modulating signals that are 120 degrees out of phase with
one another are used in order to produce out of phase load voltages. In order to preserve the
PWM features with a single carrier signal, the normalized carrier frequency, mf, needs to be a
multiple of three. This keeps the magnitude of the phase voltages identical, but out of phase with
each other by 120 degrees. The maximum achievable phase voltage amplitude in the linear
region, ma less than or equal to one, is vphase = vi / 2. The maximum achievable line voltage
amplitude is Vab1 = vab • √3 / 2

The only way to control the load voltage is by changing the input DC voltage.

1.3 Current source inverters

 Current source inverters convert DC current into an AC current waveform. In
applications requiring sinusoidal AC waveforms, magnitude, frequency, and phase should all be
controlled. CSIs have high changes in current overtime, so capacitors are commonly employed
on the AC side, while inductors are commonly employed on the DC side. Due to the absence of
freewheeling diodes, the power circuit is reduced in size and weight, and tends to be more
reliable than VSIs. Although single-phase topologies are possible, three-phase CSIs are more
practical.

In its most generalized form, a three-phase CSI employs the same conduction sequence as
a six-pulse rectifier. At any time, only one common-cathode switch and one common-anode
switch are on.

Fig 1.7: Three-Phase Current Source Inverter

Figure 1.8: Synchronized-Pulse-Width-Modulation Waveforms for a Three-Phase Current

Source Inverter a) Carrier and Modulating Signals b) S1 State c) S3 State d) Output Current
 Figure 1.9: Space-Vector Representation in Current Source Inverters

1.4 Multilevel inverters

Fig 1.10: Three-Level Neutral-Clamped Inverter

A relatively new class called multilevel inverters has gained widespread interest. Normal
operation of CSIs and VSIs can be classified as two-level inverters because the power switches
connect to either the positive or the negative DC bus. If more than two voltage levels were
available to the inverter output terminals, the AC output could better approximate a sine wave.
For this reason multilevel inverters, although more complex and costly, offer higher
performance. A three-level neutral-clamped inverter is shown in Figure 1.10.
 Control methods for a three-level inverter only allow two switches of the four switches in
each leg to simultaneously change conduction states. This allows smooth commutation and
avoids shoot through by only selecting valid states. It may also be noted that since the DC bus
voltage is shared by at least two power valves, their voltage ratings can be less than a two-level
counterpart.

Carrier-based and space-vector modulation techniques are used for multilevel topologies.
The methods for these techniques follow those of classic inverters, but with added complexity.
Space-vector modulation offers a greater number of fixed voltage vectors to be used in
approximating the modulation signal, and therefore allows more effective space vector PWM
strategies to be accomplished at the cost of more elaborate algorithms. Due to added complexity
and number of semiconductor devices, multilevel inverters are currently more suitable for high-
power high-voltage applications. This technology reduces the harmonics hence improves overall
efficiency of the scheme.

1.5 Multilevel Inverters:

In last few years there is growing interest in multilevel topologies, because of many
possibilities of expanding areas of power electronics use. It can also extend the application of
power converters to higher voltage and power ratio. Introducing multilevel converters to power
conditioning, drives, power generation and power distribution small and medium voltage (2 to
15kV) applications is very promising idea.

Multilevel converters synthesize output voltage from more than two voltage levels. Thus,
the output signals spectrum is significantly improved in comparison to classical two level
converters. The main drawback of multiphase multilevel converters is number of switches which
are growing when number of levels is increasing. Other drawback of those converters is
requirement of multiple DC voltage sources, mainly provided by capacitors. Balancing voltage
sources during operation under different load conditions is an important challenge. In spite of
these drawbacks, introducing multilevel converters will decrease switching losses (smaller
voltage on the power device) in comparison with two level appliance, allowing to increase
switching frequency and as consequence decrease requirements for reactive components. This, in
turn, results in converter weight, dimension and cost reduction.
1.6 DC-AC Inverters
Recent advances in the power-handling capabilities of static switch devices such as
IGBTs with voltage rating up to 4.5 kV commercially available, has made the use of the voltage
source inverters (VSI) feasible for high-power applications. High power and high-voltage
conversion systems have become very important issues for the power electronic industry
handling the large ac drive and electrical power applications at both the transmission and
distribution levels. For these reasons, a new family of multilevel inverters has emerged as the
solution for working with higher voltage levels. Multilevel inverters include an array of power
semiconductors and capacitor voltage sources, the output of which generate voltages with
stepped waveforms. Capacitors, batteries, and renewable energy voltage sources can be used as
the multiple dc voltage sources. The commutation of the power switches aggregate these
multiple dc sources in order to achieve high voltage at the output; however, the rated voltage of
the power semiconductor switches depends only upon the rating of the dc voltage sources to
which they are connected.
Switch-mode dc-to-ac inverters used in ac power supplies and ac motor drives where the
objective is to produce a sinusoidal ac output whose magnitude and frequency can both be
controlled. Practically, we use an inverter in both single-phase and three phase ac systems. A
half-bridge is the simplest topology, which is used to produce a two level square-wave output
waveform. A center-tapped voltage source supply is needed in such a topology. It may be
possible to use a simple supply with two well-matched capacitors in series to provide the center
tap. Today, multilevel inverters are extensively used in high-power applications with medium
voltage levels. The field applications include use in laminators, mills, conveyors, pumps, fans,
blowers, compressors, and so on.
 Fig 1.11 Classification of inverters
1.7 Two Level Inverter
“H” topology has many redundant combinations of switches’ positions to produce the
same voltage levels. As an example, the level “zero” can be generated with switches in position
S(1) and S(2), or S(3) and S(4), or S(5) and S(6), and so on.
Another characteristic of “H” converters is that they only produce an odd number of
levels, which ensures the existence of the “0V” level at the load .For example, a 51-level inverter
using an “H” configuration with transistor-clamped topology requires 52 transistors, but only 25
power supplies instead of the 50 required when using a single leg. Therefore, the problem related
to increasing the number of levels and reducing the size and complexity has been partially
solved, since power supplies have been reduced to 50%.
The single-phase H – Bridge of cascaded inverter. The ac terminal voltages of each
bridge are connected in series. Unlike the diode clamp or flying capacitors inverter, the cascaded
inverter does not require any voltage-clamping diodes or voltage balancing capacitors.
This configuration is useful for constant frequency applications such as active front-end
rectifiers, active power filters, and reactive power compensation. In this case, the power supply
could also be voltage regulated dc capacitor. The circuit diagram consists of two cascade bridges.
The load is connected in such a way that the sum of output of these bridges will appear across it.
The ratio of the power supplies between the auxiliary bridge and the main bridge is 1:3. One
important characteristic of multilevel converters using voltage escalation is that electric power
distribution and switching frequency present advantages for the implementation of these
topologies.
The full-bridge topology is used to synthesize a three-level square-wave output
waveform. The half-bridge and full-bridge configurations of the single-phase voltage source
inverter are shown in Fig. 1.12 and 1.13, respectively.
In a single-phase half-bridge inverter, only two switches are needed. To avoid shoot-
through fault, both switches are never turned on at the same time. S1 is turned on and S2 is turned
off to give a load voltage, VAO in Fig. 2.2, of +V s/2. To complete one cycle, S1 is turned off and
S2 is turned on to give a load voltage, VAO, of -V s/2.

S1

Vs/2

Vs 0 Load
A

Vs/2 S2

Fig 1.12: Half Bridge Inverter

Is

S1 S2

IL

Vs B Load
A

S3 S4

Fig 1.13: Full Bridge Inverter

. In full bridge configuration, turning on S1 and S4 and turning off S2 and S3 give a
voltage of VS between point A and B (VAB) in Fig. 1.13, while turning off S1 and S4 and turning
on S2 and S3 give a voltage of -Vs .
Table 1.1: Switching pattern of 3 level full bridge inverter

Conducing Switches Load Voltage VAB

S1,S4 +Vs
S1,S4 -Vs

S1,S4 orS1,S4 0

Table 1.1 Shows the voltage levels and their corresponding switching state condition
to generate zero level in a full-bridge inverter, the combination can be S1 and S2 on while S3 and
S4 off or vice versa. Note that S1 and S3 should not be closed at the same time, nor should S2 and
S4. Otherwise, a short circuit would exist across the dc source.
The output waveform of half bridge and full-bridge of single-phase voltage source
inverter are shown in Fig. 1.14 and 1.15respectively.
VAO

Vs
2
t

Vs
2

Fig 1.14 shows the output wave form of half bridge to get positive half cycle
S1 is turned on and S2 is turned off to give a load voltage, VAO of +V s/2.To complete one cycle,
S1 is turned off and S2 is turned on to give a load voltage, VAO, of -V s/2.
 VAB

Vs

Vs

Fig 1.15 Output waveform of Full Bridge Inverter to get positive half cycle S1 will be in on state
and S4 will be in off state to give a load voltage, VAO or vice versa

1.8 Multilevel Inverter

A voltage level of three is considered to be the smallest number in multilevel converter

topologies. Due to the bi-directional switches, the multilevel VSC can work in both rectifier and
inverter modes. This is why most of the time it is referred to as a converter instead of an inverter
in this dissertation. A multilevel converter can switch either its input or output nodes (or both)
between multiple (more than two) levels of voltage or current. As the number of levels reaches
infinity, the output THD approaches zero. The number of the achievable voltage levels, however,
is limited by voltage-imbalance problems, voltage clamping requirements, circuit layout and
packaging constraints complexity of the controller, and, of course, capital and maintenance costs.
Three different major multilevel converter structures have been applied in industrial
applications: cascaded H-bridges converter with separate dc sources, diode clamped, and flying
capacitors. The multilevel inverter structures are the main focus of discussion in this chapter;
however, the illustrated structures can be implemented for rectifying operation as well. Although
each type of multilevel converters share the advantages of multilevel voltage source inverters,
they may be suitable for specific application due to their structures and drawbacks. Operation
and structure of some important type of multilevel converters are discussed in the following
sections.
In a multilevel VSI, the dc-link voltage Vdc is obtained from any equipment which can
yield stable dc source. Series connected capacitors constitute energy tank for the inverter
providing some nodes to which multilevel inverter can be connected. Primarily, the series
connected capacitors will be assumed to be any voltage sources of the same value. Each
capacitor voltage Vc is given by

𝑣𝑐 = 𝑣𝑑𝑐/(𝑛−1)

Where n denotes the number of level. Fig 1.16 shows a schematic diagram of one phase
leg of inverters with different number of levels, for which the action of the power
semiconductors is represented by an ideal switch with several positions. A two-level inverter
generates an output voltage with two values (levels) with respect to the negative terminal of the
capacitor, while the three-level inverter generates three voltages, and so on.

Fig. 1.16 One phase leg of an inverter with (a) two levels, (b) three levels, and (c) n levels.

The term multilevel starts with the three-level inverter introduced by Nabae. By
increasing the number of levels in the inverter, the output voltages have more steps generating a
staircase waveform, which has a reduced harmonic distortion. However, a high number of levels
increases the control complexity and introduces voltage imbalance problems.
An inverter is a device that converts dc input power to ac output power at desired output
of voltage and frequency.

A multilevel converter has several advantages over a conventional two-level converter

that uses high switching frequency pulse width modulation (PWM). The attractive features of a
multilevel converter can be briefly summarized as follows.
● Staircase waveform quality: Multilevel converters not only can generate the output voltages
with very low distortion, but also can reduce the dv/dt stresses; therefore electromagnetic
compatibility (EMC) problems can be reduced.
● Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage; therefore,
the stress in the bearings of a motor connected to a multilevel motor drive can be reduced.
Furthermore, CM voltage can be eliminated by using advanced modulation strategies such as that
proposed in.
● Input current: Multilevel converters can draw input current with low distortion.
● Switching frequency: Multilevel converters can operate at both fundamental switching
frequency and high switching frequency PWM. It should be noted that lower switching
frequency usually means lower switching loss and higher efficiency.
Unfortunately, multilevel converters do have some disadvantages. One particular disadvantage is
the greater number of power semiconductor switches needed Moreover, three different major
multilevel converter structures have been reported in the literature: cascaded H-bridges converter
with separate dc sources, diode clamped (neutral-clamped), and flying capacitors (capacitor
clamped). Moreover, abundant modulation techniques and control paradigms have been
developed for multilevel converters such as sinusoidal pulse width modulation (SPWM),
selective harmonic elimination (SHE-PWM), space vector modulation (SVM), and others. In
addition, many multilevel converter applications focus on industrial medium-voltage motor
drives, utility interface for renewable energy systems, flexible AC transmission system (FACTS)
, and traction drive systems.
As previously mentioned, three different major multilevel converter structures have been
applied in industrial applications: cascaded H-bridges converter with separate dc sources, diode
clamped, and flying capacitors. Before continuing discussion in this topic, it should be noted that
the term multilevel converter is utilized to refer to a power electronic circuit that could operate in
an inverter or rectifier mode. The multilevel inverter structures are the focus of in this chapter;
however, the illustrated structures can be implemented for rectifying operation as well.
Advantages of multilevel inverters

 In High power circuits if you switch at high frequency switching losses are high.
 Particularly in Low power & low voltage circuits Mosfets are used.
 In Mosfets the conductions losses 70% of total losses and switching losses are 30 % of total
losses.
 So switching the Mosfets at high switching frequency not effects the total losses much.
 In case of High power high voltage circuits IGBT’s are used.
 In IGBT’s the conduction losses 50 % of total loss and switching losses are 50 % of total
loss. So if you switch at high frequency the efficiency of the system reduces.
 SO in High power High frequency PWM is not suitable, so we need to use multilevel
inverter for high power application.
The most attractive features of multilevel inverters are as follows.
 They can generate output voltages with extremely low distortion and lower dv/dt.
 They draw input current with very low distortion.
 They generate smaller common-mode (CM) voltage, thus reducing the stress in the motor
bearings. In addition, using sophisticated modulation methods, CM voltages can be
eliminated.
 They can operate with a lower switching frequency.
1.9 Types of Multilevel Inverters

Fig 1.17 Classification of Multilevel Inverters

In General, the multilevel inverters are classified as Single DC source and Multiple DC
sources or Several Separate DC Sources (SDCS).Both the Diode Clamped Multilevel Inverter
and the Flying Capacitor inverter comes under the category of Single DC source where the input
supply is taken from a single DC source.
1.10 Cascaded H-Bridge multilevel Inverter
The cascaded H-bridge multilevel Inverter uses separate dc sources (SDCSs). The
multilevel inverter using cascaded-inverter with SDCSs synthesizes a desired voltage from
several independent sources of dc voltages, which may be obtained from either batteries, fuel
cells, or solar cells. This configuration recently becomes very popular in ac power supply and
adjustable speed drive applications. This new inverter can avoid extra clamping diodes or voltage
balancing capacitors. Again, the cascaded multilevel inverters are classified depending the type
of DC sources used throughout the input.
A single-phase structure of an m-level cascaded inverter is each separate dc source
(SDCS) is connected to a single-phase full-bridge, or H-bridge, inverter. Each inverter level can
generate three different voltage outputs, +Vdc, 0, and –Vdc by connecting the dc source to the ac
output by different combinations of the four switches, S1, S2, S3, and S4. To obtain +Vdc,
switches S1 and S4 are turned on, whereas –Vdc can be obtained by turning on switches S2 and S3.
By turning on S1 and S2 or S3 and S4, the output voltage is 0. The ac outputs of each of the
different full-bridge inverter levels are connected in series such that the synthesized voltage
waveform is the sum of the inverter outputs.

(a) (b) (c)

Fig 1.18: Single phase structures of Cascaded inverter (a) 3-level, (b)5-level, (c) 7-level
One more alternative for a multilevel inverter is the cascaded multilevel inverter or series
H-bridge inverter. The series H-bridge inverter appeared in 1975. Cascaded multilevel inverter
was not fully realized until two researchers, Lai and Peng. They patented it and presented its
various advantages in 1997. Since then, the CMI has been utilized in a wide range of
applications. With its modularity and flexibility, the CMI shows superiority in high-power
applications, especially shunt and series connected FACTS controllers. The CMI synthesizes its
output nearly sinusoidal voltage waveforms by combining many isolated voltage levels. By
adding more H-bridge converters, the amount of Var can simply increased without redesign the
power stage, and build-in redundancy against individual H-bridge converter failure can be
realized. A series of single-phase full bridges makes up a phase for the inverter. A three-phase
CMI topology is essentially composed of three identical phase legs of the series-chain of H-
bridge converters, which can possibly generate different output voltage waveforms and offers the
potential for AC system phase-balancing. This feature is impossible in other VSC topologies
utilizing a common DC link. Since this topology consists of series power conversion cells, the
voltage and power level may be easily scaled. The dc link supply for each full bridge converter is
provided separately, and this is typically achieved using diode rectifiers fed from isolated
secondary windings of a three-phase transformer. Phase-shifted transformers can supply the cells
in medium-voltage systems in order to provide high power quality at the utility connection.
Features of CMLI
For real power conversions, (ac to dc and dc to ac), the cascaded-inverter needs separate
dc sources. The structure of separate dc sources is well suited for various renewable energy
sources such as fuel cell, photovoltaic, and biomass, etc.
Connecting separated dc sources between two converters in a back-to-back fashion is not
possible because a short circuit will be introduced when two back-to-back converters are not
switching synchronously. In summary, advantages and disadvantages of the cascaded inverter
based multilevel voltage source converter can be listed below.
Advantages and Disadvantages of CMLI.
i) The regulation of the DC buses is simple.
ii) Modularity of control can be achieved. Unlike the diode clamped and capacitor clamped
inverter where the individual phase legs must be modulated by a central controller, the full-
bridge inverters of a cascaded structure can be modulated separately.
iii) Requires the least number of components among all multilevel converters to achieve the
same number of voltage levels.
iv) Soft-switching can be used in this structure to avoid bulky and lossy resistor-capacitor-diode
snubbers.
Disadvantages
i) Communication between the full-bridges is required to achieve the synchronization of
reference and the carrier waveforms.
ii) Needs separate dc sources for real power conversions, and thus its applications are somewhat
limited
1.10.1 Symmetrical Cascaded H-Bridge multilevel Inverter
If all the input sources are of equal magnitude, it is known as Symmetrical H-Bridge
inverter as shown in fig 1.19 and the switching sequence is given in table 1.2. Here both the full
bridge inverters are fed with different sources of equal magnitude.

Fig 1.19: Symmetrical five level Cascaded H-Birdge inverter

In the above fig 1.19, each SDCS of equal magnitude is associated with a single-
phase full-bridge inverter. The ac terminal voltages of different level inverters are connected in
series. By different combinations of the four switches, S1-S4, each inverter level can generate
three different voltage outputs, +Vdc, -Vdc, and zero. The ac output of each of the different level
of full-bridge inverters are connected in series such that the synthesized voltage waveform is the
sum of the inverter outputs. In this topology, the number of output phase voltage levels is defined
by m = 2s+1, where s is the number of dc sources.
A 5-level cascaded-inverters will have two SDCSs and two full-bridge cells. The
switching table 1.2 for the five level cascaded inverter is shown below. Here, 2 Full Bridges are
used and are cascaded to each other. The Switches S1, S2, S3,and S4 are from upper H-Bridge
and Switches S5 S6 S7 and S8 are from lower H-Bridge .By giving correct switching patter n
,we get 5 voltage levels i.e 2Vdc,Vdc,0,-2Vdc,- Vdc, S1,S2,S5,D7 are on .To get 2Vdc,
S1,S2,S6,S5 are kept on .The switching table is shown below to get 5 levels with a Symmetrical
DC source.
Table 1.2 : Switching states of Symmetrical five level cascaded H-Bridge inverter

Switches ON Voltage level

S1, S2, S5 and D7 Vdc/2
S1, S2, S6and S5 Vdc
S1, S2, S6 and D8 Vdc/2
S1, D3, S6 and D8 0
S3, S4, S6 and D8 -Vdc/2
S3, S4, S7 and S8 -Vdc
S3, S4, D6 and S8 -Vdc/2
S1, S3, D6 and S8 0

Fig 1.20 Output waveform of Symmetrical Cascaded H-Bridge multilevel Inverter

1.10.2 Asymmetrical Cascaded H-Bridge multilevel Inverter
The cascaded H-Bridge multilevel inverter with two SDCS with unequal magnitude is
known as Asymmetrical Cascaded H-Bridge multilevel Inverter. The following is figure 1.21 of
Asymmetrical Cascaded H-Bridge multilevel Inverter where it is having 2 unequal DC sources
+2Vdc/3 and +Vdc/3.

Fig.1.21 Asymmetrical Cascaded H-Bridge multilevel Inverter

By using this type of Asymmetrical configuration, for a ‘n’ bridge inverter we can get
3n+1 voltage levels and n Capacitors of each rating nVdc/(n+1), Vdc/(n+1) to get Vdc max and
6n switches of each voltage rating is Vdc/(n+1).The following is the switching table of
Asymmetrical Cascaded H-Bridge multilevel Inverter.

Table 1.3: Switching states of Asymmetrical five level cascaded H-Bridge inverter
Switches ON Voltage level

S4, S2, S5 and S6 Vdc/3

S1, S2, S8 and S6 2Vdc/3
S1, S2, S5and S6 Vdc
S4, S2, S7 and S8 -Vdc/3
S3, S4, S6 and S8 -2Vdc/3
S3, S4, S7 and S8 -Vdc
S4, S2, S8 and S6 0
 CHAPTER 2

LITERATURE SURVEY

2.1 A New General Topology for Cascaded Multilevel Inverters with Reduced Number of
Components Based on Developed H-Bridge [1]

Nowadays, multilevel inverters have received more attention for their ability on high-
power and medium voltage operation and because of other advantages such as high power
quality, lower order harmonics, lower switching losses, and better electromagnetic interference.
These inverters generate a stepped voltage waveform by using a number of dc voltage sources as
the input and an appropriate arrangement of the power-semiconductor-based devices.

Three main structures of the multilevel inverters have been presented: “diode clamped
multilevel inverter,” “flying capacitor multilevel inverter,” and “cascaded multilevel inverter”.
The cascaded multilevel inverter is composed of a number of single-phase H-bridge inverters
and is classified into symmetric and asymmetric groups based on the magnitude of dc voltage
sources. In the symmetric types, the magnitudes of the dc voltage sources of all H-bridges are
equal while in the asymmetric types, the values of the dc voltage sources of all H-bridges are
different [1].

The main advantage of all these structures is the low variety of dc voltage sources, which
is one of the most important features in determining the cost of the inverter. On the other hand,
because some of them use a high number of bidirectional power switches, a high number of
insulated gate bipolar transistors (IGBTs) are required, which is the main disadvantage of these
topologies. The main disadvantage of this structure is related to its bidirectional power switches,
which cause an increase in the number of IGBTs and the total cost of the inverter. In, a new
topology with three algorithms have been presented, which reduce the number of required power
switches but increase the variety of dc voltage sources. In several algorithms for determining the
magnitudes of dc voltage sources for the conventional cascaded multilevel inverter have been
presented. The major advantage of this topology and its algorithms is related to its ability to
generate a considerable number of output voltage levels by using a low number of dc voltage
sources and power switches but the high variety in the magnitude of dc voltage sources is their
most remarkable disadvantage [1].

2.2 A Generalized Cascaded Multilevel Inverter Using Series Connection of Sub multilevel
Inverters [2]

Multilevel inverters include an array of power semi- conductors and dc voltage sources,
the output of which generate voltages with stepped waveforms. In comparison with a two-level
voltage-source inverter (VSI), the multilevel VSI enables to synthesize output voltages with
reduced harmonic distortion and lower electromagnetic interference. By increasing the number
of levels in the multilevel inverters, the output voltages have more steps in generating a staircase
waveform, which has a reduced harmonic distortion. However, a larger number of levels increase
the number of devices that must be controlled and the control complexity.

There are three well-known types of multilevel inverters: the neutral point clamped
(NPC) multilevel inverter, the flying capacitor (FC) multilevel inverter, and the cascaded H-
bridge (CHB) multilevel inverter. The NPC multilevel inverter, also called diode-clamped, can
be considered the first generation of multilevel inverter which was a three-level inverter. The
three-level case of the NPC multilevel inverters has been widely applied in different industries.
Unlike the NPC type, the FC multilevel inverter offers some redundant switching states that can
be used to regulate the capacitors voltage. However, the control scheme becomes complicated.
Moreover, the number of capacitors increases by increasing the number of voltage levels.

The CHB multilevel inverters use series-connected H-bridge cells with an isolated dc
voltage sources connected to each cell. The CHB multilevel inverters can be divided into two
groups from the viewpoint of values of the dc voltage sources: the symmetric and the
asymmetric topology. In the symmetric topology, the values of all of the dc voltage sources are
equal. This characteristic gives the topology good modularity. However, the number of the
switching devices rapidly increases by increasing the number of output voltage level. In order to
increase the number of output voltage level, the values of the dc voltage sources are selected to
be different, these topologies are called asymmetric. The CHB multilevel inverters have been
industrially employed in several applications fields such as pump, fans, compressors, etc. In
addition, they have recently been proposed for other applications like photovoltaic power-
conversion system and wind power conversion. The topologies discussed previously are the
conventional topologies. Many other multilevel inverter topologies have been introduced in
recent years. One of the topologies is the modular multilevel inverter. This topology is simpler
than the cascaded four-switch H-bridge-based inverter and has several advantages, such as
modular extension to any number of levels and redundancy. However, the topology does not
consider reduction in the number of components used. The multilevel inverter is based on
symmetric topology and uses series/parallel connection of the dc voltage sources. This topology
uses lower number of switches in comparison with the symmetric CHB multilevel inverter. The
topologies consider reduction in the components. These topologies are basically based on
asymmetric topologies; hence, the used dc voltage sources have different values. However, the
number of switching devices still remains high in these topologies. A nine-level active NPC
inverter has been which is the modification of the standard active NPC converter. A hybrid
multilevel inverter using the CHB and the diode-clamped topology [2].

Fig. 2.1 Proposed general multilevel inverter using series connection of m submultilevel
inverters, each one has n dc voltage sources.

A new multilevel inverter topology using series-connected submultilevel inverters. The

proposed multilevel inverter uses reduced number of switches. Initially, the proposed
submultilevel inverter is described and then the series connection of them to form a multilevel
inverter is discussed. The optimal structures of the proposed multilevel inverter regarding several
factors (e.g., number of switches, number of dc levels. Fig. 2.1 shows m sub multilevel inverters
in series. Each submultilevel inverter has n dc voltage source. The dc voltage sources in each
submultilevel inverter are equal. The output voltage of the submultilevel inverters (and series
connection of them) is always positive or zero. To operate as an inverter, it is necessary to
change the voltage polarity in every half cycle. For this purpose, an H-bridge inverter is added to
the output of the series connected sub multilevel inverters.

2.3 A Carrier-Based PWM Method with Optimal Switching Sequence for a Multilevel
Four-Leg Voltage-Source Inverter [3]

Compared to a two-level voltage-source inverter (VSI), multilevel VSI enables one to

synthesize output voltages with reduced harmonic distortion and lower electromagnetic
interference and also can operate at higher dc voltages using series connected switches. Even
though there are a few disadvantages such as an increased number of switches, a complicated
pulse width modulation (PWM) method, and a voltage balancing problems at the neutral point,
all the benefits make the multilevel VSI attractive in high power applications, and it has been
used since its first introduction in 1981. Multilevel diode-clamped VSIs are shown in Fig.1.
About multilevel VSIs have been focusing on the three-phase three-wire system, despite most
high power applications such as distributed generation, ac distribution, and transmission system
being set up as a three-phase four-wire system where, practically, a zero-sequence
voltage/current appears due to unbalanced and/or nonlinear loads or unbalanced source. When
custom power devices such as an active/reactive power filter, dynamic voltage restorer, and an
uninterruptible power system are required to be installed at the three-phase four-wire power
system, the ability to control both dq components and the zero-sequence component is necessary
for the power circuits. A four-leg VSI can be a promising candidate since the four-leg VSI
enables one to synthesize three output voltages independently. Compared to some other
topologies which are able to synthesize dq components and a zero-sequence component as well.
Therefore, this paper suggests a multilevel four-leg VSI as a power circuit for the high power
applications in a three phase four-wire system and also proposes a carrier-based PWM strategy
for this converter system, minimizing output voltage harmonics.

2.4 CARRIER-BASED PWM METHODS FOR A MULTILEVEL THREE-LEG VSI [3]

Various PWM strategies for a three-phase multilevel three leg VSI have been developed.
They could be generally classified into two groups, which are space vector method and carrier-
based method according to how to implement them.
 (a)

(b)

Fig. 2.2. Circuit diagram of a three-phase multilevel three-leg VSI, (a) three-level diode-clamped
VSI, and (b) five-level diode-clamped VSI.
 (a) (b)

(c)

Fig. 2.3 Output voltage planes of three-phase multilevel three-leg VSIs; N is the number of
levels. (a) Two-level three-leg VSI (N = 2). (b) Three-level PWM VSI (N = 3). (c) Five-level
PWM VSI (N = 5).

The space vector method needs to find three switching vectors (dotted in Fig. 2.6)
adjacent to a desired output voltage vector on a dq voltage plane as shown in Fig. 2.6. Once three
switching vectors are identified, the duties of the respective switching vectors should be
calculated, and then, it finally needs to arrange the respective switching vectors within a half of
switching period. The method to arrange the switching vectors with minimizing the harmonic
distortion of the output waveform, which will be referred to as “optimal switching sequence,” is
well known in case of a two-level VSI that the zero switching vectors should be spilt equally and
be placed at first and the last in the sequence. On the other hand, Celanovic and Boroyevich
introduced a simple and useful method for a multilevel VSI to find the switching vectors and to
calculate the duties of the respective vectors, but they did not propose how to achieve the optimal
switching sequence. Wang showed that the carrier-based PWM method for three-level three-leg
VSI was equivalent to the space vector method by introducing a specific zero-sequence voltage
similar to the two-level VSI. Introduced an optimal switching sequence that redundant switching
vector was split into two so as to occupy the first and last state of the switching sequence with
the same duration.

2.5 Comparison of the FPGA Implementation of Two Multilevel Space Vector PWM
Algorithms [4]

The term multilevel starts with the three-level inverter introduced by Nabae Nowadays,
multilevel converters are becoming increasingly popular in power applications, owing to their
ability to meet the increasing demand of power ratings and power quality associated with
reduced harmonic distortion and lower electromagnetic interference. Multilevel topologies have
been used as rectifiers for the connection of renewable energy sources to the utility grid and as a
power-conditioning system of variable speed wind turbines.

The combination of a large number of semiconductors to achieve high power ratings is

well established. Choosing an arrangement where all devices are individually controlled, rather
than switched together in series, provides more control opportunities. Voltage-source multilevel
inverter topologies synthesize a voltage waveform from several voltage levels typically obtained
from several capacitors or dc sources. The commutation of the power switches permits the
addition of the voltages of these sources, which reach high voltage at the output, whereas the
power semiconductors must withstand only reduced voltages.

By increasing the number of levels in the inverter, the output voltages have more steps in
generating a staircase waveform, which has a reduced harmonic distortion. However, a larger
number of levels increase the number of devices that must be controlled and the control
complexity. At present, there are no commercial digital signal processors (DSPs) having
appropriate built-in pulse width modulation (PWM) units that are enough to control the large
amount of switches used by multilevel converters. A software implementation of these PWM
units is very time-consuming. Therefore, a fast and expensive DSP is needed to carry out the
modulation and the control processes. An architecture where one field programmable gate array
(FPGA) carries out the modulation task and one DSP implements the control strategy is better
suited for multilevel converters. Thus, cheap DSP and FPGA are needed.

Since the concept of multilevel PWM converter was introduced, various modulation
strategies have been developed and studied in detail, such as multilevel sinusoidal PWM,
multilevel selective harmonic elimination, and space vector modulation. Among these strategies,
the space vector PWM (SVPWM) stands out because it offers significant flexibility to optimize
switching waveforms and is well suited for digital implementation. Complexity and
computational cost of traditional SVPWM techniques increase with the number of levels of the
converter, and most of all use trigonometric functions or precomputed tables. The 2-D SVPWM
algorithm proposed by Celanovic and Boroyevich and the 3-D calculate the switching vectors
and the times without using angles, trigonometric functions, or precomputed tables. In addition,
the complexity and the computational cost are very low. These efficient modulation algorithms
are very useful to real-time computation of the switching sequence and the ON-state durations of
the respective switching state vectors corresponding to the modulation of multilevel inverters.
Moreover, the numeric evaluation of the n-state durations is reduced to a simple addition, and
both methods use the minimum number of possible comparators [4].

The implementation in an FPGA of a SVPWM control for a two-level inverter has been
described. An FPGA was also used in to control a three-level neutral point-clamped (NPC)
inverter in wind turbine applications. Two multilevel SVPWM algorithms are analyzed and
implemented into an FPGA. A detailed description of the very high speed integrated circuit
hardware description language (VHDL) implementation realized is given. To develop all the
tasks involved, Matlab Simulink and System Generator for Simulink tools are used as well as
Foundation ISE tools. Both implementations have been compared in terms of implementation
complexity and resources of the FPGA used. Finally, both implementations have been tested
with an NPC inverter.

2.6 Hybrid Multilevel Inverter Using Switched Capacitor Units [5]

 The switched capacitor multilevel inverter can produce the desired sinusoidal voltage
waveform and boost the input voltage without any bulky transformer. Because of the inherent
voltage unbalancing of capacitors in the switched capacitor multilevel inverters, using
complicated capacitor voltage balancing is necessary. Capacitor voltage balancing techniques
will be more complex when higher number of voltage levels is produced at the output. In order to
mitigate this problem, the hybrid-source switched capacitor topologies can be used. By using this
kind of inverter with fewer switching devices and simpler control methods, it is possible to
achieve a greater number of voltage levels at the output. The hybrid source switched capacitor
topologies can be used in electric vehicle application and PV systems.

Fig.2.4. Basic unit.

Fig. 2.5 (a) Capacitor charging (vL = vc = vdc). (b) Capacitor discharging (iL = ic = is).

The multilevel inverters that use series–parallel connection of dc voltage source and
capacitors attract more attention due to simple control for capacitor voltage control. Combination
of the conventional series and the series–parallel switched capacitor multilevel inverters. The
topologies have a modular structure and can benefit the advantages of the series multilevel
inverters. The fundamental switching method is used in this investigation. In addition, to produce
all voltage levels at the output (even and odd), a new algorithm for the determination of the
magnitude of the isolated dc voltage sources is proposed. Finally, the loss calculation is done,
and the performance of the proposed topologies is verified by simulation and experimental
results of single-phase 25- and 17-level inverters.

2.7 BASIC UNIT

Fig. 2.4 shows the basic unit for the proposed multilevel inverter. The switches P and S
connect the capacitor in parallel and series with the dc voltage source, respectively. When the
switch P is turned on, the capacitor is charged to the voltage Vdc, and when the switch S is
turned on, the capacitor starts to discharge. It should be noted that the switches P and S have
complementary operation with each other. It means that, when the switch P is on, the switch S
must be off and vice versa. Otherwise, a shorted circuit occurs across the dc voltage source.
When the switch S conducts, the diode D becomes reverse biased and prevents capacitor
discharging to the dc voltage source. Thus, in the case of series connection of the capacitor and
dc voltage source (S is on), the capacitor current only flows to the load. Fig. 2.5 shows the
operating modes of the basic unit.

Fig. 2.6. Switched capacitor unit.

Fig. 2.6 shows the proposed switched capacitor unit. This topology is yield from series
combination of several basic units. In this figure, the switches Si (i = 1,2, . . . , n) connect the
capacitors in series, and the switches Pi connect the capacitors in parallel with the dc voltage
sources. To produce zero and negative voltage levels, an H-bridge has been used at the output.
 CHAPTER 3

PROPOSED CONCEPT

3.1 INTRODUCTION

The demand for high-voltage high-power inverters is increasing, and it is impossible to

connect a power semiconductor switch to a high-voltage network directly. Therefore, multilevel
inverters had been introduced and are being developed now. With an increasing number of dc
voltage sources in the input side, a sinusoidal like waveform can be generated at the output. As a
result, the total harmonic distortion (THD) decreases, and the output waveform quality increases,
which are the two main advantages of multilevel inverters. In addition, lower switching losses,
lower voltage stress of dv/dt on switches, and better electromagnetic interference are the other
most important advantages of multilevel inverters [1]–[5]. These kinds of inverters are generally
divided into three main categories, i.e., neutral-point-clamped multilevel inverters, flying
capacitor multilevel inverters, and cascaded multilevel inverters [6]–[9]. There is no diode
clamped or flying capacitors in cascaded multilevel inverters. Moreover, these inverters consist
of modularity, simplicity of control, and reliability, and they require the lowest number of power
semiconductor devices to generate a particular level [1], [10], [11]. As a result, the losses and
total cost of these inverters decrease, and the efficiency will increase [12].

Fig. 1.1 Proposed basic unit.

 TABLE 3.1

PERMITTED TURN ON AND OFF STATES FOR SWITCHES IN THE PROPOSED BASIC
UNIT

These inverters are comprised of a series connection of basic units, which consist of
different arrays of power switches and dc voltage sources. Generally, these inverters are divided
into two main groups, i.e., symmetric cascaded multilevel inverters with the same amplitude of
dc voltage sources and asymmetric cascaded multilevel inverters. The asymmetric cascaded
multilevel inverters generate a higher number of output levels in comparison with the symmetric
cascaded multilevel inverters with the same number of power electronic devices because of the
different amplitude of its dc voltage sources. As a result, the installation space and total cost of
an asymmetric cascaded multilevel inverter is lower than that of a symmetric cascaded multilevel
inverter [11], [12].

Up to now, different basic units and, thus, different cascaded multilevel inverters have
been presented in literature. In [13]– [18], different symmetric cascaded multilevel inverters have
been presented. Another topology with two different algorithms as symmetric and asymmetric
inverters have been also presented in [19]. The main disadvantages of the symmetric inverters
are the high required numbers of power switches, insulated-gate bipolar transistors (IGBTs),
power diodes, and driver circuits because of the same magnitude of dc voltage sources.
 Fig. 3.2. Cascaded multilevel inverter. (a) Proposed topology. (b) Developed proposed
topology.

These disadvantages will be higher in topologies where bidirectional power switches

from the voltage point of view have been used, as presented in [15] and [19]. Each unidirectional
switch requires an IGBT with an antiparallel diode and a driver circuit, whereas a bidirectional
switch includes two IGBTs, two antiparallel diodes, and one driver circuit if a common emitter
configuration is used. However, both unidirectional and bidirectional power switches conduct
current in both directions. In order to increase the number of output levels, different asymmetric
cascaded multilevel inverters have been presented in [12], [14], [19], and [20]. The main
disadvantages of these inverters are the high magnitudes of dc voltage sources.

In order to increase the number of generated output levels by using a lower number of
power electronic devices, a new basic unit is proposed in this paper. By a series connection of
several proposed basic units, a new cascaded multilevel inverter is proposed. Then, to generate
all positive and negative levels at the output, an H-bridge will be added to this inverter because
the proposed inverter only generates positive levels. This inverter is called the developed
proposed cascaded multilevel inverter. In order to generate all voltage levels at the output, four
different algorithms are proposed. Several comparisons are also done between the developed
cascaded multilevel inverter and its proposed algorithms with the conventional cascaded
inverters. Based on these comparisons, the developed cascaded inverter requires the minimum
number of power switches, IGBTs, power diodes, driver circuits, and dc voltage sources. Finally,
in order to investigate the capability of the developed cascaded inverter to generate all voltage
levels, the experimental results of a 15-level inverter are used.

3.2 PROPOSED TOPOLOGY

Fig. 3.1 shows the proposed basic unit. As shown in Fig. 3.1, the proposed basic unit is
comprised of three dc voltage sources and five unidirectional power switches. In the proposed
structure, power switches (S2, S4), (S1, S3, S4, S5), and (S1, S2, S3, S5) should not be
simultaneously turned on to prevent the short circuit of dc voltage sources. The turn on and off
states of the power switches for the proposed basic unit are shown in Table 3.1, where the
proposed basic unit is able to generate three different levels of 0, V1 + V3, and (V1 + V2 +V3)
at the output. It is important to note that the basic unit is only able to generate positive levels at
the output.

It is possible to connect n number of basic units in series. As this inverter is able to

generate all voltage levels except V1, it is necessary to use an additional dc voltage source with
the amplitude of V1 and two unidirectional switches that are connected in series with the
proposed units. The proposed cascaded inverter that is able to generate all levels is shown in Fig.
3.2(a). In this inverter, power switches S’1 and S’2 and dc voltage source V1 have been used to
produce the lowest output level. The amplitude of this dc voltage source is considered V1 = Vdc
(equal to the minimum output level). The output voltage level of each unit is indicated by vo, 1,
vo, 2, . . . , vo, n, and vo. The output voltage level vo of the proposed cascaded multilevel
inverter is equal to

(3.1)

The generated output voltage levels of the proposed inverter are shown in Table 3.2. As
aforementioned and according to Table 3.2, the proposed inverter that is shown in Fig. 3.2(a) is
only able to generate positive levels at the output. Therefore, an H-bridge with four switches T1
T4 is added to the proposed topology. This inverter is called the developed cascaded multilevel
inverter and is shown in Fig. 3.2(b). If switches T1 and T4 are turned on, load voltage vL is equal
to vo, and if power switches T2 and T3 are turned on, the load voltage will be −vo. For the
proposed inverter, the number of switches Nswitch and the number of dc voltage sources Nsource are
given by the following equations, respectively,

Table 3.2

Generated Output Voltage Levels Vo Based On The Off And On States Of Power Switches

Table 3.3

Proposed Algorithms And Their Related Parameters

 (3.2)

(3.3)

Where n is the number of series-connected basic units. As the unidirectional power

switches are used in the proposed cascaded multilevel inverter, the number of power switches is
equal to the numbers of IGBTs, power diodes, and driver circuits. The other main parameter in
calculating the total cost of the inverter is the maximum amount of blocked voltage by the
switches. If the values of the blocked voltage by the switches are reduced, the total cost of the
inverter decreases. In addition, this value has the most important effect in selecting the
semiconductor devices because this value determines the voltage rating of the required power
devices. Therefore, in order to calculate this index, it is necessary to consider the amount of the
blocked voltage by each of the switches. According to Fig. 3.2(b), the values of the blocked
voltage by switches are equal to

(3.4)

(3.5)

(3.6)

(3.7)

(3.8)

Where Vo, max is the maximum amplitude of the producible output voltage. Therefore, the
maximum amount of the blocked voltage in the proposed inverter Vblock is equal to
(3.9)
 Fig. 3. Cascaded multilevel inverters.

(a) Conventional cascaded multilevel inverter R2 for V1 = V2 = · · · = Vn = Vdc [14],

R3 for V1 = Vdc, V2 =· · · = Vn = 2Vdc [12], and R4 for V1 = Vdc, V2 = · · · = Vn = 3Vdc
[20]. (b) Presented topology in [17], with R7 for V1 = V2 = · · · = Vn = Vdc. (c) Presented
topology in [19], with R8 for V1 = V2 = · · · = Vn = Vdc and R9 for V1 = Vdc, V2 = · · · = Vn
= 2Vdc. (d) Presented topology in with R10. (e) Presented topology in [16], with R6 for V1 = V2
= · · · =Vn = Vdc. (f) Presented topology in [15], with R5 for V1 = V2 = · · · = Vn =Vdc. (g)
Presented topology in [13], with R1 for V1 = V2 = · · · = Vn = Vdc.

In (3.9), Vblock,j, V’block , and Vblock, H indicate the blocked voltage by the jth basic unit,
the additional dc voltage sources, and the used H-bridge, respectively.

Fig.3.4. Variation of NIGBT versus Nlevel.

 Fig. 3.5. Variation of Ndriver versus Nlevel.

Fig. 3.6. Variation of Nsource versus Nlevel.

Fig. 3.7. Variation of V block versus N level.

In the developed inverter, the number and maximum amplitude of the generated output
levels are based on the value of the used dc voltage sources. Therefore, four different algorithms
are proposed to determine the magnitude of the dc voltage sources. These proposed algorithms
and all their parameters are calculated and shown in Table 3.3. According to the fact that the
magnitudes of all proposed algorithms except the first algorithm are different, the proposed
cascaded multilevel inverter based on these algorithms is considered an asymmetric cascaded
multilevel inverter. In addition, based on the equations of the maximum output voltage levels and
its maximum amplitude, it is clear that these values in the asymmetric cascaded multilevel
inverter are more than those in the symmetric cascaded multilevel inverters with the same
number of used dc voltage sources and power switches.

3.3 Comparing The Proposed Topology With The Conventional Topologies

The main aim of introducing the developed cascaded inverter is to increase the number of
output voltage levels by using the minimum number of power electronic devices. Therefore,
several comparisons are done between the developed proposed topology and the conventional
cascaded inverters from the numbers of IGBTs, driver circuits, and dc voltage sources points of
view. In addition, the maximum amount of the blocked voltage by the power switches is also
compared between the proposed inverter and the other presented topologies. In this comparison,
the proposed cascaded inverter that is shown in Fig. 3.2(b) with its proposed algorithms is
represented by P1 to P4, respectively. In [13], a symmetric cascaded multilevel inverter has been
presented that is shown by R1 in this comparison. The H-bridge cascaded multilevel inverter has
been presented in [14]. This inverter is represented by R2. In addition, two other algorithms have
been presented for the H-bridge cascaded inverter in [12] and [20] that are represented by R3 and
R4, respectively.
 Fig. 3.8. Cascaded 15-level inverter based on the proposed basic unit.

In [15]–[17], three other symmetric cascaded multilevel inverters have been presented.
These inverters are shown by R5−R7, respectively. The other cascaded multilevel inverter with
two different algorithms has been presented in [19]. This inverter with its algorithms is
represented by R8 and R9, respectively. Another symmetric cascaded multilevel inverter that has
been presented in [18] is represented by R10 in this comparison. Fig. 3.3 indicates all of the
aforementioned cascaded multilevel inverters.

Fig. 3.4 compares the number of IGBTs of the proposed topology with the other
aforementioned cascaded multilevel inverters. As it is obvious, the proposed inverter needs a
lower number of IGBTs to generate a specific level. In addition, the fourth proposed algorithm
has the best performance among all of the proposed algorithms for the developed cascaded
inverter. However, in this comparison, the unidirectional power switches have been used in many
of the considered cascaded inverters. As aforementioned, the number of used IGBTs is equal to
the number of power diodes. As a result, the number of required power diodes in the fourth
proposed algorithm of the developed topology is lower than that of the other aforementioned
inverters and their proposed algorithms.
 Fig. 3.5 indicates the comparison of the proposed cascaded inverter with other
aforementioned topologies from the point of view of the number of driver circuits. As each
switch requires a separate driver circuit, the number of driver circuits is equal to the number of
power switches. Therefore, this comparison also indicates the number of required power
switches in the cascaded multilevel inverters. As shown in Fig. 3.5, the number of driver circuits
based on the fourth proposed algorithm of the developed cascaded inverter is lower than that of
the other proposed algorithms for this inverter and other aforementioned cascaded inverters.

Fig. 3.6 compares the number of dc voltage sources of the proposed topology with the
other aforementioned cascaded inverters. As it is obvious, the number of required dc voltage
sources in the developed inverter is less than that in the other presented inverters in literature.
This difference will be higher while the fourth proposed algorithm is considered.

Fig. 3.7 compares the maximum amount of the blocked voltage by the power switches in
the proposed topology with the other aforementioned inverters. As it is obvious, this value in the
proposed inverter is less than that in the other presented inverters except the H-bridge inverter
and presented topologies by R7 and R10. However, this is the main disadvantage of the proposed
cascaded inverter, but this inverter has different advantages in comparison to the H-bridge
cascaded inverter and the presented topologies by R7 and R10, such as its required lower
numbers of IGBTs, driver circuits, and dc voltage sources. It is pointed out that all values are
considered in per unit (p.u.), and Vdc is used as the base value in the per-unit system.

As it is obvious from the aforementioned comparisons, the developed proposed inverter

has the best performance among all of the aforementioned multilevel topologies. Reduction in
the numbers of required IGBTs, power diodes, driver circuits, and dc voltage sources, and the
amount of the blocked voltage by the power switches are remarkable advantages of the proposed
inverter that were obtained from comparisons. These advantages lead to reduction in the
installation space and total cost of the inverter. These features will have the most influence when
the fourth proposed algorithm is used.
 CHAPTER 4

MATLAB AND SIMULINK RESULTS

4.1 INTRODUCTION TO MATLAB:

The name MATLAB stands for MATrix LABoratory. MATLAB was written originally
to provide easy access to matrix software developed by the LINPACK (linear system package)
and EISPACK (Eigen system package) projects.

MATLAB is a high-performance language for technical computing. It integrates

computation, visualization, and programming environment. Furthermore, MATLAB is a modern
programming language environment: it has sophisticated data structures, contains built-in editing
and debugging tools, and supports object-oriented programming. These factors make MATLAB
an excellent tool for teaching and research.

MATLAB has many advantages compared to conventional computer languages (e.g., C,

FORTRAN) for solving technical problems. MATLAB is an interactive system whose basic data
element is an array that does not require dimensioning. The software package has been
commercially available since 1984 and is now considered as a standard tool at most universities
and industries worldwide.

It has powerful built-in routines that enable a very wide variety of computations. It also
has easy to use graphics commands that make the visualization of results immediately available.
Specific applications are collected in packages referred to as toolbox. There are toolboxes for
signal processing, symbolic computation, control theory, simulation, optimization, and several
other fields of applied science and engineering.

4.2 MATLAB/ SIMULATION RESULTS:

 CHAPTER 5

CONCLUSION

In this paper, a new basic unit for a cascaded multilevel inverter is proposed. By the
series connection of several basic units, a cascaded multilevel inverter that only generates
positive levels at the output is proposed. Therefore, an H-bridge is added to the proposed inverter
to generate all voltage levels. This inverter is called the developed cascaded multilevel inverter.
In order to generate even and odd voltage levels at the output, four different algorithms are
proposed to determine the magnitude of the dc voltage sources. Then, several comparisons are
done between the developed proposed single-phase cascaded inverter and its proposed
algorithms with cascaded multilevel inverters that have been proposed in literature. According to
these comparisons, the developed proposed cascaded topology requires less numbers of IGBTs,
power diodes, driver circuits, and dc voltage sources than other presented cascaded topologies in
literature. These features will be remarkable while the fourth proposed algorithm is used for the
developed cascaded inverter. For instance, in order to generate a minimum of 63 levels at the
output, the developed cascaded topology based on the fourth proposed algorithm needs 19 power
diodes, IGBTs, and driver circuits, and 10 dc voltage sources. However, the cascaded multilevel
inverter that was presented in [20] requires 44 power diodes, IGBTs, and driver circuits, and 11
dc voltage sources. Therefore, the developed proposed inverter has better performance and needs
minimum number of power electronic devices that lead to reduction in the installation space and
total cost of the inverter. Finally, the accuracy performance of the developed proposed single
phase cascaded multilevel inverter in generating all voltage levels is verified by using the
experimental results on a 15-level inverter.
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