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Electronic Theses, Treatises and Dissertations The Graduate School

2010

Development and Implementation of a 25


kVA Phasor-Based Virtual Machine
Fletcher Fleming

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THE FLORIDA STATE UNIVERSITY

COLLEGE OF ENGINEERING

DEVELOPMENT AND IMPLEMENTATION OF A 25 kVA PHASOR-BASED

VIRTUAL MACHINE

By

FLETCHER FLEMING

A Thesis submitted to the


Electrical and Computer Engineering Department
in partial fulfillment of the
requirements for the degree of
Master of Science

Degree Awarded:
Summer Semester, 2010
The members of the committee approve the thesis of Fletcher Fleming defended on
July 2nd, 2010.

Chris S. Edrington
Professor Directing Thesis

Mischa Steurer
Committee Member

Linda DeBrunner
Committee Member

Mark H. Weatherspoon
Committee Member

Approved:

Simon Y. Foo, Chair, Electrical and Computer Engineering Department

Ching-Jen Chen, Dean, College of Engineering

The Graduate School has verified and approved the above-named committee members.

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ACKNOWLEDGEMENTS
First, I want to thank my research and academic advisors Mischa Steurer PhD and
Chris S. Edrington PhD, respectively, for their continuous support of my research and
involving me in the Virtual Machine Project in the first place. Their provisions, whether
computer or power equipment needs, office and lab space, or maintaining funding made
this thesis possible. Dr. Steurer’s comprehension of power systems,
power-hardware-in-the-loop studies, and technical direction of my research profoundly
increased my involvement with the Virtual Machine Project and my understanding of the
related fields. He taught me how to independently investigate, prepare, present, and
defend technical data and claims in a concise, professional and scientific manner (which
applies to much more than research!). Thank you for making me a better engineer and
more prepared individual. Dr. Edrington’s never ending guidance and faith when I
doubted myself taught me never to give up; that focusing and working harder through the
problem was the path to growth (both intellectually and personally). He helped edit this
thesis, taught me how to write technical papers and be self-critical, gave me multiple
opportunities to explore the scientific community (even in China!) and was always there
to meet and talk about my ideas and problems, asking questions where needed. Most of
all my two advisors taught me how to approach a problem and accomplish any goal
through both scientific and practical planning and analyses.
Special thanks go to those who helped implement and experimentally validate the
Virtual Machine. Foremost, Oleg Vodyakho PhD for taking countless hours out of his
busy schedule to personally oversee that my developmental approach was carried out
safely and effectively. His tough love taught me numerous practical lab skills:
consistency, time efficiency, and how to use the resources available to my advantage
(whether it be simulations, analytical procedures, oscilloscopes for debugging, others
with professional experience, reconfiguring hardware, etc.). Furthermore, he also helped
edit this thesis. I really appreciate it; you are truly a friend and mentor. Thanks to the
senior engineering design technician, John Haurer for the many safety consultations and
necessary installations and reconfigurations of various system components needed to
interface and debug my research. Thanks to Dominik Neumayr, whose previous work and
experience in the lab greatly facilitated my learning, understanding, operation and

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capability with all of the amplifier equipment. He and Jesse Leonard spent many hours
assisting in the operation of the two converters which are physically 30 meters apart,
requiring multiple people for safe operation. Thank you to my family who are all very
patient and loving as I attempt to cross higher academic limits. Everyone who contributed
that was not specifically named I thank you too. During my course of work at Florida
State University (2007-2010), I was supported by Office of Naval Research (ONR) Grant
Number N00014-04-1-0664.

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TABLE OF CONTENTS

LIST OF FIGURES ...................................................................................................... VII

LIST OF TABLES ........................................................................................................... X

LIST OF ABBREVIATIONS ........................................................................................ XI

ABSTRACT................................................................................................................... XII

CHAPTER 1 ...................................................................................................................... 1

1.1 MOTIVATION................................................................................................................. 1

1.2 HARDWARE-IN-THE-LOOP........................................................................................ 2
1.2.1 Controller-Hardware-in-the-Loop................................................................................. 4
1.2.2 Power-Hardware-in-the-Loop ....................................................................................... 4
1.2.3 Interface Filter ............................................................................................................... 6

1.3 LITERARY REVIEW ..................................................................................................... 7

1.4 VM CONCEPT............................................................................................................... 15
1.4.1 Achieving Power Flow ................................................................................................. 17
1.4.2 Thesis Statement........................................................................................................... 19

CHAPTER 2 .................................................................................................................... 22

2.1 SYSTEM DESCRIPTION............................................................................................. 22

2.2 TEST BED MODIFICATIONS .................................................................................... 24


2.2.1 Motor Drives ................................................................................................................ 25
2.2.2 Output Sine Filter......................................................................................................... 27
2.2.3 dSPACETM Control System........................................................................................... 30
2.2.4 Real-Time Digital Simulator........................................................................................ 31

CHAPTER 3 .................................................................................................................... 33

3.1 VSD DRIVE CONTROLS............................................................................................. 36


3.1.1 Rectifier Controls......................................................................................................... 36
3.1.2 Motor-Side Inverter Controls....................................................................................... 38

3.2 25 KVA AMPLIFIER VM CONTROL ALGORITHM............................................. 41


3.2.1 Impedance Scaling References..................................................................................... 43
3.2.2 Phasor-based current control: Proof of Concept ........................................................ 45

3.3 SIMULATION MODEL AND RESULTS................................................................... 46

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CHAPTER 4 .................................................................................................................... 51

4.1 VM DEVELOPMENT, IMPLEMENTATION, AND RESULTS ............................. 51

4.2 VALIDATION VIA PHYSICAL IM............................................................................ 56

4.3 LIMITATIONS .............................................................................................................. 61

4.4 FUTURE WORK ........................................................................................................... 63

4.5 CONCLUSION............................................................................................................... 64

APPENDIX A .................................................................................................................. 66

A.1 MACHINES .................................................................................................................... 66

A.2 25 KVA INTERFACE VOLTAGE AMPLIFIER....................................................... 67

A.3 45 KVA Δ-Y, 208/480 TRANSFORMER ..................................................................... 70

APPENDIX B .................................................................................................................. 72

B.1 REFERENCE FRAME THEORY ............................................................................... 72

B.2 IM MODELING ............................................................................................................. 76


B.2.1 Single Phase Equivalent IM Circuit (Phasor-based)................................................... 76
B.2.2 Differential Equation based Three-Phase IM Model................................................... 78
B.2.3 VSS (RSCAD) Model.................................................................................................... 81

B.3 MODULATION STRATEGIES ................................................................................... 82


B.3.1 Hysteresis Modulation ................................................................................................. 82
B.3.2 Sine Triangle Pulse Width Modulation ........................................................................ 83
B.3.3 Space Vector Modulation............................................................................................. 85

APPENDIX C .................................................................................................................. 88

C.1 DERIVATION ................................................................................................................ 88

C.2 MATLAB SCRIPT......................................................................................................... 90

C.3 SCRIPT RESULTS ........................................................................................................ 91

REFERENCES................................................................................................................ 93

BIOGRAPHICAL SKETCH ......................................................................................... 99

PUBLICATION LIST .................................................................................................. 100

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LIST OF FIGURES
Figure 1-1: HIL examples................................................................................................... 3

Figure 1-2: CHIL system flow diagram - generic example ................................................ 4

Figure 1-3: PHIL signal flow diagram - voltage drive example......................................... 5

Figure 1-4: Amplifier-HUT LCL interface filter ................................................................ 6

Figure 1-5: Generic electric machine operation................................................................ 16

Figure 1-6: VM Concept: Open-loop VSD PHIL test scenario ........................................ 17

Figure 1-7: VM PHIL power flow vector diagram........................................................... 18

Figure 2-1: VM test bed flow chart................................................................................... 24

Figure 2-2: Standard two-level, six pulse converter topology.......................................... 26

Figure 2-3: Open cabinet view of VSD and DC drive...................................................... 27

Figure 2-4: System implementation of VSD output voltage ripple filter ......................... 28

Figure 2-5: Experimental implementation of VSD output voltage ripple filter................ 28

Figure 2-6: VSD connected to transformer without ripple filter ...................................... 29

Figure 2-7: VSD connected to transformer with ripple filter, R=2Ω................................ 29

Figure 2-8: VSD connected to transformer with ripple filter, R=1Ω................................ 30

Figure 3-1: Detailed VM test bed flow chart .................................................................... 35

Figure 3-2: Sinusoidal AFE vector control block diagram............................................... 37

Figure 3-3: Steady state IM torque-speed relationship for linear V/Hz ratios.................. 40

Figure 3-4: Closed-loop V/Hz IM slip control ................................................................. 40

Figure 3-5: Outer-loop speed control, inner-loop current control .................................... 41

Figure 3-6: Phasor-based amplifier VM control strategy ................................................. 42

Figure 3-7: Equivalent circuit of coupling network.......................................................... 45

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Figure 3-8: Simulink switching converter test bed model ................................................ 46

Figure 3-9: Simulated synchronized current flow, 480V 60Hz........................................ 47

Figure 3-10: Simulated real power flow via phase shift, 480V 60Hz .............................. 48

Figure 3-11: Simulated VM vs IM steady state terminal characteristics.......................... 49

Figure 3-12: Simulated VM start-up transient response, 160V 20Hz .............................. 50

Figure 4-1: Synchronized converters: Transformer voltages and current ........................ 51

Figure 4-2: Non-synchronized converters: Current drawn via magnitude difference ...... 52

Figure 4-3: Open-loop VM current references, Id =10A................................................... 53

Figure 4-4: Open-loop VM current references, Iq =10A................................................... 54

Figure 4-5: VM control, VSD terminal characteristics, 100VLL 30Hz, 1.5% loaded....... 55

Figure 4-6: Experimental VM start-up transient response, 160VLL 20Hz........................ 56

Figure 4-7: Experimental VM vs IM terminal characteristics, 240VLL 30Hz, unloaded.. 57

Figure 4-8: VM vs IM experimental FFT; 240VLL 30Hz; unloaded ................................ 58

Figure 4-9: Experimental VM vs IM terminal characteristics, 160VLL 20Hz, 2% load ... 59

Figure 4-10: Experimental VM vs IM terminal characteristics, 160VLL 20Hz, 4% load . 59

Figure 4-11: VM vs IM experimental FFT, 160VLL 20Hz, 2% load ................................ 60

Figure 4-12: VM vs IM experimental FFT, 160VLL 20Hz, 4% load ................................ 61

Figure A-1: Test bed IM and DC load .............................................................................. 67

Figure A-2: Open cabinet view of 25 kVA interface voltage amplifier ........................... 70

Figure A-3: Open cabinet view of 45 kVA Δ-Y, 208/480 transformer ............................ 71

Figure B-1: Trigonometric relationship for stationary abc to arbitrary dq0 transform .... 73

Figure B-2: Single phase equivalent IM circuit, including rotor copper losses................ 77

Figure B-3: Single phase equivalent circuit, neglecting core and rotor copper losses ..... 78

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Figure B-4: RSCAD IM Model, VSD connected ............................................................. 81

Figure B-5: Operation principle of HCC; courtesy of [65]............................................... 82

Figure B-6: SPWM switching logic.................................................................................. 84

Figure B-7: SVM control flow.......................................................................................... 85

Figure B-8: Eight possible converter switching states...................................................... 86

Figure B-9: SVM output voltage state diagram................................................................ 86

Figure B-10: Vs decomposed into adjacent sectors........................................................... 87

Figure C-1: Equivalent circuit of coupling network, mesh analysis shown ..................... 88

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LIST OF TABLES
Table 1: Converter coupling network frequency independent parameters ....................... 43

Table 2: Frequency dependent voltage drop calculations................................................. 45

Table 3: IM nameplate parameters ................................................................................... 66

Table 4: IM equivalent circuit parameters ........................................................................ 66

Table 5: DC machine nameplate parameters .................................................................... 67

Table 6: Voltage amplifier technical specifications.......................................................... 69

Table 7: Technical specifications of the 45 kVA transformer.......................................... 71

Table 8: Figure B-1 transformation variable description.................................................. 73

Table 9: Description of variables in IM derivations ......................................................... 79

Table 10: Script results proving current flow concept...................................................... 92

x
LIST OF ABBREVIATIONS
AFE: Active Front End
CHIL: Controller-Hardware-in-the-Loop
dSPACE: Digital Signal Processing and Control Engineering
DIM: Damping Impedance Method
DURIP: Defense University Research Instrumentation Program
FFT: Fast Fourier Transform
FPGA: Field Programmable Gate Array
HCC: Hysteresis Current Control
HIL: Hardware in the Loop
HUT: Hardware under test
IGBT: Insulated-Gate Bipolar Transistor
I/O: Input/Output
IM: Induction Machine
INV: Inverter
ITM: Ideal Transformer Model
LinVerter: Quasi Linear-Inverter
MHIL: Mechanical Hardware in the Loop
PEBB: Power Electronics Building Block
PCD: Partial Circuit Duplication
PEC: Power Electronics Controller
PHIL: Power-Hardware-in-the-Loop
PLL: Phase Lock Loop
PI: Proportional-Integral
RFT: Reference Frame Theory
RTDS Real Time Digital Simulator
SVM: Space Vector Modulation
SPWM: Sine Wave Pulse Width Modulation
TFA: Time-variant First-Order Approximation
THD: Total Harmonic Distortion
TLM: Transmission Line Model
VTB-RT: Virtual Test Bed Real-Time
VSD: Variable Speed Drive
VSS: Virtually Simulated System
VM: Virtual Machine

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ABSTRACT
A motor drive system should be reliable, efficient, and robust under numerous
applications, loads, and control schemes. To ensure such characteristics and fully test the
range of operation for a motor drive, manufacturers and developers traditionally must
have a wide assortment of test bed equipment to recreate various machine load
combinations. During motor drive development stages, expensive hardware is exposed to
faulting and instability risks prior to completely debugging the product. The associated
risks and expenditures increase with the power level. Therefore, this thesis provides a
motor drive testing method, deemed the “virtual machine,” (VM) that removes a great
deal of the risk and cost associated with motor drive development and validation. The
technique used to accomplish the VM exploits the Power-Hardware-in-the-Loop (PHIL)
concept to replace equipment; particularly a voltage amplifier is used to recreate the
terminal characteristics of various machine loading scenarios that a motor drive is
conventionally tested against. A unique transformer coupling network is proposed
between the amplifier and motor drive to provide decoupling and properly step voltages.
By implementing the VM concept on such a transformer coupled PHIL test bed, potential
pitfalls and non-linearities due to the transformer can be assessed; thus, providing the
field with a new PHIL filter structure and de-risking the design prior any future
increments in power level. When validating, the VM shows matching, consistent results
compared against both simulations and a physical induction machine (IM) energized via
the same motor drive. Note that multiple counter torque loads were provided via a DC
machine. Although the proposed amplifier control method is based on a steady state
phasor system, it also proves adequate for recreating the transient terminal characteristics
of an IM across the line start. The conclusion proves the VM concept a viable solution for
removing cost and risk in drive development as well as verifies the PHIL transformer
coupling network. The concept of controlling active and reactive power flow between
parallel connected LCL coupled converters is established then applied as a PHIL
technique; thus, opening the field to use this approach for evaluating more complex,
simulated systems. The limitations of the proposed method are discussed as well as future
work areas to address such constrictions and improve the fidelity of the VM. Finally,

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after polishing the limitations, a future direction of increasing the VM power level is
established and some derivatives of the PHIL load emulation concept given.

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CHAPTER 1
INTRODUCTION
1.1 Motivation
Higher level power electric drive applications range from utilities and industrial
plants, to naval, land and aerospace propulsion. Such a widespread reliance on the
technology advocates the need for extensive validation of motor drives before their
implementation. Thus, reliability, efficiency, and consistent performance are significant
drive attributes. Conventional validation processes can require elaborate test beds in order
to maintain such characteristics and debug any developmental errors. Aside from needing
both the electric drive and/or motor under test, multiple motor-load combinations could
be needed to test the full range of drive applications. Lower power machines tend to be
more accessible and less expensive; considerable size differences cut down on necessary
prototyping materials. This convenience is not shared as power levels increase through
the kilowatt to megawatt range. Higher energy requirements increase the cost of
operation, noise levels, test bed space requirements, safety precautions, and have fewer
available, qualified testing sites. Furthermore, it is common that the motor and electric
drive manufacturers are not local to one another; and possibly two different companies.
Thus, drive validation expenditures can quickly aggregate as materials, prototyping and
development, operation and testing, and transportation all contribute to the overall cost.
With such high costs associated with conventional motor drive validation, one can see the
room for economic improvement.
The concept presented in this thesis, known as the Virtual Machine (VM),
provides a new approach to electric motor drive testing. It mitigates some of the
associated cost and risk while providing a wider range of testing scenarios by exploiting
Power-Hardware-in-the-Loop (PHIL). PHIL, more thoroughly explained in the next
section, allows the exchange of power between some hardware under test (HUT) and a
virtually simulated system (VSS) through a voltage amplifier and a coupling interface.
The VSS, existing in a digital real-time environment, contains a model of the desired
motor-load combination needed for traditional electric motor drive validation processes.
Then, the PHIL concept is utilized to connect the electric motor drive under test to the

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simulated environment, i.e. the VM. Without the use of PHIL, dynamic VM loading
conditions would have inaccuracies as the changes are not accounted for without
feedback. Ultimately, expensive hardware is taken out of the process and various
motor-load combinations become available for drive validation in a real-time
environment. The VM test bed then consists of the tested drive and the needed
components to implement PHIL: a software signal-to-power level amplifier, real-time
simulator, and a coupling network between the amplifier and drive. Any desired
motor-load dynamic test is then a mathematical model away. No rotating mechanical
components are needed as they are replaced with power electronics. This added benefit
could prevent damage when investigating faulted circumstances, as a real machine’s
inertia prevents safe, instant stalling. Once validated the VM concept could provide
useful insight into the future testing of electric drives and machines at higher power
levels.

1.2 Hardware-in-the-Loop
Before further reviewing related VM works, it is necessary to describe
Hardware-in-the-loop (HIL). HIL, also commonly called HIL simulation, is a procedure
that integrates a piece of hardware equipment under test (HUT) into a larger, virtually
simulated system (VSS) through some coupling interface. Two sensible HIL abstractions
are noted Figure 1-1. Figure 1-1a illustrates a pilot training to fly via a flight simulator.
The pilot acts as the test subject, HUT; while the flight simulator running on the
computer serves as the VSS. Input/output from the computer interfaces the two systems.
Thus, the pilot, HUT, inputs flight commands through the flight desk controller
connected to the computer. In turn, the computer processes these commands in the flight
simulator program, VSS. The second part of the interface, the computer monitor, gives
the HUT feedback of the flight environment. The HUT receives the feedback and adjusts
commands as necessary. This process repeats, creating a loop; i.e. Hardware-in-the-Loop.
Another HIL scenario is illustrated in Figure 1-1b. A musician wishes to test out how a
guitar amplifier/speaker stack sounds with his favorite song and instrument. The
musician’s music composition now acts as the VSS, his ears and guitar as the interface,

2
and the speaker cabinet and amplifier as the HUT. A similar feedback loop is formed as
the sound is assessed.

(a)

(b)
Figure 1-1: HIL examples
(a) flight simulator (b) musician testing guitar amplifier

Applying the HIL concept to electric drive simulations removes the inaccuracies
of model simplification and linearization common to other simulation methods, as one or
more actual devices replace their modeled counterparts. Furthermore, severe
circumstances are analyzed with less risk or cost; precautions can then be taken before
hidden defects cause intolerable system damage. Such a procedure provides higher
fidelity and reliable testing results before the final implementation of the tested devices.
For electrical systems and drives, two broad categories of HIL testing exist depending on
the HUT and the required interface: Controller-hardware-in-the-Loop and an extension of
this concept, Power-hardware-in-the-Loop.

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1.2.1 Controller-Hardware-in-the-Loop
Controller-hardware-in-the-Loop (CHIL) takes the HIL concept and implants a
controller (typically for electric drives), or part of it, as the HUT. It is then tested against
a simulation of the system that it would normally control; the VSS (typically drive
circuitry, machines, loads, etc.). CHIL interfacing is simply a low level digital to analog
converter (DAC), since controller signals exchanged with real hardware are only around
+
/- 5 to15V, 0-150 mA. Rarely are commercial DAC inadequate for interfacing the HUT
and VSS in CHIL simulations. CHIL has various advantages over conventional,
simulation-only controller testing. Primarily, the control algorithm is implemented
directly on the hardware it is designed for use on; thus, truncation error, controller time
delay, and nonlinearities are accounted for. Furthermore, traditional controller testing
procedures have less capability of evaluating the control schemes response to various
system disturbances; such as faults or impulse loads. With CHIL, prospective controller
problems are recognized risk free as protection schemes are more robustly tested, system
performances are optimized via a real controller hardware implementation; all without
testing against the actual hardware system. Figure 1-2 shows the system flow of the
generic CHIL simulation discussed.

Figure 1-2: CHIL system flow diagram - generic example

1.2.2 Power-Hardware-in-the-Loop
Power-hardware-in-the-loop (PHIL) follows the HIL concept with the added
stipulation of power exchange between the tested power components, HUT, and a

4
simulated power system, VSS. Thus, a power interface is more complex then the
controller interface, as a power coupling network is necessary to interface power
exchange. Typically, this network consists of an amplifier (e.g. voltage source converter)
to step up the simulated power systems real-time voltage references to an appreciable
power level as well as components to interface the inverter with the HUT, usually some
inductive filter. Ultimately, the HUT is connected via an amplifier interface to power
hardware that is operated from a real-time simulated, “virtual” grid.
Figure 1-3 shows the three PHIL subsystems, VSS, interface, and HUT; and how
they interact through a voltage drive PHIL example. Here the HUT is a power electronics
drive, specifically a variable speed drive (VSD). Sensory data is taken from the drive and
input into a simulated environment. In order to operate the amplifier as a current sink one
must feedback the opposite signal, i.e. voltage. Furthermore, current source operation
requires current feedback. The simulated power systems response to the sensory input is
then sent as a voltage reference to an interface amplifier. The amplifier, coupled to the
HUT, then appears to the HUT as the simulated system via its terminal characteristics.
Note that the interaction of power flow between the HUT and VSS is denoted by a
bidirectional arrow. Depending on the PHIL application current could flow in either
direction between the HUT and the amplifier.

Figure 1-3: PHIL signal flow diagram - voltage drive example

PHIL testing allows drive systems or divisions of them, like the example in Figure
1-3, to be tested under real power levels prior to the completion of the entire system. This
greatly decreases the turn around time from designing to commissioning and gives

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additional opportunities to identify design flaws, component defects, and test the HUT
response under various transient conditions or in applications it wasn’t originally
designed for.

1.2.3 Interface Filter


A note should be made regarding the “AMP/HUT interface filter” shown in
Figure 1-3. In PHIL systems, the flow of current between the amplifier and some HUT is
obviously important to the validity of experiments. Thus, an interface filter is a well-
known technique for maintaining the currents integrity. Various trade-offs exist when
designing the filter, but the most common, successful topology is the LCL filter [1]
shown in Figure 1-4.

ΔVfilter
Lfilter Vfilter Lsource
Converter/ PCC
HUT
Amplifier ifilter isource
ic Cfilter

Figure 1-4: Amplifier-HUT LCL interface filter

The point of common coupling (PCC) marks the interface between amplifier and
HUT; thus including the filter in the interface structure and making the voltages and
currents at the PCC equal to those referenced in the VSS. Common amplifier topologies
are voltage source converters or some other drive topology requiring switching, thus
current waveforms are subject to harmonic switching ripple. The voltage dropped across
the filter structure is represented via ΔVfilter. The filter capacitance, Cfilter, provides a low
impedance path for such harmonic switching ripple, effectively filtering it out of the
PCC, while the inductance, Lfilter, adds reactance for decoupling the amplifiers switching
effects from the HUT. While also adding decoupling for the HUT, the source inductor,
Lsource, prevents current drawn from the HUT, isource, from unevenly branching through
Lfilter and Cfilter (Kirchoff’s Current Law), possibly deviating the actual current drawn
from the VSS reference. Placing another inductor, Lsource, equivalent to Lfilter on the

6
source side of the filter, prevents such an uneven branch from occurring (i.e. Kirchoff’s
Current Law at Vfilter).

1.3 Literary Review


Improvement in electric drive testing procedures have facilitated in the past few
decades as available computational power has progressed with the advancement of
processors. This allowed more complex and non real-time, or off-line, simulations to
disclose details regarding transients, power quality disturbances, motor characteristics,
etc. [2]. In 1993 the need for real-time validation was emerging, thus the Manitoba
HVDC Research Center in Winnipeg, Canada developed the real time digital simulator
(RTDS) [3],[4]. RTDSTM exploits intercommunication between multiple processors to
partition the computations associated with large electrical systems, controls, and
corresponding simulations. The computational power of massively parallel processors
minimizes the time step per calculation to some tolerable “real-time” time frame.
In [5], Langston et al. detailed the real-time simulation of an integrated power
system for an all-electric destroyer class ship and presented the experiences and details
regarding the development of such a model. Apparent from this paper is the extensive
parallel hardware required for the prototyping of such systems. The nine rack RTDSTM
system shown introduces a large cost prior to any expenditure related to the development
of an electric ship model. Such a large cost overhead minimizes the community of
real-time simulation users and developers. Thus, Lu et al. [6] offered a new low-cost
approach by developing open source real-time software, Virtual test bed real-time
(VTB-RT). Such an approach offers an acceptable simulation resolution as an alternative
to higher cost proprietary real-time solutions. Although this subsidizes the cost of
proprietary software, the price of the hardware necessary to run it is still unavoidable.
Hardware-in-the-Loop (HIL) is a long-standing concept expedient for virtually
prototyping electrical systems, where a piece of hardware equipment is incorporated into
the simulations of larger system. Such exposure between hardware and simulated
environments grants insight to how hardware reacts when implemented in larger systems,
long before they are put into service. Advancements in real-time capabilities, such as
RTDSTM, motivated further evolution in HIL techniques. In [7] three different types of

7
HIL simulations for electric drives are reviewed: Controller-Hardware-in-the-Loop,
Power-Hardware-in-the-Loop, and Mechanical-Hardware-in-the-Loop (MHIL). Then, a
simulation for each of the HIL types are shown for an electric scooter drive traction
system. The electric drive controller board signals were tested in real-time by interfacing
the board to the simulated electric scooter drive: signal level interfacing between the
HUT and VSS is thus categorized as CHIL. Next, a PHIL scenario was proposed and
simulated. The controller board and converter were tested against a simulated electrical
machine and mechanical load, thus power and control signals interfaced the HUT and
VSS. Power signals are attained by additional power electronics serving as an amplifier
to the signal level signals of simulation. MHIL incorporates the controller, converter, and
electric machine while simulating a mechanical load. In this final case, the interface
between HUT and VSS need be capable of mechanically coupling the two. Bouscayrol et
al. [7] provide an exhaustive literature review and a viable overview of the technology,
but only present simulations of PHIL and MHIL systems in lieu of an experimental setup.
CHIL is an older approach to HIL testing than PHIL as controllers more naturally
interface with the signal levels of simulations than power components. Thus, there is a
longer standing knowledgebase regarding CHIL testing than PHIL; a brief overview of
the past decade shows the growth of CHIL. Wu et al. [8] demonstrates the design,
implementation, and testing of a digital controller for an H-bridge inverter. First, the
control logic is developed and verified in non real-time against a simulated system. Next,
the control logic is replaced with an actual hardware controller interfaced to the real-time
simulated test system. Aside from providing a safer, quicker, and more reliable means of
controller testing, such procedures expose the control algorithm to hardware features that
conventional simulations have no access to. [9] exemplifies how CHIL is used to test
such specific controller responses. A variable speed drive controller card’s sensitivity
against power quality deviations was tested via a simulated distribution system of the
U.S. Coast Guard Icebreaker Ship “Healy”. Promising results, exclusive to the CHIL
testing method, showed that the firing board could tolerate highly distorted voltages and
frequency changes, but it was unable to abide certain short-term phase-shifted single-
phase voltage sags, only three-phase voltage sags. CHIL has also been used to design,
prototype, and verify entirely new control algorithms as in [10] and [11]. In [10] a

8
stochastic-based field programmable gate array (FPGA) IM drive algorithm with neural
networks is shown to greatly reduce the required computational resources and reduce
prototyping costs, while [11] shows a new algorithm to detect harmonics due to nonlinear
loads for power quality improvement applications. As CHIL experiments are not the
focus of this thesis, it is important to note the niches they play in HIL testing and PHIL
development.
Ren et al. [12] demonstrates the value of PHIL by using a 50 kW scaled-down
duplicate of a 5 MW PHIL test bed, prior to its implementation, to mitigate any
overlooked risks or design flaws that are difficult to identify. An RTDSTM simulation of a
100 kVA, 0.8 pf gas turbine generator exposed to pulse loads represents a weak power
system. The simulation is connected via an interface amplifier and transformer to power
an induction motor in hardware, loaded via a separate drive. The motor load current is
then fed back into the simulation and injected as a current source. This allows the
simulated gas-turbine to “see” the physical motor via a simulated current source
equivalent to the physical motor’s measured load current. Various pulse, motor loads and
transient conditions were simulated revealing potential pitfalls in the design of such a
PHIL system. Furthermore, the simulation to hardware interface has a testing benchmark
for its future power level. Later in [13], Steurer et al. further applies [12], showing the
first testing of commercial motor drives at the previously alluded 5MW power level. A
very similar system was assessed: a simulated 4-MW gas-turbine generator with pulsed
loading interfaced to a commercial 2.5-MW VSD, separately loaded, through a 5-MW
variable voltage source (VVS) amplifier converter. Through [12] lower power level PHIL
testing defined the potential risks associated with the development of a similar higher
power level PHIL test bed [13]. In [14] the versatility of PHIL is shown by utilizing a test
bed originally built for electric ship propulsion studies, as shown in [12], to perform wind
energy research. This flexibility is crucial as it allows multiple studies, testing, and
configurations to exist in one PHIL test bed. Such a cross-over between studying
propulsion drive dynamics and wind energy studies is possible as the RT-HIL test bed
exhibits all the necessary features for both: a continuous real-time digital simulator, i.e.
RTDSTM, an interface amplifier, two mechanically coupled dynamometer induction
machines, and their power electronic drives.

9
Langston et al. [15] demonstrate how RT-HIL can be utilized to develop a
detailed simulation model of a super conducting fault current limiter (SCFCL) and its
effect on a utility type impedance relay. Simulated is a three phase source behind an
R-L load coupled to a generator through a transmission line. The line contains a SCFCL,
is subject to single-line-to-ground faults at various locations, and has breakers at each end
to isolate any fault. External to the simulation, a hardware impedance relay takes phase
voltage and current measurements and simulated breaker state signals to provide trip and
reclose signals to the simulated breakers; thus, the relay fully interacts with the
simulation. Studies revealed the importance of sensor locations and the versatility of the
SCFCL model for accommodating other superconductive materials as areas of
improvement in the SCFCL model. Promising fault current reduction was shown via such
simulation, [15], prior to actual PHIL SCFCL tests, [16]. In [16] the first PHIL
closed-loop current control approach to testing a 10 m SCFCL segment was shown. The
PHIL interface introduced instabilities possibly requiring greater control schemes to
accommodate, but the limiting behavior of the SCFCL is shown under a variety of
conditions.
Further evidence of PHIL instability and accuracy issues are shown in [17]. The
PHIL software/hardware interfacing method, namely the analog to digital conversion
(ADC) and digital to analog conversion (DAC), caused a time delay creating large error
in the power system studied; in this case the crash-back maneuver of an all electric ship.
Such a time delay degrades the apparent power factor as the ships bus sees current
lagging voltage. A four-stage systematic approach involving:
(1) pure simulation
(2) PHIL simulation
(3) CHIL experimentation; used to assess the error
(4) a final PHIL test case
The CHIL test revealed the latency issue of ADC/DAC, thus a time delay compensation
method was needed to improve the issue. A Fast Fourier Transform (FFT) was used to
decompose the signal up to the 13th harmonic, the desired phase shift was then added to
each harmonic, the signal was reconstructed from the FFT to compensate the current
feedback, and was then added into step-4 the PHIL test.

10
Various interface models, approximations, and hardware topologies have been
utilized to accommodate the inaccuracies of PHIL studies [18]-[21]. In early studies [18]
simple first-order systems were tested, determining that the PHIL interface does not
significantly affect system behavior. Although Ren, [17], shows under more complex
non-linear systems (e.g. electric ships), PHIL interfaces could greatly alter dynamics.
Wu et al. [18] introduces three PHIL interfaces: an ideal transformer interface (ITM),
time variant first order system (TFA), and a transformer line model (TLM). Each
interface is analyzed as they couple a voltage source behind impedance to DC-DC
converter fed DC motor. Converter input current and reference voltage are compared
against a co-simulation of the same system via the multi-agent platform performing data
acquisition. Results showed ITM exhibited the closest match with the simulation, but
more accurate verification is necessary to fully understand the interfacing tradeoffs. Two
additional interface algorithms, partial circuit duplication (PCD) and the damping
impedance method (DIM), are shown in [19]. The TFA interface algorithm from
[18]-[19] was first developed via [20] to compensate for delays via approximating the
dynamics of the HUT with time variant first order systems. It is also noted here that the
hardware side of the interface, the signal amplifier, need to absorb and deliver power,
thus a four-quadrant converter is a popular choice. Recently, in [21] a synchronous
generator indirectly controlled by the VSS acts as the interface amplifier; its terminal
currents are injected into the simulation via current sources. Roscoe et al. [21] observed a
few disadvantages of a synchronous generator hardware interface: neither harmonics nor
phase imbalance could be reproduced and limitations exist when tracking specific voltage
and frequency rate of changes demanded from simulation. Yet, brief hardware faults were
repeated successfully.
Structured methods for analyzing the performance of the emerging interface
algorithms are shown in [1],[20],[22]. Wu et al. exposed the drawbacks of conventional
performance evaluation methods applied the PHIL interfaces [22] and introduces a new
tactic in [23]. The interface algorithms are tested by decoupling both an inductive-
resistive (RL) and capacitive first order system. Steady state error, response under load
changes and sensitivity to system conditions are assessed via relative error from
simulation and the visual inspection of waveforms. Results imply that PHIL systems

11
retain stability under undesired transients or have conflicting results with the original
system, thus a better performance standard is needed. In [23] Wu introduces a technique
based on wavelet theory and frequency response analysis, allowing the local analysis of
non-stationary, transient signals to better track the behavior of the actual system under
different operation frequencies. TFA yielded the closest results to the actual system. Ren
et al. [19] proposes estimating the accuracy by evaluating the transfer function of the
system response with respect to interface disturbances. Various PHIL simulations and
validating experiments were conducted concluding that none of the interfaces are ideal,
but certain algorithms provide higher stabilities and accuracies. Later, Ren provides a
novel, analytical method for determining HIL software interface inaccuracies. Interface
perturbation is categorized into two categories, interface transfer function perturbation
and noise perturbation, and given a definitive function [24]. Then an error function, only
requiring the open-loop system transfer function and interface perturbation function, is
derived to assess accuracy. Such a technique is shown valid for both linear and non-linear
systems. Most recently, Lentijo et al. [1] compares and contrasts two hardware coupling
interfaces via simulation and analysis: a link-inductor and LCL filter. Through four
figures of merit the LCL filter provides the best coupling solution:
 frequency response
 infinity norm of error
 over one period
 total harmonic distortion (THD) and harmonic analysis
Only by adding complexity to the inverter controls under closed-loop experiments does
the LCL filter provide a disadvantage, as it is not a first order system.
Finally, the use of PHIL coupling interfaces to provide virtual load emulation to
the HUT should be discussed; this is most important as the VM concept is based on this
principle. The earliest roots of the real time PHIL load emulation is seen in 1998 [25].
The design goal was to test motor drives by emulating the behavior of a loaded electric
motor through a power electronic interface parallel coupled with the HUT. A low power,
4 kW, induction motor drive was connected via a power electronic amplifier and series
link inductors to a real-time model of an induction machine loaded with various torque
profiles. A design tradeoff was noted for the coupling link inductors as smaller values

12
provided faster current control and transient response, but higher values more effectively
decoupled the 12 kHz switching of the HUT. System stability was shown as the virtual
motor sent steady state references to the amplifier. Next a speed reversal case, from
-50 Hz to 50 Hz, showed that during such transients reverse power flow is possible
causing the DC link voltage of the HUT to rise. Therefore, an actively controlled front
end (AFE) is necessary to safely regenerate power back to the main supply. Slater et al.
[25] provided insight regarding the PHIL testing of motor drives, but the power level
shown was relatively small for commercial motor drive testing and the versatility of such
a “universal” test bed was not fully exploited by simulating various machine
characteristics to fully test drives. Furthermore, since 1998, computational capabilities
have greatly increased and improved PHIL interfaces emerged.
Power flow between parallel-connected, LCL filter coupled, three-phase
converters was analyzed in [26] as Borup et al. proposed nonlinear load sharing methods.
Although many strategies are possible for drawing and tracking PHIL current references
into a VSS, the power flow analysis noted here defined a basic relationship between
parallel coupled converters governing real and reactive power flow. Results showed that
active power flow was primarily controlled by altering the excitation voltage angle
difference between the two converters, while reactive power flow was dictated via
variation in voltage amplitudes. Such methods and analysis can be critical for PHIL
virtual load emulation test beds (such as the proposed VM design) to control power flow
between the VSS controlled amplifier and the HUT.
Monti et al. presents another PHIL load emulation platform [27]; three current
control algorithms to determine the necessary applied filter voltage to draw current to
closely tracking the PHIL references [28]; and recommends improvements based on the
approach used and experiences with the test bed [29]. In [27] Monti expands on Slater’s
concept [25] by proposing feedback of the simulated machine rotor position to the HUT,
thus giving a higher granularity when testing motor drives. Interface input/output (I/O)
challenges were overcome with the addition of a custom frequency bandwidth mismatch
algorithm in a field programmable gate array. Furthermore, an LCL coupling filter was
used in lieu of an inductive link. Results were shown for two transient IM conditions:
across the line starting and a V/Hz ramp. Next, Monti et al. propose three current control

13
algorithms: trapezoidal approximation (bilinear), exact calculation of the exponential
matrix, and backwards difference [28], with the latter providing the most stability under
varying filter parameters. A practical application is then applied to the PHIL load
emulation test by “stating” that various machine loads could represent elevator loading
dynamics; thus, an elevator drive is the motor drive under test. While the HUT was
“based” on a 20 kVA rating, results only showed 5A peak to peak transient current with
little to no explanation on voltage amplitude applied. Four design improvements to the
PHIL platform noted in [29] are:
 A new method of obtaining input voltages as a substitute for recreating
voltages from PWM signals; removing unnecessary control dependence.
 Filter or replace noisy voltages negatively affecting the control algorithm.
 A more interactive user interface with the model during PHIL simulations
 Replace the PHIL signal amplifier with a more reconfigurable, modular
solution which allows easier scalability of the platform/controls under
different power levels or load emulations.
Another PHIL load emulation interface amplifier solution uses a quasi
linear-inverter, i.e. LinVerter to couple hardware and software signals [30]. Note that
while a LinVerter eliminates harmonics, only creating the desired fundamental, it limits
the platform flexibility from harmonic studies. The parallel bridge structure of this
topology creates sharing of load current in each of the bridge arm inductors. Such sharing
creates a cause and effect relationship: reducing the current in each of the phase legs,
creating additional voltage drops, and increasing the inductors sizing and switching
frequency. Experimentally, PHIL load emulation drive testing was limited to specific
speed/load profiles since the prototyped LinVerter amplifier was underrated for the
drive/machine test bed. The most recent PHIL load emulation is shown in [31]. A
415 VLL, 30 A motor drive is coupled to a virtual simulated machine through a converter
amplifier and LCL filter interface. It is then driven up to rated speed via free acceleration
and subsequently loaded at 80 percent rated torque. Results show loaded current draw up
to 7 A. The HUT operates much like a grid connected system, i.e. with no encoder/speed
feedback for closed-loop control. Next, the induction machine emulated load is replaced
by an unbalanced load and later by a nonlinear active load. Current drawn through the

14
PHIL interface accurately tracks the reference for each case. A flux modulator PHIL
current control strategy is overviewed before the using the newly proposed “optimal
feedback controller” based on a linear quadratic regulator.
Finally, [32]-[34] represents the author’s progression of work towards a 25 kVA
PHIL load emulation test bed, known as the “Virtual Machine”. Although the VM
concept presented in this thesis is based on PHIL load emulation previously reviewed, the
various differences and approaches taken from the previously published systems pose
new challenges, opportunities to uncover new knowledge, and potential improvements to
the aforementioned PHIL works. The details of [32]-[34] will be discussed in following
sections of the thesis.

1.4 VM Concept
Before unveiling more details concerning the virtual machine concept, it is
instructive to briefly describe how typical three-phase alternating current (AC) electric
machines are operated. Electric motor drives, e.g. variable frequency drives, apply
three-phase voltages to the terminals of a machine to excite it (typically the stator field
windings, if singly-fed), in turn creating a magnetic field. Depending on the type of
electromagnetic machine (induction, permanent magnet, etc.) this magnetic field interacts
with a rotational component, the rotor, ultimately inducing an electromagnetic force,
moving it. Under closed-loop control, torque and speed sensors may provide feedback to
the drive’s controller. Such controllers then modify the applied voltage of the drive in
order to control the desired aspect of the machine: speed, torque, current, etc. Without
such information the drive would have no knowledge of the machines state, blindly
applying voltage as the machine responds; such controls are called open-loop. Specific
control strategies will be covered in later chapters. Figure 1-5 depicts typical electric
machine operation via a variable frequency drive, abstracting the drives controller and
leaving out any counter torque load applied to the machine for simplicity. These loads are
commonly machines mechanically coupled to the shaft of the controlled machine and are
operated in the similar manner via some loading drive.

15
Figure 1-5: Generic electric machine operation

Such a configuration is essential in applications requiring physical machines, but


what if one just wanted to test the motor drive? Although drive control strategies vary
between machines, most motor drive topologies are not machine dependent. Instead,
drives are specified via their power rating; implying that one drive could control multiple
types of properly rated machines. If so, then according to Figure 1-5 drive testing would
become costly to test the full range of motor-load combinations. Furthermore, faults in
the drive or the controller would be subject to directly damaging expensive hardware, as
a real machine’s inertia prevents safe, instant stalling. Exploiting the PHIL concept, an
interface amplifier could be connected to a drive under test and electrically represent a
wide range of motor-load combinations, removing such cost and risk. The VM concept
prevents such mechanical issues since a power electronics amplifier replaces any rotating
mechanical components.
Consider Figure 1-6, here an open-loop VSD PHIL load emulation test scenario is
shown demonstrating the VM concept. The HUT is a VSD electrically coupled through
an LCL type filter to an interface amplifier representing various high fidelity machine
models with detailed load dynamics. The combination of amplifier, filter, and load model
should present the same dynamics of the load itself, i.e. a unity transfer function. The
amplifier voltage is controlled such that it is a current sink/source at the PCC for the
VSD, matching actual current flow with the machine model running in the VSS, a digital
real-time environment. The terminal characteristics of a real machine-load combination
are then closely represented via the amplifier to the VSD, given that the voltage interface
amplifier has enough bandwidth.

16
Figure 1-6: VM Concept: Open-loop VSD PHIL test scenario

1.4.1 Achieving Power Flow


The bidirectional arrow drawn between the HUT and interface filter in Figure 1-6
shows that power may be exchanged either way during different machine operation
(generator or motor). To better investigate the power exchange between the HUT and
amplifier consider Figure 1-4, with a VSD acting as the HUT. The VSD and voltage
amplifier each apply voltage to their respective side of the filter, effectively coupling to
each other at the PCC. Current is either drawn or sourced from the HUT to the VSD
depending on the phase and/or magnitude differences in these applied voltages. The
vector diagram of Figure 1-7 illustrates the relationship that the amplifiers magnitude and
phase angle play on reactive and active power flow through an LCL filter. Note that the
phasor abstraction shown in Figure 1-7 is only true under ideal filter conditions, i.e. no
resistance. By setting zero phase difference between V PCC and V AMP the effects of
offsetting the two voltage magnitudes may be observed, Figure 1-7a shows both voltages
aligned electrically. Through observation, by modifying the applied amplifier voltage,
│V AMP│, while maintaining a constant voltage from the HUT, │ V PCC│, the voltage drop
across the filter impedance is varied. The current drawn, I filter, through a primarily
inductive impedance lags the voltage, Δ V filter, by 90° electrically; inducing only reactive
power flow. The magnitude of the filter current │ I filter│may then be controlled through
the right triangle relationship formed via the orthogonal axis and the resulting hypotenuse
(1.1). Using the amplifiers applied voltage magnitude as a control variable; one can see
how reactive power flow may be controlled through LCL coupled converters.

17
V PCC  V AMP  V filter (1.1)

¯IĪFilter
¯ AMP

V ΔV
¯ Filter= jXeq¯Ifilter

¯ PCC

V
(a)

¯ AMP

V
ΔV
¯ Filter= jXeq¯Ifilter
θAMP
¯ PCC

V ¯IĪFilter
(b)
Figure 1-7: VM PHIL power flow vector diagram
(a) Reactive power flow (b) Active power flow

Next, the phase difference between V AMP and V PCC effect on current flow is
noted in Figure 1-7b. Considering the angle at the PCC, θPCC, to be a zero degree
reference point, θAMP then represents both the amplifiers voltage phase angle and the
difference in angles between the amplifier and PCC. Once again │ V PCC│ is held constant
and at 0° electrical while θAMP is changed. The filter voltage drop, Δ V filter, is now
orthogonal to VPCC; aligning the phase of I filter with that of VPCC, creating active power
flow. A similar argument can then be made to use θAMP as a control variable for active
power flow. Figure 1-7 shows current flow in only one direction. If Δ V filter is of opposite
polarity the resulting current would also reverse direction; reinforcing the need for both
drives to have control schemes accommodating reverse power flow. Finally, when there
is no phase shift or magnitude difference between the two voltages applied to the filter,
VPCC and VAMP are said to be synchronized and no current flows.
This concept of independently controlling active and reactive power flow through
LCL coupled converters is important ensure to that the PHIL interface properly mimics
the references sent via the VM and safely excites the PHIL experiment. Independent
access to active/reactive PHIL current flow is obtained by applying the Park
transformation to the resulting currents of the simulated machine, and then utilizing the

18
power flow theory for parallel LCL coupled converters previously discussed; i.e. the
phase and magnitude relationship of applied voltages. These references are then linearly
scaled via the systems impedance (Ohm’s Law), to provide the voltage references to the
amplifier’s controller. A single phase, script based, equivalent circuit model of the actual
network coupling the parallel coupled converters provides proof of the aforementioned
concept, but is left to Section 3.4.2 in order to first provide adequate detail of the VM
PHIL test bed.

1.4.2 Thesis Statement


Conventionally, an inductive filter interface isolates the HUT from the interface
amplifier, providing impedance for current draw. LCL filters are usually the optimal
topology for such PHIL applications, but do not suffice when coupling parallel converters
of different voltage levels. In such applications, a transformer must be used to provide the
necessary step in voltage; introducing various degrees of non-linearity into the PHIL
interface. Specifically, the VSD under test in this work supplies an IM rated for 480 VLL,
but the VSS interface voltage amplifier outputs at 208 VLL. A 208/480 V, Δ-Y
transformer is necessary to step the amplifier voltage up to that of the VSD, creating a
30° electrical lagging phase shift between the amplifier and VSD. Furthermore, low
frequencies applied to the transformer could be attenuated, limiting the low VM speed
range. DC current components could cause unwanted harmonics and even saturation.
Likewise, applying voltages much lower than the rated transformer value appears
non-linear and unbalanced, creating fictitious non-linearities for the VM drive. The
transformer is also subject to switching frequencies from both the VSD and voltage
amplifier, thus filters are presented to accommodate the resulting high frequency voltage
ripple. The amplifier then presents the unique problem of subjecting the reproduced VM
terminal characteristics to these switching harmonics. Traditional machine operation has
no exposure to such harmonics introduced when replacing a machine with power
electronics. The amplifier, controlled via VM references modeled in RTDSTM, runs at
best in 2 μs; non-linear constraints such as saturation, slotting effects, or non-sinusoidal
winding distributions would have to be linearized or neglected in order to meet real-time

19
requirements. Natural transient conditions observed in machines (start-up, load torque
steps, etc.) are limited by the amplifiers 5 kHz bandwidth.
The primary objective for the 25 kVA VM implementation at the author’s
research center, The Center for Advanced Power Systems (CAPS), is to assess the
non-linearities associated with the non-conventional transformer-based LCL PHIL filter
used to couple the parallel connected converters. Furthermore, any additional limitations
and drawbacks upon developing and implementing the 25 kVA VM should be noted and
evaluated. Once the issues related to such a transformer coupled system and VM
development and operation are assessed, CAPS intends to facilitate the VM concept on a
5 MW test bed which mirrors the proposed 25 kVA test bed. Thus, allowing potential
pitfalls and concerns to be addressed prior to increasing the power level and risk.
In this thesis, a phasor-based PHIL approach to a virtual machine is introduced
that mimics the behavior of an available 15 hp induction machine energized via an
18.5 kW VSD through a transformer coupled 25 kVA amplifier. The development and
implementation of such a system is described alongside many of the system limitations.
The concept of controlling steady state power flow between parallel coupled converters
will be experimentally proven and utilized in the development of a simplified current
control strategy for the PHIL VM test bed. Controls governing the PHIL voltage
amplifier will use a phase locked loop (PLL) to properly synchronize the excitation angle
between the VSD and the amplifier. Then, a mathematical relationship between the field
oriented coordinates at the PCC in the synchronous rotating reference frame and an
active/reactive power flow algorithm will be used to control the interface voltage
amplifier such that the desired machine current references are drawn at the PCC.
Specifically active power flow is governed by the voltage phase shift between the
paralleled converters output and mapped to the d-axis coordinate plane. Likewise, the
reactive power flow is controlled via the magnitude difference between converters and
mathematically related to the q-axis synchronously rotating with the PCC.
Reverse power flow into the VSD is compensated via actively controlling the
front end rectifier via a vector-based grid synchronization algorithm modulated through
hysteresis current control (HCC). The AC side of the VSD, the inverter, is controlled via
open-loop V/Hz references and space vector modulation. Results are validated against

20
both a PHIL simulation of the test bed and the real VSD driven IM, serving as the
template for the modeled VM. The proposed PHIL test bed provides not only unique
challenges when coupling the interface voltage amplifier to the HUT, but also a
simplified phasor-based current control solution for directly managing active and reactive
power flow; and a higher power level than any previous VM demonstrations.
The rest of the manuscript is organized throughout four chapters. Chapter 1 has
provided the motivation for, a basic understanding of the necessary concepts within, a
literature review of, and an explanation of the VM concept presented in this thesis.
Chapter 2 then describes the system used to implement the 25 kVA VM and then
highlights the hardware modifications necessary to reconfigure an existing system in
order to accommodate to proposed concept. Note here a substantial power level increase
from any similar PHIL machine-load emulation experiments. Next, Chapter 3 further
explains how the equipment is utilized to carry out the VM implementation; specifically
discussing in detail, the controls necessary to operate the HUT and amplifier for PHIL
current control. A simulation is then used to validate the VM concept on the proposed
system and assists in experimentally developing it. Chapter 4 then presents
developmental as well as final VM implementation results. Experimental results are then
taken as the same VSD that was used to excite the VM separately energizes a real IM
under the same controls. Consistency between simulation, VM, and IM results validate
the VM concept. After validation, the limitations of the presented design and an outline
toward future work are presented. The conclusion shows that the phasor-based VM
design operates effectively during steady state conditions and has been shown to track
references during transient start-up and loading. Such a technique could provide useful
insight into the future testing of electric drives and machines at higher power levels.
Finally, the equipment specifications; a helpful mathematical relationship known as
reference frame theory; necessary machine models for simulating the IM and creating
VM current references; and the modulation strategies used to operate the power
electronic converters switches are detailed in subsequent appendices.

21
CHAPTER 2
SYSTEM DESCRIPTION AND MODIFICATIONS
2.1 System Description
A versatile, hybrid PHIL IM drive test bed is utilized in order to prototype the
proposed VM concept. For conventional IM operation, a Danfoss 18.5 kW VSD
containing a diode rectified front end and fully controlled two-level, six pulse inverter
back-end energizes a 15 hp Reliance Electric IM. The IM that acts as a dynamometer
coupled to a 15 hp Reliance Electric DC motor separately controlled from a Reliance
Electric Flexpack3000 DC motor drive. The DC drive load reference and AC drive
switch logic are controlled through dSPACETM rapid control systems prototyping
software and a custom interface card from Alborg University. The interface card
bypasses factory control algorithms giving direct access to gate drive firing pulses for
custom control implementation. This test bed, funded by a Defense University Research
Instrumentation Program (DURIP) Grant, is used for developing new VSD control
strategies, investigating various loading impacts, CHIL experimentation, etc. Note that
the test bed contains additional equipment non-related to this thesis: a variable voltage
source (VVS) for varying the AC grid input into the VSD; a 15 hp permanent magnet
synchronous machine (PMSM) loaded via another DC machine load with drive; and
identical Danfoss VSD drives with Alborg cards. For the scope of this thesis, the IM and
VSD will provide benchmark results for the piecewise development and validation of the
VM. For a detailed characterization of the DURIP funded test bed refer to [35],[36],[37]
as well as APPENDIX A.
A modification to the proposed DURIP funded test bed was necessary to add a
fully controlled front end in lieu of a passive diode rectifier. Another alteration allows the
IM VSD to switch between supplying an IM to a line coupling it with the PHIL voltage
amplifier. When supplying the PHIL voltage amplifier a Δ-Y transformer is used to step
the VSD line voltage down from 480V to the amplifiers 208V rated line voltage.
Furthermore, a sine filter is needed between the output of the VSD and the transformers
Y-secondary (480V) winding to mitigate a high frequency voltage ripple caused by
switching transients of the inverters insulated-gate bipolar transistors (IGBT). Such a

22
filter not only prevents the transformer from seeing the high frequency noise but further
decouples the VSD from the PHIL system. The interface voltage amplifier is essentially a
25 kVA AC/DC/AC converter. The functionality of the amplifier is to increase signal
level voltage commands (from RTDSTM) to actual power levels, interfacing PHIL
experiments. Similar to the VSD, the voltage amplifier also contains harmonic output
voltage filters. These filters in conjunction with the transformer serve as the LCL filter
structure coupling the two converters, although more complex than a conventional LCL
filter due to the transformer. When the VSD output is switched from energizing the IM to
the PHIL interface amplifier, VSD measurements are fed into the VM RTDSTM
simulation to excite the modeled machine, creating a current reference. In turn a control
algorithm will compute the voltage reference for the amplifiers inverter such that the
modeled machine currents under load equals the currents drawn into the amplifier. To
command the desired amplifier voltage RTDSTM then sends the voltage reference to the
two dedicated ABB controllers separately controlling the active rectifier front end and
inverter of the amplifier.
The VSD measurements into to the VSS, modeled machine current response,
reference calculation, and interface amplifier drawing the current command constitute a
feedback loop forming the PHIL experiment. Figure 2-1 depicts the test bed under both
VSD switch conditions: real IM control and VM control. Note that although the amplifier
and the VSD (AFE and inverter) are controlled via two separate controllers, yet only one
is shown here for simplicity. Measurements are shown as thin blue arrows into either
dSPACETM or RTDSTM (VSS) and switch controls are denoted by similar outgoing
arrows to the converters.

23
208Vll
Grid
AFE INV
Voltage Amplifier

AMP Output Filter

Virtual 480/208
VM
Load Transformer
VSS - VM

480Vll
IM/VM DC
Grid VSD Output DC
Switch IM Drive
AFE INV Sine Filter Machine
HUT – VSD
Physical Setup – IM/DC Load

Figure 2-1: VM test bed flow chart

2.2 Test Bed Modifications


The following section details the necessary modifications to the existing test beds
(both amplifier and VSD) in order to accomplish the VM concept. Note that hardware
configurations that remained the same, but are still necessary to detail the system have a
detailed specification listed in APPENDIX A. These include the induction and DC
machines used in validating the VM, and the 45 kVA transformer and the 25 kVA
voltage amplifier specifications. Note that the 45 kVA transformer, while crucial to the
impact of this work, was formerly integrated into the amplifier test bed for a separate
project. Thus, simply implementing a contactor to switch the transformer between the
VM test bed and the existing one is not considered a major hardware modification to the
existing test bed. Likewise, the addition of a switch allowing the VSD to supply either the
transformer for the VM application or the IM for traditional machine operation is not
considered a substantial enough alteration to detail in the following sections.

24
2.2.1 Motor Drives
The motor test bed drive components utilized in the VM test bed consist of a DC
Drive for load control and two AC motor drives together acting as an AC/DC/AC
converter. The Reliance Electric Flexpack 3000 DC Drive is used to regulate torque
commands to the DC load. Although the DC drive controller still manages modulation
and firing pulses for the drive, factory controller references are bypassed for those sent
via dSPACETM control. Specific DC drive control strategies and modulation techniques
are not the focus of this work and are left to the level abstraction from the manufacturer.
The interested reader can investigate [38],[39] for such control strategies. The DC drive
is rated for up to 500 V, 25 A, but only 2.47 A at 300 V is used when exciting the field as
shown in Table 5 in APPENDIX A.
Regarding the AC drives, the AC grid feed was previously passed through a
passive, uncontrolled diode rectifier in order to create a DC voltage. In turn the rectified
DC voltage supplied a DC/AC converter, actively controller for machine operation. Such
a setup is sufficient for IM motor operation as current was only flowing one direction,
into the IM. The VM concept uses a power electronics converter in place of the IM, thus
under ideal “motoring” conditions the current direction follows that of the real setup. VM
developmental faults or IM “hard” startup conditions could incite reverse power flow. An
across the line IM startup condition will be used for both VM and actual IM test scenarios
in order to evaluate the transient robustness of the VM control strategy, thus actively
controlling the AC/DC converter will provide the drive protection under reverse power
flow. Specifically, controlling the DC-link voltage at a constant value prevents any
current flow back into the converter from charging the capacitor coupling the AC/DC and
DC/AC converters. This is undesirable as the DC-voltage is used to couple to DC/AC
inverter, any transient DC fluctuations could adversely affect the functionality of this
back-end. Furthermore, uncontrolled reverse power flow could charge the capacitor past
rated level, possibly damaging equipment. With proper switch controls the AC/DC
converter is grid synchronized and can push excess energy back onto the 480 V
Tallahassee grid, effectively making the VSD a sink or a source.
When reconfiguring the VSD AC drives, one of the 18.5 kW, 25 hp,
Danfoss VLT 5022 VSD now acts as an AC/DC converter taking 3-θ AC 480VLL grid

25
voltage and regulates a stiff, commanded 680 VDC across a capacitor. The internal diode
rectifier, previously used, is bypassed and the drive is reverse connected such that the
output is a DC voltage; i.e. an AC/DC converter. A 1.2 mH line reactor existing between
the AC grid feed and the AC/DC converter was increased to 2.4 mH in order to provide
enough reactance to contribute a sinusoidal, filtered path for controlled current to flow
while decreasing the total harmonic distortion (THD). With only 1.2 mH of line reactance
the grid side current was not maintained at or below a safe rating for the drive, thus
inciting the need for a higher grid-side line reactance. Controlling a stiff DC-bus voltage
removes the AFE’s mathematical complexity from the VSD model, as the AFE may be
represented as a stiff DC source (assuming switching losses and transients are not of
concern).
Another identical Danfoss drive fed from this DC-link capacitor completes the
back-to-back AC/DC/AC converter topology of the VSD. This DC/AC drive inverts the
DC voltage across the capacitor to a controlled 3-phase output AC voltage for exciting
the IM. Previously, the VSD test bed only included inverter control. Once again the
drive’s internal diode rectifier is bypassed for direct DC voltage input via the AFE.
Specific VSD control strategies are discussed in Chapter 3. Each drive has a standard
two-level, six pulse, three-phase converter topology rated to 37.5 A and a DC-link
capacitor, see Figure 2-2; other technical information can be found via [40],[41]. Figure
2-3 shows the actual cabinet housing the three drives, sensors, fuses, contactors, filters,
power supplies, fans, etc.

idc
+

Vdc
+ + +
Vag Vbg Vbg
- - - -

da ias db ibs dc ibs


Figure 2-2: Standard two-level, six pulse converter topology
control pulses, dabc

26
Two Danfoss VLT
5022 AC Drives

2.4 mH
grid-side line Reliance Flexpack 3000
reactor DC Drive

Figure 2-3: Open cabinet view of VSD and DC drive

2.2.2 Output Sine Filter


As previously indicated, the VSD inverter output voltage is dominated by high
frequency ripple due to IGBT switching transients. Such high frequency noise is a
non-issue when energizing an IM, as the field windings provide enough inductance to
filter out the high frequency noise. Once the VSD is switched from sourcing the IM test
bed over to the PHIL VM test bed as the HUT, the noise becomes problematic. As shown
in Figure 2-6, the transformer windings do not provide sufficient inductance to filter the
VSD ripple voltages. The high frequency noise compromises the PLL synchronization of
the voltage amplifier with the VSD output voltages. Thus, additional filtering is required
between the HUT and step-down transformer. In [32],[33] the author introduces the
design of such a low pass filter. The filter, shown in the system diagram of Figure 2-4,
consists of a line reactor between the VSD and transformer branching to a series resistor
and capacitor, wye-connected between phases. Note that the filter is present in every
experiment the VSD is used, not just those involving the transformer; thus, when the
VSD excites the IM the filter impedance is incorporated into the results for consistent

27
validation. The inverter switching frequency is set at 4 kHz, therefore the components
were chosen such that the resonant frequency of the filter was far enough away not to
introduce error. Below (2.1) shows the 1.5 kHz cutoff, or resonant, frequency calculation.
The impact of the proposed filter on the primary and secondary transformer windings and
the PWM signal out of the VSD is seen through Figure 2-7. Finally, Figure 2-8 shows the
low pass sine filter with only 1 Ω of resistance. Although it does not play a role in the
resonant frequency calculation (2.1), the resistance dominates the damping factor, ζ, or
ratio of attenuation to the resonance frequency (2.2). Thus, comparing Figure 2-7 and
Figure 2-8 one can easily see the effect of a damping resistor.

1.2 mH

480/208
HUT-VSD Transformer
2Ω
10 uF

Figure 2-4: System implementation of VSD output voltage ripple filter

1.2 mH
10 uF

2Ω

Figure 2-5: Experimental implementation of VSD output voltage ripple filter

1 1
f res    1453Hz (2.1)
2 LC 2 1.2 *10 *10 9 )

R C
  (2.2)
2 L

28
Figure 2-6: VSD connected to transformer without ripple filter
(CH1: 480V wye-secondary high side transformer winding – 200 V/div;
CH2: 208V Δ-primary low side transformer winding – 200 V/div;
CH4: VSD PWM signal out, DC to V line out - 200 V/div)

Figure 2-7: VSD connected to transformer with ripple filter, R=2Ω


(CH1: 480V wye-secondary high side transformer winding - 50V/div;
CH2: 208V Δ-primary low side transformer winding - 20V/div;
CH4: VSD PWM signal out, DC to V line out - 200 V/div)

29
Figure 2-8: VSD connected to transformer with ripple filter, R=1Ω
(CH1: 480V wye-secondary high side transformer winding - 20V/div;
CH2: 208V Δ-primary low side transformer winding - 20V/div;
CH4: VSD PWM signal out, DC to V line out - 200 V/div)

2.2.3 dSPACETM Control System


Digital Signal Processing and Control EngineeringTM (dSPACETM) provides a PC
development environment for the real-time interfacing of drive control algorithms
existing in MATLAB to the various FPGA/DSP (digital signal processing) boards needed
for hardware I/O commands. An extensive dSPACETM interface is used consisting of:
two DS 5101 PWM cards, three DS 4003 Digital I/O card, a DS 3002 Incremental
Encoder Interface Board, a DS 2002 Multi-Channel A/D Board, a DS 2103
Multi-Channel D/A Board, a DS 814 Host-PC Ethernet connection card, and a DS 1005
PPC processor board. All connection details are shown in [37]. MATLAB/Simulink is
used to rapidly prototype new control strategies before compiling and loading the model
into the dSPACETM control desktop user interface. Here the user has real-time access to
variables linked from Simulink while the model runs on the associated hardware
processors. The dSPACETM I/O cards are optically connected to a VLT5000 V1.0
Aalborg Interface Control and Protection Card, allowing external control signals to
operate the IGBT gate drivers. For VSD operation, dSPACETM takes system feedback

30
from various sensors, gives torque references to the DC drive, processes the AFE and
inverter control strategies and then, depending on the modulation strategy, either directly
modulates or sends the desired references to their respective FPGA cards for modulation.
Recall that initial VSD design was exclusively for the purpose of motor control
via actively controlling the inverter back-end to vary voltage and frequency applied to the
motor; the DC voltage applied to the inverter was attained through a diode rectifier
circuit, i.e. no active IGBT switch logic. The Aalborg card allows one of the two
available Danfoss drives to be connected grid-side as an AC/DC converter, ultimately
being reconfigured such that the six IGBTs are controlled for grid synchronization in lieu
of motor control, i.e. an AFE. This is critical as the factory drive does not have gate level
access to the IGBTs, only an outer level front panel controller for motor speed and torque
references. Note that the Danfoss drive being used as an inverter also has an Aalborg card
bypassing its controller; previous works have reconfigured the inverter hardware via this
card for the purpose of developing more advanced VSD motor control algorithms [42].
All of the necessary controller and signal connections that allow dSPACETM to
control the AFE IGBTs were necessary. Primarily this involved an addition of an Aalborg
controller card onto the AFE for gate access to IGBTs and multiple British naval
connector (BNC) cables to interface to dSPACETM. Further modifications involved
reconfiguring the dSPACETM DAC breakout for additional AFE IGBT output pulses
ultimately rebuilding the existing setup.

2.2.4 Real-Time Digital Simulator


A brief note should be made regarding the real-time digital simulator, as it is
crucial to the 25 kVA amplifier’s operation. Real-Time Digital SystemsTM offers a
real-time platform for large-scale electromagnetic transient simulations. Designed for
various PHIL and CHIL experiments at CAPS, a 14-rack system exists consisting of
multiple paralleled DSPs and analog I/O ports for hardware/simulation interfacing.
Extensive details of CAPS available RTDSTM system and capabilities are shown in [5];
note that since published, five additional racks, various processor upgrades, and multiple
hardware I/O connections have been added. For this thesis, the development
environment, RS-CAD, provides a graphical user interface to model the desired IM, run a

31
phasor-based current control strategy, and send the necessary inverter voltage references
to an interface amplifier. While more connections were not necessary for controlling
additional drives as in the VSD dSPACETM test bed, various BNC cables and I/O cards
were reconfigured in order to read the necessary sensory data into the amplifier control
strategy and output the desired voltage commands to the AC PEC800 controller, see
APPENDIX A.

32
CHAPTER 3

CONTROLS AND SIMULATION


Performance and safety are paramount in systems with substantial power levels;
thus proper system modeling and control validation precede any experimental
implementation. Such a procedure allows for safe experimental development along with a
thorough understanding of the body of knowledge associated with it. The development
and validation of an IM software model necessary to create amplifier references is no
exception. The PHIL system’s validity, response, and similarity between the actual VSD
system controlling an IM rely heavily on the referenced model. Prior to this section it is
recommended that any reader unfamiliar with reference frame theory (RFT) or IM
modeling read 4.5APPENDIX B for the necessary background theory. Specifically,
knowledge of RFT is necessary prior to understanding specific IM models and the AFE
and amplifier control strategies. The transform finds use in electric drive controls and
power system analysis, and as later described, is vital in the final machine model
implementation. Furthermore, APPENDIX B explains a single phase equivalent circuit,
phasor-based IM model as a foundation. Then the shortcomings of such a simplified
model are detailed. Subsequently, a more dynamic, transient three phase differential
equation based solution is presented to account for deficiencies prior to VSS
implementation. Ultimately, the implemented IM model for VM references is presented
at the end of the IM modeling section in APPENDIX B.
The converters from the aforementioned test bed require detailed control
strategies in order to achieve the desired PHIL phasor-based VM solution. Specifically,
the VSD requires the most attention since the Aalborg interface control and protection
card bypasses the built in Danfoss controller, providing lower level access to the gate
signals and overlaying control logic; with no factory controller, these gate level signals
must be constructed. The developed VSD control schemes are presented; bidirectional
AFE operation and inverter IM speed control. The inverter is not modeled using an
averaged mathematical approach [38],[43], but uses either the switching model matching
the topology of Figure 2-2 or a stiff source; therefore further discussion of inverter
modeling is omitted. Three modulation strategies used to control the drive IGBTs are

33
detailed in APPENDIX B: Hysteresis current control (HCC), sine wave pulse width
modulation (SPWM), and space vector modulation (SVM).
Control of the PHIL interface amplifier is higher level than VSD control due to
the implementation of the two separate ABB controllers previously mentioned: the
μT-PEC and AC PEC800. The μT-PEC controls the AFE DC-link voltage without any
user-level interaction, yet the AC PEC800’s control over the inverter voltage requires
voltage references directly sent via RTDSTM to the controller’s SPWM module. These
RTDSTM voltage references control the amplifier such that it draws the same current as
the modeled VM would. Therefore, even though the amplifier control is higher level than
the VSD-HUT, it defines the VM control logic. The necessary control algorithm to
compute voltage references for the AC PEC800 is presented; keynoting on an important
impedance calculation. Next, a single phase equivalent circuit of the coupling network
proves the VM control concept for the presented test bed via a MATLAB script. Finally,
the RSCAD simulation model is shown with unique simulation results prior to the
experimental verification of the VM. Figure 3-1 provides more detail of the system
description than that initially shown in Figure 2-1 as a conceptual flow chart.
Specifically, the control strategies implemented in the following sections are incorporated
as well as actual every hardware component in the test circuit. Note that the actual
components are pictorially shown and are specified in APPENDIX A.

34
Figure 3-1: Detailed VM test bed flow chart

35
3.1 VSD Drive Controls
One of the multiple necessary functionalities IGBTs contribute to power
converters is controlling the amount of power delivered while contributing minimal
power losses. When in saturation mode, essentially being controlled as a switch, the
closed state IGBT allows current flow, but creates a minimal voltage drop across the
device. Furthermore when open, voltage potential across the device exists, yet without
current flow. Properly timed IGBT switch commands generated via modulation strategies
ensure that the exact amount of power necessary is delivered to a load without creating
unwanted power dissipations within it. The modulation strategy, effectively the last layer
of a drive control system, receives a previous control algorithm’s output as its input
command and outputs either pulses or some duty cycle used for IGBT gate control. Input
references, can exist in phase or referred variable from, and range from AC or DC
currents and voltages, duty cycle, frequency and phase, etc., depending on the specific
modulation strategy, drive topology, and control objectives. Control algorithms, whether
open or closed-loop, can consist of multiple layers optimizing various performance
aspects. The VSD within the scope of this work requires two control algorithms for
actively controlling the rectifier and the inverter. The following section reviews the
modulation strategies before discussing the implemented AFE two-loop vector control
strategy, modulated via hysteresis current control and the open-loop V/Hz inverter
control strategy modulated by either sine wave pulse width modulation or space vector
modulation.

3.1.1 Rectifier Controls


As previously mentioned the built-in diode rectifier is not sufficient under reverse
power flow through the VSD [44]. AFE control not only protects the VSD during early
VM developmental stages, but also allows for the VM controlled amplifier to regenerate
back into the VSD. To visualize this reconsider the VM operating as a generator sourcing
current instead of a motor sinking current. During reverse power flow the DC-link
capacitor will likely charge past rated value. Furthermore, grid power exchange seen on
the side of the AC/DC converter will have no regulation. These two failure conditions
define the requirements needed from an intelligent AFE control scheme: maintain a

36
constant voltage command across a DC-capacitor while synchronizing current draw
through the grid-side reactor with the sinusoidal grid voltage, regulating only active
power exchange. Figure 3-2 depicts a control strategy satisfying these requirements. Note
that controls needed for the inverter are outlined in the next section. The closed-loop
control strategy requires feedback of DC-link voltage, line-line voltages, and phase
currents. The phase detection algorithm transforms the abc-line voltages to
α -coordinates, and then uses (B.4) to determine the voltage phase angle, θ. Finally, the
measured line voltages and phase currents are converted to the synchronously rotating
dq-plane via the voltage phase angle.

Figure 3-2: Sinusoidal AFE vector control block diagram

An outer-loop DC voltage controller calculates the error between the measured


DC-link voltage to that referenced (680VDC pre-charge value) passing it into a
proportional integrator (PI) controller. The output of which represents the grid-side active
current reference, Id*, needed to change the capacitor charge to the referenced value. The
reactive power control loop must set the reactive current reference, Iq*, to be zero; any
other value would create reactive power draw, invalidating the second controller design
constraint. The dq-axis current references feed inner-loop current controllers. Once again

37
the error is calculated and input to PI controllers. The inner-loop PI controllers’ outputs
represent the AC-side dq-axis converter voltage references needed. dq-quantities are then
inverse transformed back to phase variables for the HCC modulation strategy with
respect to the synchronous angle derived from the input line voltage. In addition to using
HCC to modulate the AFE, SPWM was also implemented for complementary works;
ultimately needed to reduce noisy measurements in the DC-link and grid-side current. A
series line reactor between the grid source and the active rectifier provides a sinusoidal,
filtered path for current flow. A modification to the VSD AFE line reactor (from 1.2 mH
to 2.4 mH) was needed in order to limit the current flow under both steady state and
transient conditions for both modulation strategies as well as decrease the total harmonic
distortion (THD). For HCC, doubling the inductance lowered the necessary switching
frequency as current decays much slower. Another system constraint is that the
dSPACETM controller used can not compile the necessary time step to modulate a small
hysteresis band; due to the higher frequency switching requirement.

3.1.2 Motor-Side Inverter Controls


The term variable speed motor drive directly pertains to the relationship between
the inverter output and its effect on IM operation. Thus it is no surprise that given a stiff
DC input voltage the inverter is entirely responsible for IM control. A variety of inverter
control strategies exist that optimize various IM performance aspects. By exploiting the
previously discussed mathematical backbone of IM modeling, operation, and even RFT,
desired performance characteristics such as speed, torque, flux, etc. can be directly
regulated via the inverter control algorithm. Depending on controller design, complexity
and cost may increase with performance and controllability, thus motivating the study of
advanced controls. Note that control strategies consist of various layers; only the
calculations necessary control variables for sending the modulator the associated
references are to be considered in this section; e.g. voltages, currents, flux linkages,
angles, frequencies, slip, etc. depending on the strategy. Two IM speed control strategies
are presented: a V/Hz slip controller and a two-loop strategy controlling both speed and
current. An additional SVM control scheme is also implemented that directly takes

38
open-loop voltage references via a dSPACETM slider, but is left out for redundancy. That
the strategies actually implemented are the V/Hz slip controller and the open-loop SVM.
V/Hz control, the simplest IM control, is based on a linear, steady state
relationship between the voltage amplitude, Vs, and frequency, ωe, applied to the IM
terminals and the stator flux linkage, Λs. At high speeds the resistance term in Faraday’s
Law (3.1) is much less than that of the flux linkage thus is excluded; notated via the
strikeout in Equation (3.1). One can easily see that in order for Λs to remain constant
under steady state conditions, preventing magnetic saturation, Vs and ωe must change at
the same rate.
(3.1)
V s  Rs I s   e  s

The mechanical speed of the machine is directly related to the electrical frequency, which
sets the speed of the rotating stator and rotor magnetic fields. Furthermore, the square of
the applied voltage varies with the torque developed. Varying both of these linearly not
only changes the synchronous speed of the IM, but keeps the operating point close to the
newly set synchronous speed. The Torque-speed curve near synchronous speed is abrupt,
allowing minute changes in speed to provide a considerable torque difference. Figure 3-3
reinforces these principles, showing a family of linearly scaled voltage magnitudes to
applied frequencies with respect to their base quantities in a torque-speed curve. Further
derivations and control flow diagrams can be found in [38],[45],[46],[47]; a traditional
closed-loop VSD IM control strategy known as maximum torque per ampere is shown in
[48]. This control scheme is of considerable importance as it is open-loop. For the VM,
controlling the VSD in such a manner eliminates the need for speed feedback into the
VSD control scheme from the machine modeled in the VSS.

39
VB

0.5VB

Te
0.1VB

50 100
Percent of synchronous speed

Figure 3-3: Steady state IM torque-speed relationship for linear V/Hz ratios

Vb
ω*rm +
- PI +
+ b V

ωrm 
Figure 3-4: Closed-loop V/Hz IM slip control

Figure 3-4 shows a closed-loop V/Hz solution by using encoder feedback to


determine slip for the V/Hz calculations. This is used in lieu of pre-calculating an
open-loop V/Hz ratio and sending the references to a modulator. Note that ω*rm
represents the commanded speed reference and ωrm the measured speed. After saturation
and rate limiters the error between the reference and actual current is calculated and sent
into a PI controller. The output represents the motors slip (B.14), without the per unit
base, necessary to regulate the error to zero. The speed measure is then added back and
the sum is (1) directly used as the excitation frequency and (2) multiplied by the ratio of
base voltage to base speed be and used as the excitation phase voltage. Note the other
saturators present in the system are used for both preventing unsafe voltage commands
and for controller stability.
A more elaborate two-loop VSD inverter control scheme is proposed in Figure
3-5 for the sake of future works toward closed-loop VSD control. The two-loop, vector
based control structure closely matches that seen in Figure 3-2. The difference is that the
outer-loop no longer controls Vdc and generates a d-axis current reference, instead it now

40
control regulates a speed command via generating a q-axis current reference. More
specifically, the speed is regulated via computing the error between measured and
commanded speed, then feeds a PI controller. The output of which is a q-axis current
reference used in an inner-loop current controller. Likewise, a d-axis current reference
represents active current control to the load is input from an open-loop slider. The d-axis
current references could be managed from an external control loop regulating id, possibly
for torque or harmonic control, but such a loop is not discussed. The inner current control
loop consists of PI controllers taking in error from both dq-axes currents and outputting
voltage references. Prior to transforming back to phase variables and outsourcing the
voltage references to a modulation scheme, a feed forward decoupling term is
incorporated to remove the influence the dq-axes have on one another; ultimately
incorporating independent control of each. The coupling is a product of mutual
inductances seen in the system.

r
Feedforward
Decoupling
iq

idref 

PI Limiter

id
v dref ref
vabc
i qref dq0 / abc
 rref   
PI Limiter PI Transf .
   vqref
r iq

id
Feedforward
Decoupling

Figure 3-5: Outer-loop speed control, inner-loop current control

3.2 25 kVA Amplifier VM Control Algorithm


As the VSD inverter operates via an open-loop V/Hz controller, the amplifier
control scheme must provide the necessary perturbation (via applied voltage) to recreate
IM current flow. The AC PEC800 controller of the amplifier provides various levels of
control protection alongside modulating the RSCAD voltage references into firing pulses,
via SPWM. Therefore, only the RSCAD control logic to create amplifier voltage

41
references that sink the commanded current is necessary. As described in Chapter 1, the
relationships between paralleled converters’ excitation voltage phase and magnitude are
utilized to recreate the terminal characteristics of an IM on the voltage amplifier.
Specifically, the voltage drop across the impedances coupling the two converters is
controlled to establish the necessary current flow.

Iabc/VM abc
dq Z
Virtual
Load
VM θ+30° ΔVdq
abc dq
- 208
Vabc/VSD dq + abc 480
Vabc_amp_ref
θ θ

PLL +
+

30°

Figure 3-6: Phasor-based amplifier VM control strategy

Figure 3-6 describes the control loop for the 25 kVA voltage amplifier controller
references. The VSD voltages are read into the amplifier control loop and are used to
energize the modeled machine terminals, paralleling actual machine operation, Figure
B-4. A PLL then extracts the phase and frequency of the excitation voltage. Specific
limitations exist in the PLL’s response to drastic changing frequencies, i.e. load changes,
transients, etc. Furthermore, signals with high noise content or perturbations that
temporarily cause aperiodicity contribute to PLL inaccuracy. Initial phase detection and
frequency lock-on takes sufficient time; therefore accurate phase lock is closely
monitored before closing any contactors creating current flow between converters. For
steady state and small changes in excitation frequency the PLL operates with tolerable
response, thus will serve as the phase detection mechanism for the amplifier control
algorithm. This is critical, as the amplifier output voltage must be in phase with the VSD
in order to prevent unwanted current flow between the parallel connected voltage drives.
Synchronization is accomplished by using this angle when transforming the VSD
voltages into the dq-coordinate plane. Likewise, the resulting machine current is
transformed into the dq-coordinate plane synchronously rotating with the excitation
voltage; note that transformers 30° electrical phase shift is taken into account by adding
the necessary offset to the phase angle. The dq-axes current references are then scaled by

42
the impedance of coupling network to represent the necessary voltage drop between
converters to draw the commanded real/reactive current. More detail of the impedance
scaling is given in the follow section. The voltage drop is then added to the applied VSD
dq-coordinate voltages; inverse transformed back to abc-phase voltages, offsetting the
angle once again by 30°; scaled for the transformer voltage step (A.1); and directly sent
to the AC PEC800. It should be noted that q-axis current references draw current 90° out
of phase with the voltage; i.e. controlling reactive power draw. Furthermore, once
converted into a voltage reference via impedance scaling, the q-axis voltage changes the
amplifier’s voltage magnitude with respect to the PCC. Likewise, the d-axis current
references draw current that is in phase with voltage, i.e. active power draw. Once
converted into a voltage reference, the d-axis voltage modifies the amplifier’s output
voltage phase in relation to the VSD excitation voltage at the PCC.

3.2.1 Impedance Scaling References


The current references’ impedance scaling assumes a constant excitation
frequency. This is congruent with open-loop VSD V/Hz in steady state operation,
allowing for a phasor abstraction to simplify a complex non-linear network; ultimately
contributing to the title, “phasor-based virtual machine”. Incorporating frequency variant
impedance gains would place greater reliance on phase detection response and require a
more advanced VSD control scheme, both of which are left as future advancements to the
VM concept. Table 1 provides a summary of frequency independent parameters
influencing the coupling network between the VSD and amplifier. Note that the
transformer reactance is set as a constant, independent of frequency for simplification.

Table 1: Converter coupling network frequency independent parameters


Vb Base phase voltage 277 V
Sb Transformer power rating 45 kVA
Zb Base impedance 1.7067
ZT_pu Per unit transformer impedance 5.18%
XT Transformer reactance 0.0884
n Transformer turns ratio 0.4333
LAMP Amplifier filter inductance 0.6 mH
LVSD VSD sine filter inductance 1.2 mH

43
Transformer manufacturer data is provided via a per unit impedance for the transformer.
By assuming that the transformer reactance is much greater than the resistance and
deriving the base impedance via (3.2), the reactance may be calculated via(3.3).

2
Vb (3.2)
Zb 
Sb

X T  Z b Z T _ pu (3.3)

Further simplification of the network can be made to the by referring the amplifier
to the high voltage (480V), secondary side of the transformer, creating the equivalent
circuit in Figure 3-7. (A.1) defines the primary to secondary winding ratio; the inverse is
required when referring over the low side primary (208 V). Equation (3.4) converts the
amplifier filer inductance to its equivalent reactance while referring it over to the
secondary side, denoted by the prime superscript. Finally, (3.5) assuming no resistive
elements, sums the system reactance into an equivalent impedance, Zeq. Figure 3-7 also
illustrates the principle of the amplifier controlling the voltage drop across the coupling
network, ΔVeq, in order to sink the referenced current from the VSD. Finally Table 2
quantifies the frequency dependent parameters, ultimately yielding equivalent
impedances for the coupling network at 20 Hz, 30 Hz, and 60 Hz. Note that these values
differ slightly from those implemented to account for losses and inductances within the
electrical wiring.

j * 2f * LAMP
X ' AMP  (3.4)
n2

Z eq  X ' AMP  X T  X VSD (3.5)

44
ΔVeq=Zeq*iVSD

iVSD ΔVAMP ΔVT ΔVVSD


+ +
X’AMP XT XVSD
VAMP VLOW VPCC VVSD
- -

Figure 3-7: Equivalent circuit of coupling network

Table 2: Frequency dependent voltage drop calculations


f Excitation frequency 20 Hz 30 Hz 60 Hz
X’AMP Referred amplifier reactance 0.4015 0.6023 1.2046
XVSD VSD sine filter reactance 0.1508 0.2262 0.4524
Zeq Impedance drop 0.6407 0.9169 1.7454

3.2.2 Phasor-based current control: Proof of Concept


To emphasize the VM current draw concept illustrated in Figure 3-7, voltage loop
equations for VAMP, VLOW, VPCC, and VVSD were derived for equivalent the circuit and a
MATLAB script was created to calculate voltage drops across each element. Input into
the script are the VSD excitation frequency and per unit phase voltage magnitude applied,
the per unit value of VSD rated current to be draw into the amplifier, and the phase of the
current with respect to the PCC. In short, user input sets the VSD output and desired
current draw. In turn, the script applies KVL and phasor theory to the circuit, outputting
the magnitudes and angles for the four voltage potentials shown in Figure 3-7; see
APPENDIX C for a derivation. By analyzing the voltage potentials for various active and
reactive current commands, it is shown that for the parallel connected converters used, a
difference in the applied phase angle independently controls the active current, while
magnitude offsets regulate reactive current.
In Table 10 of APPENDIX C results for consistent VSD excitation
(160VLL, 20Hz) are organized into four categories for analysis: strictly real and reactive
power flow, both, and reverse power flow. In summary, active current is requested by
removing the angle offset between current and voltage. In response, the voltage potentials
all have the same magnitude, but varying angles; thus verifying that active current (and

45
ultimately active power draw) is independently controlled via excitation angle. Likewise,
reactive current control via magnitude difference is shown.

3.3 Simulation Model and Results


Simulation environments MATLAB/Simulink and RSCAD were used to provide
unique simulation results prior to experimental verification of the VM. A Simulink model
was developed to investigate if the converters’ switching patterns influenced the
amplifier’s synchronization with the VSD output voltages. After proper evaluation, the
synchronization angle was offset to draw real power to further prove the aforementioned
power flow concept for parallel connected converter under switching patterns. Figure 3-8
illustrates the model; note that electrical components, a switching converter model, and a
transient solver (Dormand-Prince, with a 1 μs time step) were used in lieu of a
mathematical model of the system. Both converters are controlled via SPWM with a DC
source (no AFE). The VSD uses open-loop commands, while the amplifier simply detects
the phase of the VSD and offsets the phase and voltage magnitude as necessary to
synchronize. No modeled IM or other controls were incorporated into this preliminary
stage model.

Figure 3-8: Simulink switching converter test bed model

Figure 3-9 shows the expected current flow under steady state converter
synchronization, at the rated 480 V, 60 Hz. Once synchronized, a small amount of current
flow is expected due to the coupling network being primarily reactive. The waveform
ripple is a result the 4 kHz VSD and 5 kHz amplifier switching frequencies and the LCL-
filter design, while the 1.3 A current flow out of the VSD is primarily a product of the

46
PHIL LCL-interface filter. Finally, notice the transformer’s influence on the amplifier
and VSD measurements; i.e. the 30 ° shift between signals and turns ratio amplitude
difference.

Transformer Currents
4

3A
2
(A)

-2 Ia Amp
Ia VSD 1.3 A
-4
0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065

Transformer Voltages
500
480 VLL
(V)

Va Amp

208 VLL Va VSD

-500
0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065
time (s)

Figure 3-9: Simulated synchronized current flow, 480V 60Hz

Figure 3-10 shows the current-voltage relationship for the amplifier and VSD
(480 V, 60 Hz excitation) once the amplifier’s synchronized voltage phase is offset by 7°
electrical. Notice that current and voltage are exactly aligned, thus no reactive power
flow. Approximately, 8.1 A current draw into the amplifier and 3.5 A out of the VSD and
is shown. The data was extracted with respect to the VSD sourcing; depending on
sensory orientation, the current could be 180° out of phase with the voltage. This still
coincides with real power flow, just in the other direction.

47
Amplifier
10
8.1 A

Vab (V%100)
5

208 VLL
Ias (A)

-5 Ia Amp
Va Amp
-10
0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065

VSD
6

4 480 VLL
V ab (V%100)

0 3.5 A
-2
Ias (A)

Ia VSD
-4 Va VSD

-6
0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065
time (s)

Figure 3-10: Simulated real power flow via phase shift, 480V 60Hz

As the next step, in order to verify the VM control strategy used to send amplifier
voltage references, an RSCAD model was developed. RSCAD, the software package
used to send the amplifier voltage references, provides a true nature test environment for
developing and verifying the VM control algorithm. Thus, modeling the non-linearity of
switching converters is not of primary concern here. Instead, the phasor-based controls
are tested by taking both open-loop and simulated machine (Figure B-4) current draw
references. Figure 3-11 compares the steady state terminal characteristics for the VSD
supplying the IM and the VM under 2 percent torque loading. Given that the DC machine
under loading is only rated to 850 rpm, a safe excitation voltage for the entire system was
chosen, i.e. 160 V 20 Hz (around 600rpm). This provides the VM and IM with equal
operating conditions, adding consistency to analysis. Table 5 shows that higher machine
speeds are attainable, but require field weakening and reduced loading conditions. Graph
annotations point out equal voltage phase and magnitudes, but shows discrepancy in
current phases; the simulated VM current lags simulated IM operation by 15° phase. Note
that when simulating the VSD connecting to the IM, the output voltage sine filter is
included; but additional impedances are exclusive to the VM test scenario. Specifically

48
that of the transformer, amplifier filter, and conducting cable between the two, thus
contributing to the phase shift. The VM simulation was carried out by first synchronizing
the two converters without any current draw references. Once synchronized, the VSD
voltages were used to run the IM to steady state. Finally the current controller was
activated, multiplying the IM current commands by the impedance drop of the coupling
network; thus calculating the necessary amplifier voltage adjustment to draw the current
command. The IM simulation data was straight-forward: using VSD measurements to run
the IM model to steady state, then taking terminal measurements.

160V, 20Hz, 2% torque load

30

f = 20 Hz, Δt = 0.05s
20

Vab = 160 V
10
Vab(V%5)

θdiff = 15°

0
Ias(A)

-10 Ias = 8.8 A

-20 Ias IM
Vab IM
Ias VM
-30
Vab VM

0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17


Time (s)

Figure 3-11: Simulated VM vs IM steady state terminal characteristics


160V 20Hz 2% load

Finally, an across the line VM start-up scenario was simulated for initial transient
studies. After synchronizing the amplifier the current controller was enabled to take
machine references prior to initiating the machine. Therefore, once the modeled IM was
energized, the transient current characteristics were used as controller input allowing the
amplifier to reproduce the start-up transients as the machine ran to steady state. The top
graph of Figure 3-12 shows 50 A peak current draw into the amplifier. Next, the actual

49
a-phase current draw is plotted against the simulated machine current reference. Similar
to the constraint reducing the excitation frequency from 60 Hz to 20 Hz, the machine
references were saturated at 50 A; a safe experimental limit for current flow into the
25 kVA amplifier. Such a graph shows that the phasor control strategy implemented,
(under simulated hardware) could respond to transient start-up conditions. The third
graph shows the machines electromagnetic torque production, τe. Note that under start-up
conditions the torque oscillates between positive and negative values, possibly causing
reverse power flow. Although the AFE of the VSD provides for safe bidirectional power
flow, caution should be taken when experimentally recreating such transient
circumstances. The final plot shows the electrical frequency of the machine as it starts up
and runs to steady state, 125 rad/s for 160 V, 20 Hz excitation.

IaAMP = 50 A
50 IaAMP_SS = 1.72 A
Iabcamp (A )

-50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

50
Iamp vs . IV Mref

0 Iamp
IVMref
-50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.5
 e (p.u.)

-0.5

-1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
150
 e (rad/s)

100

50 ωSS = 125 rad/s


0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (s)

Figure 3-12: Simulated VM start-up transient response, 160V 20Hz

50
CHAPTER 4
EXPERIMENTAL RESULTS
4.1 VM Development, Implementation, and Results
Previously, Section 2.1.3 assessed the VSD output harmonics apparent on the
transformer, which was only excited via the low voltage side (amplifier disconnected);
leading to the development and implementation of the VSD sine filter, Figure 2-6 through
Figure 2-8. This analysis was published alongside results from the VSD energizing the
IM to 200 rpm in [32]-[33]. The mitigated VSD output harmonics and AFE control
implementation (Section 3.3.2) onset experimental verification of the PHIL VM concept.
A gradual approach was taken in order to develop and experimentally validate the
amplifier controls prior to implementation, starting with the synchronization of the
amplifier with the VSD across the transformer. In [34] the synchronization of the two
converters and reactive current flow results via amplifier magnitude scaling was
presented. Figure 4-1 shows successful synchronization (no current draw) of transformer
coupled converters; both of which have different switching frequencies, DC-link and
system voltages. Once synchronized, the current flow between parallel converters is not
governed by converter characteristics or system parameters.

Figure 4-1: Synchronized converters: Transformer voltages and current


(CH1: 480V wye-secondary high side transformer winding – 20V/div;
CH3: 208V Δ-primary low side transformer winding – 20V/div;
CH2: 480V wye-secondary high side transformer current flow – 5A/div)

51
Figure 4-2 shows current flow due to offsetting the amplifier amplitude once the voltage
phase was synchronized. The experimental procedure entailed slowly stepping up the
amplitude difference until a safety condition monitoring amplifier current flow was
triggered to trip. Shown are the last two steps prior to bypassing the 20 A trip threshold.

V M Current Draw and P E B B Trip at 20A


0.025

0.02

0.015

0.01

VMCurrent Draw(kA)
0.005

-0.005

-0.01

-0.015

-0.02

-0.025
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Tim e (s ec )

Figure 4-2: Non-synchronized converters: Current drawn via magnitude difference

Next, current flow due to the phase and magnitude differences (ultimately the
real/reactive power flow) were independently related to open-loop d and q-axes current
references; specifically, the d-axis controlling active power flow and the q-axis reactive.
The current references were then impedance scaled and sent to the AC PEC800 as
amplifier voltage references. Figure 4-3 and Figure 4-4 depict steady state phasor control
operation under 10 A Id and Iq open-loop controller references, respectively. Note that
100 VLL at 60 Hz excited the system. Furthermore, the 30° phase shift discrepancy from
the expected 0° for active power draw in Figure 4-3 is due to a line-line voltage
measurement. Line-line voltages lead line-neutral by 30°, thus showing that active power
was drawn solely from requesting d-axis current. A similar argument can be made for
q-axis current references via Figure 4-4; offsetting the line-line voltage by 30° shows a
90° phase shift, i.e., reactive power flow. The experimental procedure for testing the
independent power flow controls are as follows:
(1) set the VSD to sourcing 0 V
(2) activate the amplifier synchronization controls (0 A references) while
maintaining an open contactor between the drives; thus preventing any current
(3) close the contactor and slowly ramp up the VSD voltage to 25 V; allowing the
PLL to synchronize the amplifier with the VSD; mitigating initial current flow

52
(4) once synchronized further increase the voltage to 100 V; set the desired
dq-axes current references and take measurements.

VSD Output Vab vs. Ia

Ia INV out
100 VLL
10 Vab INV out

5 θdiff = 30°
Vab (V%10)

0
Ia (A)

-5

-10 10 A

0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055


Time (s)
Figure 4-3: Open-loop VM current references, Id =10A
VSD terminal characteristics, 100VLL 60Hz

53
VSD Output Vab vs. Ia

Ia INV out

10 Vab INV out


100 VLL

θdiff = 60°
Vab (V%10)

0
Ias (A)

-5

10 A
-10

0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055


Time (s)
Figure 4-4: Open-loop VM current references, Iq =10A
VSD terminal characteristics, 100VLL 60Hz

Although at different voltage excitations a comparison between Figure 3-10 and


Figure 4-3 verifies the active power flow experimental results via simulation. Figure 3-10
offsets the amplifier phase reference by 7° while Figure 4-3 commands 10 A of d-axis
current, yet both show current synchronized with voltage. Progressively, the next
experimental step was to excite a machine model to steady state via VSD voltage
feedback into RTDSTM and utilize an inverse Park Transform (B.10) to create dq-axis
current references. Then activate the current control scheme; ultimately recreating the
previous experiment without independently controlling the current references. Figure 4-5
shows the VSD terminal characteristics of such a test. The system is excited via 100 V,
30 Hz VSD output. Furthermore, a torque load of 1.5 percent was applied to the machine
in order to create substantial current draw for measurement (5.25A).

54
VM 100V 30Hz, 1.5% torque load

Ia
10 100 V
Vab

4
Vab (V%10)

0
Ia (A)

-2

-4

-6

-8
5.25 A
-10

0.02 0.03 0.04 0.05 0.06 0.07 0.08


Time (s)
Figure 4-5: VM control, VSD terminal characteristics, 100VLL 30Hz, 1.5% loaded

Finally, the transient PHIL system response was analyzed by sending the machine
start-up transients as current commands, in lieu of waiting for steady state before
enabling the control scheme. Figure 4-6 shows the amplifier current draw, referenced and
measured current comparison, the machines electromagnetic torque and electrical speed,
as 160 V 20 Hz excites the machine to steady state. Such a value was chosen as it follows
V/Hz scaling for the 4 pole IM characterized in Table 3 and 2. When validating the
experimental transient response via the simulation results of Figure 3-12, a close match is
shown. The second graph overlaying amplifier current draw and current references shows
a 4.4 ms time delay. Such is expected for the phasor-based control strategy. Controller
latency issues and PHIL interface delay [4],[19],[24] prevent the instantaneous
amplification for the desired voltage references. By the time the referenced current is
recreated, the IM model is a few time steps ahead, requesting different currents.
Assessing the time delay would add a true real-time aspect to the VM controller, but
doing so would require a new predictive control strategy to account for the time delay.

55
IaAMP = 50 A
50
IaAMP_SS = 3 A

Iabcamp (A) 0

-50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

50 Δt = 4.4ms
Iamp vs. IVMref

0 Iamp
IVMref
-50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.5
e (p.u.)

-0.5

-1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
150
e (rad/s)

100

50 ωSS = 125 rad/s


0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (s)
Figure 4-6: Experimental VM start-up transient response, 160VLL 20Hz

4.2 Validation via Physical IM


In order to fully validate the steady state VM results, the VSD terminal
characteristics were compared when energizing both the VM and the actual IM for three
different excitation and loading scenarios. Figure 4-7 compares the two as the VSD
supplies a 240 VLL 30 Hz excitation; the blue plot is the real IM, while the red is the VM.
The IM was unloaded; the mechanically coupled DC machine was not controlled to
provide counter torque. Note that the mechanical coupling alone provides a low amount
of torque as it contributes inertia to the system; note the resulting 4.7 A current flow. In
order to create similar current flow for the VM experiment, a 0.25 percent torque load
was applied to the modeled machine. Inspection of Figure 4-7 shows the VSD
240 V 30 Hz excitation for both systems and a phase shift between currents, as previously
hinted from the simulation results of Figure 3-11. The experimental phase shift is nearly

56
half (θdiff = 8°) of that the simulation results predicted (θdiff = 15°). Furthermore, note the
high noise content of the unloaded 4.9 A currents; as later shown, loading provides higher
current draw that reduces the noise content.

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
250 15
240 V
200

10
150

100 θdiff = 8°
5

50
Vab (V)

Ias (A)
0 0

-50

-5
-100

-150
4.9 A -10

-200

-250 -15
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
Time (s)
Figure 4-7: Experimental VM vs IM terminal characteristics, 240VLL 30Hz, unloaded

To analyze the harmonic content, Figure 4-8 provides an FFT spectral analysis for
the measurements. The most obvious difference in FFTs, is that the VM current and
voltage spectrums contain 5 kHz, 1 kHz and 9 kHz harmonics that are inherited from the
5 kHz switching frequency of the amplifier and its combination with the 4 kHz switching
of VSD. 8 kHz and 12 kHz multiples of 4 kHz switching frequency are apparent in all
waveforms, but only the VM voltage spectrum shows the 10 kHz component from the
amplifier. This is intuitive as IM is not subjected to the switching and the transformer
provides enough inductance to filter the current.

57
Single-Sided Amplitude Spectrum of Ias IM/VM
1
2.12 A, 4 kHz IM
VM
4.9 A, 30 Hz 0.5
0.6 A, 12 kHz
|Ias (f)| 0

4.2 A, 30 Hz 0.25 A, 5 kHz 0.8 A, 12 kHz


-0.5

0.22 A, 1 kHz 2.5 A, 4 kHz 0.6 A, 9 kHz


-1
0 2000 4000 6000 8000 10000 12000

Single-Sided Amplitude Spectrum of Vab IM/VM


4
18 V, 4 kHz IM
240 V, 30 Hz VM
2
3 V, 12 kHz
|Vab(f)|

3.2 V, 12 kHz
-2 1.2 V, 5 kHz

8 V, 4 kHz 2.4 V, 9 kHz


-4
0 2000 4000 6000 8000 10000 12000
Frequency (Hz)
Figure 4-8: VM vs IM experimental FFT; 240VLL 30Hz; unloaded

Similar analysis was carried out for two loading scenarios, 2 percent and 4 percent
of the rated torque. The IM-DC load system is not rated for loading past 850 rpm, thus a
160 V 20 Hz excitation keeps the system around 585-600rpm, well within its mechanical
limitations. Figure 4-9 and Figure 4-10 show the comparison in VSD terminal
characteristics for the 2 percent and 4 percent loading conditions, respectively; while
Figure 4-11 and Figure 4-12 show FFT spectral analyses. The ratio between the
fundamental components (20 Hz) with the VSD switching frequency (4 kHz), are much
greater than the unloaded case. Thus the current appears much more sinusoidal. As
expected the unloaded 4.9 A current draw increased to 8.9 A and 11.9 A as the torque
increases from 2 percent to 4 percent the rated torque. Another key difference is that as
the torque load increases, the harmonics from 5 kHz amplifier switching frequency
decrease; thus the 1 kHz and 9 kHz harmonics decrease as well. Note that torque loading
conditions were kept in a low range to minimize keep current draw, ultimately a safe
measure for staying within the equipments rating and for keeping the dissipated heat low
when running the equipment for long periods of time.

58
VM: 160V-20Hz 2% torque ref --- IM: 160V/20Hz SVM SS-2% torque ref
40

160 V
30 Ia IM
Vab IM
Ia VM
20
Vab VM

10
Vab (V%5)

0
Ias (A)

-10

-20 8.9 A

-30

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Time (s)
Figure 4-9: Experimental VM vs IM terminal characteristics, 160VLL 20Hz, 2% load

VM: 160V 4 % torque ref --- IM: 160V/20Hz SVM SS-4 % torque ref
40

160 V

30 Ia IM
Vab IM
Ia VM
20
Vab VM

10
Vab (V%5)

0
Ias (A)

-10

-20

11.9 A
-30

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Time (s)
Figure 4-10: Experimental VM vs IM terminal characteristics, 160VLL 20Hz, 4% load

59
Single-Sided Amplitude Spectrum of Ias IM/VM
1.5
1.6 A, 4 kHz IM
1 0.6 A, 12 kHz & 16 kHz VM
8.9 A, 20 Hz
0.5

|Ias (f)|
0

9.6 A, 20 Hz -0.5 0.01 A, 5 kHz


0.22 A,
-1 1 kHz 2.1 A, 4 kHz
0.7 A, 12 kHz & 16 kHz
-1.5
0 0.5 1 1.5 2 2.5 3
4
x 10
0.8 V,
Single-Sided Amplitude Spectrum of Vab IM/VM
1 kHz
14 V, 4 kHz 2.3 V, 12 kHz & 16 kHz IM
2
160 V, 20 Hz VM
1
|Vab(f)|

-1
0.4 V, 5 kHz
2.6 V, 12 kHz
-2
5.1 V, 4 kHz 2.2 V 16 kHz
0 0.6 V, 0.5 1 1.5 2 2.5 3
1 kHz Frequency (Hz)
x 10
4

Figure 4-11: VM vs IM experimental FFT, 160VLL 20Hz, 2% load

60
Single-Sided Amplitude Spectrum of Ias IM/VM
1
0.5 A, 12 kHz IM
0.65 A 16 kHz VM
11.9 A, 20 Hz 0.5
1.4 A, 4 kHz
|Ias (f)| 0

12 A, 20 Hz 0.05 A, 1.38 A, 4 kHz


-0.5
1 kHz 0.5 A, 12 kHz
(both) 0.7 A 16 kHz
-1
0 0.5 1 1.5 2 2.5 3
4
x 10

Single-Sided Amplitude Spectrum of Vab IM/VM


4
0.74 V,
1 kHz 10 V, 4 kHz 2.3 V, 12 kHz & 16 kHz IM
160 V, 20 Hz VM
2
|Vab(f)|

-2 0.37 V, 5 kHz
2.5 V, 12 kHz
0.48 V, 1.5 V 16 kHz
8 V, 4 kHz
1 kHz
-4
0 0.5 1 1.5 2 2.5 3
Frequency (Hz) 4
x 10
Figure 4-12: VM vs IM experimental FFT, 160VLL 20Hz, 4% load

4.3 Limitations
The methodology and equipment used to implement and validate the proposed
VM control concept exposes the final operation to various limitations, possibly inhibiting
higher granularity results. Although not confined to hardware, the VSD, IM-DC load
used for VM validation, PHIL interface, and VSS each contribute restraints. Prior to
elucidating individual component limitations, it is imperative to reiterate the inherent
limitations of a phasor-based VM control solution. By abstracting the PHIL coupling
network as a strictly reactive, constant value, a stipulation requiring constant excitation
frequency arises. Given that the inverter control strategy operates under V/Hz control
logic, only a stiff VSD of constant magnitude and frequency can satisfy such a
requirement. Hence, the highly accurate steady state VM results when validated against
traditional VSD-IM operation. More advanced machine drive operation is done under
variable speed (or frequency) control, hence VSD. Thus, for a more traditional
closed-loop VSD operation, additional controls would need to be implemented to

61
recalculate the impedance of the coupling network based on the instantaneous excitation
frequency. Such a provision would also require a highly responsive phase tracking
mechanism, e.g. [49], to consistently synchronize the amplifier with a dynamically
changing frequency. The PLL implemented could fall short in tracking drastic frequency
disturbances; an extra degree of error atop high noise content preventing accurate phase
lock and the time required to accurately lock-on. In addition to this, the VSD would need
a more advanced inverter closed-loop control strategy taking the VM speed signal as
feedback.
Furthermore, while the phasor-based current control strategy accurate reproduces
transient current references, as experimentally shown in Figure 4-6, there is a 4.4 ms time
delay. Reducing the time delay brings rise to the limitations of the PHIL interface and the
VSS. The inherent drawbacks limiting the PHIL interface from instantaneously recreating
the modeled machine characteristics are due to the time latency required to:
(1) sense the VSD voltage, and send the measurement into the VSS; sampling delays
(2) apply it to the modeled machine terminals, process the result as a current
command, and calculate the amplifier voltage reference; all of which are internal
VSS delays
(3) physically switch IGBTs and reproduce the voltage command; controller and
device time delays
While some controller delays are unavoidable, they can be mitigated. A more advanced,
predictive control solution for determining current references prior to actually being
commanded from the modeled machine would create a more real-time VM solution;
although, system delays would need to be incorporated into such a prediction. The
bandwidth of the voltage amplifier is constrained to the converter switching frequency,
5 kHz, and limits the ability to reproduce transient conditions such as unknown torque
load pulsations. Furthermore, the VSS model implemented on the RTDSTM could be
optimized and brought closer to the 2μs time step limit; currently it is at 50 μs. Reducing
the time step could compromise the validity of the modeled machines non-linearity. The
Δ-Y transformer (part of the PHIL LCL filter) necessary to provide the voltage
compatibility between converters, not only creates a phase shift, but attenuates the low
frequencies applied to the transformer. This in conjunction with low voltage magnitudes

62
that are applied to the transformer appear non-linear and unbalanced, limit the low speed
range of the VM. In order to prevent the converter switching patterns’ high frequency
voltage ripple from affecting the transformer, converter output filters must be used.
Specifically, the VSD sine filter incorporates additional impedance into the traditional
PHIL LCL-filter topology. The amplifier then presents the unique problem of subjecting
the reproduced VM terminal characteristics to these switching harmonics; i.e. amplifier
produced distortions. Traditional machine operation has no exposure to such harmonics
introduced when replacing a machine with power electronics. Moreover, the amplifier
fuse rating limits the power rating from 50 kVA to 25 kVA. Finally, the DC machine
speed rating limits the validation of the VM to 30 Hz, unloaded. Given a higher rated
mechanical system, a full 60 Hz speed range could be assessed.

4.4 Future Work


Various avenues are available to further the VM via future work; ultimately
preparing it for 5 MW implementation. Higher power level machines cost exponentially
more to design, validate, and fabricate than their medium and lower voltage counterparts;
thus a 5 MW or greater application of the VM concept would provide the most significant
cost deduction when prototyping and testing either novel machine drives or machine
topologies. Presently, available at FSU-CAPS is a 5 MW, 6.25 MVA level test bed,
hence providing a reasonable future work objective for the VM. Prior to such aspiration,
all of the previously listed limitations would need to be addressed at the 25 to 50 kVA
power level to provide a higher fidelity VM, yet still mitigate any risks involved to the
lower power level. Specific attention needs to be given to analyzing the transformer PHIL
interface’s stability issues, time latencies, non-linearities, and frequency attenuation; as it
is unique to the PHIL field. Other improvements could incorporate a closed-loop VSD
inverter strategy, e.g.: constant slip current control [38]; the outer-loop speed control
inner-loop current controller featured in Figure 3-5 [50]; a strategy based on VSD IM
control through an output filter [46]; or traditional maximum torque per ampere IM
control [48]. The first two of which are relatively similar to controls already implemented
on the VSD-AFE and would provide a nice learning curve for debugging and developing
closed-loop VSD-VM operation. A more strenuous approach to analyzing the dynamic

63
VM response could also be addressed; i.e. controlled start-up, load change responses, and
speed and torque control of the machine via the VSD. Also available for validation are
other machine types, specifically a PMSM. Further application of the PHIL load
emulation, VM concept could facilitate the development of a not only current sink
application, but also sourcing via a virtual generator, possibly validated via the PMSM.
By utilizing the same parallel connected converter control theory, but instead of
simulating a machine for current references, one could simulate a virtual microgrid which
utilizes the reactive power compensation ability of a static synchronous compensator
(STATCOM). The necessary reactive power compensation controller would be integrated
into the VSS with the virtual microgrid to control the STATCOM such that proper
amplifier voltage references were generated [34],[51]. Various power compensation
scenarios are then possible as the amplifier adjusts its voltage accordingly with respect to
the VSD.

4.5 Conclusion
In this thesis, a testing method for removing the risk associated with the testing
and development of novel drive technologies and control strategies without using any real
motors/generators to test VSDs was presented. The proposed technique utilizes the PHIL
load emulation concept to recreate the terminal characteristics of a high fidelity induction
machine modeled in a real-time environment, thus no rotating machinery required.
Specifically, the current draw is recreated via altering the phase and magnitude of a
voltage amplifier parallel connected with a VSD under test via a unique LCL type filter.
Specifically, a Δ-Y transformer proved adequate for not only providing the necessary
voltage step between parallel connected converters, but also as a PHIL filter structure
regardless of inherent non-linearities; ultimately allowing the voltage amplifier to be
controlled to create the necessary voltage drop across the coupling LCL impedance to
draw the modeled machines current command.
The specifications and necessary modifications to the 25 kVA test bed used for
VM implementation were presented alongside the major challenges associated with each.
Next, the mathematics necessary for IM modeling; implementing the three modulation
strategies; and the VSD AFE, inverter, and voltage amplifier controls were thoroughly

64
presented. Computer simulations and experimental results were compared in a
developmental procedure against an actual VSD operated IM in order to validate the
approach safely. Steady state VM results matched very closely to an actual IM. Although
the phasor-based current control solution is based on a linear steady state principle, when
tracking transient machine start-up current references, it performs adequately with minor
time delay. Various system and methodological limitations of the phasor-based control
approach and the VSD, PHIL interface and VSS were given; keynoting on PHIL
amplifier bandwidth and latency, transformer non-linearities, and open-loop VSD
operation. Finally, future works show that assessing the distinguished restrictions would
provide a higher fidelity VM solution prior to scaling the power level up to 5 MW.

65
APPENDIX A
EQUIPMENT SPECIFICATION
A.1 Machines
The nameplate parameters for the 15 hp inverter duty Motor Reliance Electric IM
are shown in Table 3. Proper modeling of this machine in the virtual realm will require
more specific machine details, thus Table 4 illustrates IM equivalent circuit data found
from both the IM datasheet and calculated from IEEE standard 112. For more
information on no-load, DC, and locked-rotor tests determining electric machine
parameters please refer to [52],[53],[38].

Table 3: IM nameplate parameters


Horsepower rpm Amps Volts Hz
15 885 20.4 460 30
15 1765 18.6 460 60

Table 4: IM equivalent circuit parameters


VsN = 460 V IsN = 20.4 A
fsN = 30 Hz p=4
Rs = 0.26 Rr = 0.175
Ls = 0 4.72 mH Lr = 7.74 mH
Lm = 126.26 mH

The 15 hp Reliance Electric DC motor is used to load the IM through a TM 312


torque transducer. Table 5 shows similar nameplate data for the DC machine. Note that
no field current regulator kit is installed, thus the nameplate field data is used as input.
Furthermore, note that the DC machine cannot exceed 850 rpm without field weakening,
a test bed feature that has not been enabled. As this is coupled with the IM, such a rating
places a constraint on attainable operating speeds under loaded conditions. The torque
transducer is overrated for this application handling up to 500 N·m of torque and high
speeds up to 32000 rpm, values far exceeding the requirements of IM operation. Note that
equivalent circuit model data is not of primary concern for the DC machine, as its
purpose is only to provide a counter-torque load to the IM. The DC load models used in

66
the virtual realm simply will provide this counter-torque mathematically. Further
information using the machines data for modeling is addressed in Chapter 3. Figure A-1
is a lab photograph of the IM and DC machines mechanically coupled.

Table 5: DC machine nameplate parameters


Rated Nameplate Data Field Data
Voltage 500 V Voltage 300 V
Max Safe Speed 3600 rpm Winding Type Shunt
Power 15 hp Amperage 2.47
Amperage 25 A Hot Amps. 1.86/0.86
Max Speed 850/1700 rpm

DC Machine

Induction
Machine

Figure A-1: Test bed IM and DC load

A.2 25 kVA Interface Voltage Amplifier


A 25 kVA AC/DC/AC drive operates as the PHIL simulation interface voltage
amplifier consisting entirely of off the shelf control and power components fed from the
208 V Tallahassee grid. The drive is nearly identical to the topology of the VSD
back-to-back DC-link coupled converter topology previously illustrated in Figure 2-2. An
actively controlled rectifier front end is interconnected to another force-commutated
inverter via a DC-link capacitor; again compensating for bidirectional power flow, but
with an ABB PowerPak 3-3 module comprising the assembly of the amplifier, in lieu of a
Danfoss unit. The design, commission, and assembly of the 25 kVA interface voltage

67
amplifier was the product of a previous Center for Advanced Power Systems (CAPS)
project.
The ABB PowerPak 3-3, essentially an IGBT based power electronic building
block (PEBB), contains three LoPak5 IGBT modules, a DC-link capacitor bank, and
Semikron SKHI65 gate drivers. In addition to the necessary voltage and current
measurements, power and fault/protection devices, and drive controllers, the PowerPak
gives the amplifier multiple functionalities, assuming the hardware/software is configured
appropriately, hence the term “power electronics building block”. Of the available
hardware, two of the LoPak5 IGBT modules and the DC-link capacitor bank makeup the
AC/DC/AC converter. An aluminum heat sink and water coolant backplane provides
thermal relief for the IGBTs switching substantial values of current at 5 kHz. The
3-phase, 208 V grid input passes through a filter before connecting to the IGBT module
forming the AFE, for a detailed diagram of the amplifiers design and power electronics
see [54],[55]. The amplifier also contains a harmonic filter at the inverter output
(identical topology to the filter seen Figure 2-4) with parameters: 600 μH inductance,
0.1 Ω resistance, and a 20 μF capacitance.
Control of the amplifier is accomplished through two separate ABB controllers.
The μT-PEC AFE controller, a former ABB specific design concerning a micro turbine
project, controls reactive draw through the input filter and a steady DC-link voltage. An
AC PEC800 in conjunction with various peripheral hardware (current/voltage transducer,
combinational I/O, PEBB interface and DC offset boards, PEC measurement boards, and
commission interface box) controls the back-end inverter. Voltage references sent via
RTDSTM are directly sent to the controller’s sine wave pulse width modulation (SPWM)
module. Both controllers algorithms are programmed via MATLAB/Simulink RTW via
an Ethernet connected host PC.
Previously, another first generation ABB μT-PEC controlled the DC/AC inverter
back-end, until a separate project recently updated the controller to a newer, supported,
AC PEC800 [56],[57]. The inverter μT-PEC controller limited the smallest possible time
step of the 25 kVA amplifier and did not provide any application level control builder
functionality. Upgrading to the AC PEC800 allowed the inverter to be controlled under
both closed and open-loop voltage control algorithms; formerly restricted to open-loop

68
control, RTDSTM voltage references are directly forwarded to the SPWM block. The
closed-loop control strategy, commonly called “amplifier mode”, sends the references to
the AC PEC800 subordinated current controller and allows the generation of up to the
23rd harmonic; open-loop SPWM references suffice for VM implementation, as harmonic
reproduction is unnecessary. Specific details regarding the voltage amplifiers’ AFE and
inverter control strategies are not the focus for this thesis, only the voltage amplifier
functionality. Specifically, that allowing the reproduction of machine terminals
characteristics via PHIL references sent from RTDSTM. A more comprehensive overview
can be found in [58],[59],[60]; note that some of the control scheme is proprietary to
ABB.
Table 6 provides technical detail of the amplifier. Figure A-2 depicts an open
cabinet view of the 25 kVA interface voltage amplifier, annotating various components.
Not shown or annotated: power supplies, commissioning interface, terminal blocks,
contactors, DC bus braking resister, or fans. Finally, note that the amplifier power rating
could be increased to 50 kVA given higher rated fuses within the voltage amplifier.

Table 6: Voltage amplifier technical specifications


Amplifier Type Voltage or Current regulated
Amplifier topology AC / DC / AC
Power flow direction bidirectional
AFE/Inverter Pulse Width Modulation, carrier frequency
Voltage modulation pattern fs = 4 kHz.
Input voltage 3 phase AC, 208 V (line – line)
DC bus voltage 390V
Output voltage 3 phase AC, 0~240 V
Output power 25 kVA (fuse limited)
Output Filter L = 600 μH, R = 0.1Ω, C = 20 μF
Bottleneck is sample time of controls,
Time delay
minimum delay ~ 100us
1.5 kHz (allows the reproduction of harmonic
Bandwidth
order up to 23th)
IGBT switching Harmonic THD < 5% when generating 60Hz
injection fundamental waveform

69
Current/Voltage
Combinational Transducer
I/O

Inverter: Interface firing


AC 800PEC pulse &
Controller DC offset Boards

Two PEC
Measurement
AFE: μT-PEC Interface Boards
Controller

Sensors, I/O Filter


Components, IGBTs,
Liquid Cooling

Figure A-2: Open cabinet view of 25 kVA interface voltage amplifier

A.3 45 kVA Δ-Y, 208/480 Transformer


A 45 kVA, Δ-Y transformer is used when stepping up the primary, Δ-connected,
208 VLL interface voltage amplifier output to coincide with the secondary,
wye-connected, 480 VLL VSD output. The transformer provides galvanic isolation and
filtering due to winding inductance. Furthermore, due to the Δ-connection, the secondary
voltage lags the primary by a 30° electrical phase shift. Such a phase shift is of major
concern when modeling the transformer and when implementing a PLL to synchronize
amplifier voltage output with the VSD. The relationship between the transformer winding
ratio and the primary-secondary voltages and currents is shown through (A.1). Note that
line or phase voltages are not of concern as the 3 root three terms divides out. The
transformer’s low-side winding inductance and the voltage amplifier’s output filter
(LCR) form a LCL PHIL coupling interface filter unique to this study; effectively

70
filtering the 5 kHz switching frequency, yielding a cutoff frequency of 1.5 kHz. Figure
A-3 shows a transformer with its front panel removed. Note that tertiary windings exist
but are not utilized in this application, thus their terminals are disconnected and
ungrounded. Table 7 provides more technical data for the transformer.

Np I s V p 208VLL
    0.4333 (A.1)
Ns I p Vs 480VLL

Figure A-3: Open cabinet view of 45 kVA Δ-Y, 208/480 transformer

Table 7: Technical specifications of the 45 kVA transformer


Manufacturer POWERTRAN USA
Type Dry Transformer Class AA
Rated Power 45 kVA
Temperature Rise 150 °C
Weight 490 lbs
Insulation System FH4G, 220 °C
Ambient Temperature 40 °C max
Connection 3-phase Δ-Y
Frequency 60 Hz
Primary Voltage 3-phase 208 VLL
Primary Current 125 A
Secondary Voltage 3-phase 480 VLL
Secondary Current 54.1 A
Impedance 5.18 %

71
APPENDIX B
BACKGROUND THEORY
B.1 Reference Frame Theory
Phase variables are one method of expressing various system parameters through
excitation voltages or currents. Frequently, these parameters are internal to the system;
consequently, they are often not measurable or practically feasible to use in analytical
considerations and are limited to being expressed in terms of the excitation frequency.
For example consider the abstraction of placing sensors on the fictitious windings present
within the rotor of an AC machine. These abstract values are not accessible to measure as
they represent quantities inside the machine, thus introducing the need to express
variables in other frames of reference. Reference frame theory (RFT) is commonly used
when transforming rotational or stationary systems with multiple frequencies into a
universal frame of reference, removing mathematical complexities. An example of
reduced complexity is evident when applying the reference frame transformation to an
induction machine, referring the stator and rotor to a frame rotating at a common angular
velocity, eliminating the time-varying inductances. Other applications of RFT are helpful
in the analysis of various static power-system components or control systems associated
with electric drives [38], both of which will be applied to the VM test bed.
Therefore, it is instructive to briefly introduce the theory of transforming variables
from an abc frame of reference to a newly defined qd0 frame of reference. Figure B-1
[38] shows the trigonometric relationship between the abc and qd0 planes while Table 8
defines the associated parameters. Note that “f” is left generic but could represent
voltage, current, flux linkage or electric charge. By noting that fabcs in Figure B-1
represents stationary phase quantities (denoted via subscript s) being transformed to fqd0s,
quantities associated with the arbitrary rotational speed ω, one may begin to visualize
how fabcs is transformed into fqd0s. The rotating frame of reference may be defined as
needed: constant, synchronous, stationary, or any other convenient value.

72
Figure B-1: Trigonometric relationship for stationary abc to arbitrary dq0 transform

Table 8: Figure B-1 transformation variable description


fabcs Phases 120˚ apart, stationary paths
fqd0s Orthogonal 90˚ planes, f0s coming out of the page
ω Angular velocity of fqd0s
θ Angular displacement of fqd0s

In other words, RFT transforms three-phase variables into orthogonal components


along an axis offset by θ, the angular displacement. Note that θ and ω are directly related
to the desired frame of reference through the orthogonal axes, d and q. The zero-variables
are not associated with θ, thus are only mathematically related to abc-variables via
phase-balancing; for the use of RFT regarding this work all phases are assumed to be
balanced, thus the 0-axis may be ignored. Before proceeding with the equations
describing the RFD trigonometric relationships, note that stationary phase variables are
assumed to be the initial frame of reference. The interested reader should investigate [38]
for analysis when transforming between reference frames. The Clarke Transform is
defined as the stationary abc-phase variable transformation to the stationary dq0
reference frame, i.e. ω is zero. Common notation refers to the stationary dq0-plane as the
α -plane. Although a direct, one step mathematical transform exists, a two step
mathematical procedure is commonly followed when transforming to an arbitrarily
rotating reference frame [38],[61] from a three phase stationary plane.
(1) The Clarke Transform is used to convert the three phase stationary coordinate
plane into the two phase α -plane. Note that under balanced conditions the
-axis disappears mathematically.
(2) Next the stationary α -plane is projected onto the rotating dq0-plane. Once
again, under balanced conditions the 0-axis vanishes.

73
The Clarke Transform alone is useful as it not only provides the intermediate
stationary transform, but also an analytical method for determining the phase and
frequency of the transformed signal. Trigonometrically it is very similar to the transform
depicted in Figure B-1, yet does not require θ, as the target frame of reference is
stationary. To mathematically represent step (1), the forward abc-α and inverse
α -abc transforms are shown by (B.1) and (B.2), respectively. Note that [38] provides
further detail regarding the mathematical derivation. Once in the stationary reference
frame another trigonometric operation, (B.3), further transforms onto an arbitrary
reference frame rotating with some defined angular speed, ω, with phase θ; thus step (2)
shown mathematically. Under circumstances where one wishes to transform into the
reference frame rotating synchronously with the phase angle of the abc-phase input, (B.4)
is used. Other methods to obtain θ vary depending on the application and desired frame
of reference: via the integrating the angular velocity, using a PLL, encoder feedback, etc.

 1 1  f 
 1  
 f  2  f 
a
2 2
f   
3

3  b 
(B.1)
  3
0  f 
 2 2   c 
 
 fa 
 1 0 
f  2 1 3   f 
  
 b 3 2 2  f   (B.2)
 f c   1 3
  
 2 2 

 f d   cos  sin    f   (B.3)


f   
 q   sin  cos    f  

 f 
  tan 1   (B.4)
 f 

Combining the two steps into one mathematical operation is referred to as the
Park Transformation, which is described below. A shorthand mathematical notation is
defined by (B.5) and (B.6), simplifying the fabcs and fqdos vectors, respectively. A

74
“forward” transform from the stationary abc-coordinate plane to an arbitrary rotating
dq0-coordinate plane is shown in (B.7).


( f qd 0 s )T  f qs f ds f0s  (B.5)

( f abcs )T   f as f bs f cs  (B.6)

f qd 0 s  K s f abcs (B.7)

In (B.8), Ks represents the trigonometric operation shown in Figure B-1 needed to


perform the transform. Similarly, (B.9) and (B.10) define the inverse process. For power
systems and machines applications the instantaneous power is equal regardless of the
reference frame. This is logical as observing a system from a different perspective should
not alter its outcome. Note the transformation constant is different than (B.1) to illustrate
a power invariant form, which mathematically equates power through the transformation,
see (B.11).

 2 2 
cos( ) cos(  3 ) cos(  3 )
2 2 2 
K s   sin( ) sin(  ) sin(  ) (B.8)
3 3 3 
 1 1 1 
 2 2 2 

f abcs  ( K s )1 f qd 0 s (B.9)

 
 cos( ) sin( ) 1
 2 2 
( K s ) 1  cos(  ) sin(  ) 1 (B.10)
 3 3 
cos(   
) 1
2 2
) sin( 
 3 3 

Pabcs  Pqd 0 s 
3
vqs iqs  vds ids  2v0 s i0 s  (B.11)
2

75
B.2 IM Modeling

B.2.1 Single Phase Equivalent IM Circuit (Phasor-based)


Phasor theory is helpful for simplifying trigonometric calculations performed on
AC quantities into algebraic ones by removing the time-variance from a waveforms
amplitude, phase, and frequency. When simplifying circuit analysis via a phasor
abstraction, the excitation frequency, common to all electrical components, is maintained
at a constant value, ωe. Furthermore, due to the time-invariance only steady state
conditions are accurately modeled, accurate transient response under varying input
requires a more in depth model.
The single phase, phasor-based equivalent circuit model is the simplest
approximation of an induction machine. An extremely close resemblance exists between
the single phase transformer equivalent circuit and that for the IM. This should be
intuitive as both operate on the same physical principle: inducing voltage and current into
a secondary winding via magnetic coupling. IM are magnetically coupled via an air gap,
creating a higher reluctance flux path, thus resulting in a more gradual magnetomotive
force-flux slope than that of a transformer, which is magnetically coupled via an iron core
[53]. Another considerable difference is that IM design exploits the magnetically induced
current and resulting electromagnetic fields to create electromagnetic force, inducing
torque on a prime mover, the rotor. Furthermore, IM are typically singly excited in that
only the primary winding, the stator, has applied voltage; whereas transformers are
typically utilized to step voltage and current between windings, having voltage present at
both terminals. Considering this principle one may refer the rotor circuit (secondary) to
the stator (primary) to obtain the circuit of Figure B-2. Note that variables representations
that are not immediately intuitive: Rc represents the core resistance, XM the magnetizing
reactance, and Rconv are described below. By solving Ohm’s Law for impedance, then
substituting (A.1) for the voltage and current, the square of the transformer turns ratio is
derived to mathematically refer impedances from the secondary rotor circuit into the
primary stator circuit; derived via (B.12). Note that the rotor subscript “r” is represented
as “2” once referred. The stator and rotor impedances are common datasheet parameters,

76
when not known they are easily found via the experiments outlined in
IEEE Standard 112; detailing such experiments are not the focus of this work.
2
 Np 
Z 2    Z R (B.12)
 Ns 

Rs jX1 jX2 R2
+

Vas RC jXM Rconv

-
Figure B-2: Single phase equivalent IM circuit, including rotor copper losses

The changing rotor characteristics due to machine speed variance are represented as
varying impedance, notated via Rconv, and shown in (B.13) as a mathematical relationship
between rotor resistance and speed. Note that slip, s, is a term used to define the
relationship between the mechanical shaft speed of the machine’s rotor, ωr, and that of
the rotating magnetic fields, ωe. Equation (B.14) mathematically defines the term on a per
unit basis.
R2 1 s 
Rconv   R2  R2   (B.13)
s  s 

e  r
s (B.14)
e

A further simplification can be made by neglecting the rotor copper and core
power losses. When modeled, the simplified circuit, shown via Figure B-3, is populated
via the IM parameters provided in Table 4.

77
Rs jX1 jX2
+

Vas jXM R2/s

-
Figure B-3: Single phase equivalent circuit, neglecting core and rotor copper losses

A relationship between electrical air gap power, PAG (B.15), electromagnetic


torque, Te (B.16), and rotor speed, ωr, brought together via Newton’s Law (B.17) allows
the mechanical aspects of the machine to be accounted for. I2 is the rotor current referred
to the primary winding, J is the inertia of the rotor (kg·m2 or J·s2), P is the number of
magnetic poles within the IM, and TL is positive for a mechanical shaft on the IM.
R2
PAG  3I 22 (B.15)
s

PAG
Te  (B.16)
 sync

2
Te  J  r  TL (B.17)
P

B.2.2 Differential Equation based Three-Phase IM Model


A differential equation based modeling technique provides a higher granularity
dynamic solution for observing transient IM performance under varying excitation
voltages and frequencies. The single phase equivalent phasor-based circuit of Figure B-3
lacks such detail under dynamic conditions, therefore equations (B.18)-(B.31) will be
used to represent the IM. Table 9 provides definitions for variables in the following
derivations.

78
Table 9: Description of variables in IM derivations
Ls Stator winding inductance
Lms Stator magnetizing inductance
Lsr Mutual inductance between stator and rotor
L’sr Mutual inductance between stator and referred rotor
θr Electrical angular displacement of rotor
θrm Mechanical angular displacement of rotor
L’r Referred rotor inductance
L’lr Referred rotor leakage inductance
Lls Stator leakage inductance
ωe Electrical speed
XM Magnetizing reactance
Xlr Referred rotor leakage reactance
Xls Stator leakage reactance
P Number of magnetic poles
Te Electromagnetic torque
TL Load torque
m Damping coefficient
J Inertia constant

Equations (B.18)-(B.20) define the stator, referred rotor, and stator to referred
rotor mutual inductances, respectively. In (B.21)-(B.23) the stator magnetizing, leakage,
and the referred rotor leakage inductances are expressed in terms of reactance. Such an
expression is necessary as machines commonly are defined by reactance due to the ease
of implementation into a per unit system. Next, equations (B.24)-(B.26) form the base of
the dynamic design. Both the stator and referred rotor three phase voltages are described
through (B.24). The substitutions of (B.18)-(B.23) into (B.24) are necessary to obtain the
final form for each of the voltages; this will be left out due to its lengthiness and
redundancy. Electromagnetic torque, Te, is defined in both equations (B.25) and (B.26),
the first produced via electrical excitation, and second described from Newton’s Second
Law. Equation (B.25) is used to solve for Te, and substituted into (B.26) to solve for
angular acceleration; thus allowing integration to obtain θr, as in (B.27). Equation (B.28)
relates electrical and mechanical rotor displacement via the number of poles, P. Finally,
the stator, shaft, and rotor powers are all solved for in (B.29)-(B.31), respectively. The
interested reader may find another IM modeling technique via [62].

79
 1 1 
 Lls  Lms 
2
Lms 
2
Lms 
 1 1 
Ls    Lms Lls  Lms  Lms  (B.18)
 2 2 
1L 
1
Lms Lls  Lms 
 2 ms 2 

 1 1 
 L'lr  Lms 
2
Lms 
2
Lms 
 1 1 
L' r    Lms L'lr  Lms  Lms  (B.19)
 2 2 
1L L'lr  Lms 
1
 Lms
 2 ms 2 

 2 2 
 cos( r ) cos( r 
3
) cos( r  )
3 
 2 2 
L' sr  Lms cos( r  ) cos( r ) cos( r  ) (B.20)
 3 3 
cos(  2 ) cos(  2 ) cos( r ) 
 r
3
r
3 

X ls
Lls  (B.21)
e

X 'lr
L'lr  (B.22)
e

2 X
Lms    M (B.23)
 3  e

 Vabcs   rs  pLs pL'sr   iabcs 


V '    p ( L' )T r 'r  pL'r  i 'abcr 
(B.24)
 abcr   sr

P T 
Te   iabcs  L'sr i'abcr (B.25)
2  r

2 dr 2
Te  J   m r  TL (B.26)
P dt P

80
d r
r  (B.27)
dt

P
 r    rm (B.28)
2

Pstator  i 2 as rs  i 2 bs rs  i 2 cs rs (B.29)

Pshaft  Te rm (B.30)

Protor  i ' ar r ' r i ' br r ' r i ' cr r ' r


2 2 2 (B.31)

B.2.3 VSS (RSCAD) Model


RSCAD, the software used for modeling the VSS, has an IM model with a large
community of users that have provided model feedback and ensured accurate model
validation long before the VM project. Due to this and the influence the IM model has on
the operation and validity of the VM, this model will be implemented. Furthermore, both
the previously discussed equivalent circuit and differential equation based models are
utilized with generalized machine theory to create a detailed electromagnetic transients
dq0-representation. Model features include built in torque loading and speed control
features, reconfigurable magnetizing current saturation curves, multiple rotor cages, and
various other reconfigurable machine parameters [63],[64]. To visualize the model and
how it interfaces with the VSD measurements see Figure B-4.

Figure B-4: RSCAD IM Model, VSD connected

81
B.3 Modulation Strategies

B.3.1 Hysteresis Modulation


Hysteresis modulation, or bang-bang, is the simplest modulation strategy. When
used to modulate current, it is known as hysteresis current control (HCC). The hysteresis
value represents the tolerable deviation above and below the reference that the actual
currents are regulated between. Error between current references obtained via an
outer-loop control strategy and measured feedback is calculated. Then the calculated
error is sent into a relay comparator with its bounds set to the hysteresis band, thus the
error is bound between the hysteresis values. If the measured current is less than the
difference between referenced current and the lower hysteresis band, the upper switch of
the bridge is turned on, allowing the current to increase. Likewise, once the measure
feedback increases past the sum of upper band and the reference current, the upper switch
is then turned off, causing current decay. This process is repeated indefinitely to maintain
the error between the defined hysteresis bands, ultimately causing the current to track the
reference. Figure B-5 illustrates HCC operation as the current is controlled between the
set hysteresis bands. Note the pulses are high for increasing current, have the amplitude
of half the DC-link voltage, and no set switching frequency.

Figure B-5: Operation principle of HCC; courtesy of [65]

82
Like most two-level modulation strategies, the two switches of one phase leg have
complemented firing pulses. Under HCC the VSD acts as a three phase current source, as
current references are recreated at the output. The simplicity, ease of implementation,
direct access to current and quick controller response makes HCC an attractive
modulation solution, but with such simplicity comes drawbacks. The switching frequency
of the drive is not regulated or known at any time. Although known system parameters,
specifically inductance, play a major role in how fast the currents rise and fall during
each switching cycle, not every cycle repeats at the same rate. Aside from an improperly
designed line reactor, the hysteresis band selected could be too narrow for a given
controller’s speed; thus commanding switching every computational cycle, ultimately
saturating the converters switching frequency to that of the controller. Constant switching
events create various high frequency harmonics in the AC voltage output of the converter
and increase thermal heat (losses) greatly. Power losses and converter efficiency are
inherently higher for specific modulation strategies; therefore HCC is not the best choice
for applications looking to maximize these parameters.

B.3.2 Sine Triangle Pulse Width Modulation


Sine-triangle pulse width modulation, or sine-wave (SPWM), is a carrier based
modulation strategy to control converter switches. Unlike hysteresis modulation, in
SPWM the control variables do not oscillate between error bands modulating the
reference signal. Instead a bipolar triangular waveform of unity amplitude serves as a
carrier waveform used to modulate three phase sinusoidal converter duty cycles into their
corresponding pulse waveforms. The converter output voltage then follows the sinusoidal
duty references creating voltage source operation; this could be considered a
disadvantage in some motor drive applications since direct access to current provides
torque control. The relatively low frequency sinusoidal references appear constant against
a much higher frequency triangular carrier signal. Figure B-6 illustrates SPWM, showing
a single phase comparison between the carrier and a sinusoid duty reference for a
two-level, 6-pulse converter topology. Here the carrier switching frequency is 1.3 kHz,
much lower than typical implementation to provide distinction between pulses and their
switching logic.

83
SWPWM Illustration

Carrier vs. Reference


1

0.5

0
-0.5

-1
6 7 8 9 10 11 12
-3
x 10

1
Low Pulse A

0.5

0
6 7 8 9 10 11 12
-3
x 10

1
Hi Pulse A

0.5

0
6 7 8 9 10 11 12
time(s) -3
x 10

Figure B-6: SPWM switching logic

A comparator is used between the carrier and reference to govern each phase’s
firing pulses. Note that the top IGBT fires when the duty reference is higher than the
carrier, while the bottom is the complement. Necessary dead time compensation is not
shown [66] as is provided with many other protection schemes via the Aalborg card.
SPWM, while still a straightforward modulation strategy, limits many of the
low-frequency harmonics seen in more primitive, strictly comparator-based PWM
instantiations and provides less harmonic content than HCC. Furthermore, the triangular
carrier signal provides the converter with a constant switching frequency; useful in power
loss calculations, duty based firing pulse controllers, system parameters design,
pinpointing harmonics, etc.
Typically the duty cycle is limited between zero and one, implying that when
controlling the standard two-level, 6-pulse converter that the output amplitude varies
between zero and half the DC voltage (Vdc/2). By overmodulating, or commanding duty
cycle greater than one, this value can be increased to that attainable from standard PWM

84
techniques (Vdc(2/π)) with the added penalty of increasing low frequency harmonics. To
mitigate the low frequency harmonics while still increasing the output amplitude (Vdc/√3)
one must incorporate 3rd order harmonics into the sinusoidal duty reference [38].

B.3.3 Space Vector Modulation


Space vector modulation is an alternative to SPWM that still provides voltage
source operation without low frequency harmonics [67]. Major differences between the
two are that SVM exploits RFT, is more complex, and does not require comparators for
each phase, as in typical PWM strategies. A variety of SVM algorithms schemes exist,
therefore only the premise behind SVM will be explained as shown in Figure B-7







 

Figure B-7: SVM control flow

The eight possible switching states of the converter, denoted in Figure B-8 as
“k” (zero through seven), outline eight voltage vectors, denoted in Figure B-9 as Vk, in
which the instantaneous voltage vector, Vs, lies between; see for an Figure B-10 example.
The eight voltage vectors (two of which are redundant zero-vectors located at the origin)
form a hexagonal boundary outlining the six non-zero voltage states (sectors), each
spanning 60°. The following discussion relates to the two-level, 6 pulse converter since a
3-level, 12 pulse topology would increase the voltage vectors from eight (23) to
twenty-seven (33), greatly increasing complexity.

85
k=0 k=1 k=2 k=3

k=4 k=5 k=6 k=7


Figure B-8: Eight possible converter switching states

-axis
V3= [0 1 0] V2= [1 1 0]
Sector 2

Sector 3
Sector 1

V4= [0 1 1] θ=60°
V1= [1 0 0]
α-axis
V0 =[0 0 0]
Sector 4 V7=[1 1 1] Sector 6

Sector 5
V5= [0 0 1] V6= [1 0 1]

Figure B-9: SVM output voltage state diagram

Voltage references input into the modulation scheme (once again from some
external “outer-loop controller”) undergo a Clarke Transformation into the α -coordinate
plane. From the α -coordinate plane the voltage excitation angle is calculated (B.4) and is
used to determine the sector the instantaneous voltage lies within, this is intuitive as the
sectors are equally spaced by 60°. Specifically, as shown in Figure B-7, the resulting Vs
sector and a unitary ramp generator, used to produce the desired converter switching
frequency, is input into the switching time calculator. Inside the calculator the
instantaneous voltage vector is then broken into contributions from the two adjacent
voltage vectors that outline the sector, Figure B-10. To better understand the adjacent
voltage vectors the switch logic of the upper IGBT is denoted in Figure B-9. Notice that
only one switch differs between adjacent sectors. The components of Vs along the two
adjacent sectors are then averaged to generate timing logic to satisfy the voltage demand.

86
Finally, a gate logic block is used to compare the voltage vector timing sequences with
the ramp generator to create pulses for the inverter IGBTs.

V2

VS
VS2

VS1
δ V1
Figure B-10: Vs decomposed into adjacent sectors

The mathematical backbone of SVM, specifically input references and timing


calculations, may vary depending on the level of model detail to the inverter which it is
applied to [68],[69],[70]. The aforementioned technique only transforms the voltage
references into the stationary reference frame, ultimately calculating pulse waveforms for
a switching model. Specifically when using average or fast average inverter models, the
α -representation of the reference voltages are further derived into modulation indices
and normalized to the DC-link voltage before setting up the axes used in Figure B-9.
Such a generalization is possible given that the DC voltage changes slowly with respect
to the switching frequency. The remaining timing pulse derivation is then based on the
modulation indices in lieu of the former method: decomposing the instantaneous voltage
vector into its adjacent vector components. For a more in depth analyses refer to
[38],[65].

87
APPENDIX C
VM CURRENT CONTROL CONCEPT
C.1 DERIVATION
The following derivation (C.1) through (C.9) was implemented in the MATLAB
script at the end of Appendix C in order to prove the VM PHIL Current Flow Concept.
Figure C-1 is a reproduction of Figure 3-7 for convenience. It represents the single-phase
equivalent circuit of two converters and the coupling network, while Table 1 and Table 2
provide numerical values for the parameters. Furthermore, Table 10 gives multiple script
results for various inputs.

ΔVeq=Zeq*iVSD

iVSD ΔVAMP ΔVT ΔVVSD


+ +
X’AMP XT XVSD
VAMP VLOW VPCC VVSD
- -

Figure C-1: Equivalent circuit of coupling network, mesh analysis shown

First, (C.1) decomposes the equivalent impedance of (3.5) into the resistive and reactive
components, and then solves for the voltage drop across the network, ΔVeq, by
multiplying by the current out of the VSD, IVSD.

Veq  I VSD 0  jX eq  (C.1)

The voltage loop equations for the right and left loops shown in Figure C-1 are shown in
(C.2) and (C.3), respectively; note that in (C.3) the phasor angle at the point of common
coupling is set to zero.
VVSD  VVSD  VPCC (C.2)

VPCC  VPCC 0  V AMP  VT  V AMP (C.3)

88
By substituting (C.3) into (C.2) and expanding to phasor form one obtains (C.4). Next,
the equation of (C.4) is broken into the real and imaginary components as shown in (C.5).

VVSD VSD  VVSD  VSD  VT  VT  V AMP  AMP  V AMP  AMP (C.4)

VVSD   jVVSD  
(C.5)
VVSD  VT  V AMP  V AMP   jVVSD  VT  V AMP  V AMP 

Next, the voltage at the PCC (C.3) is broken into real and imaginary; then the imaginary
components are extracted into an equivalent equation and solved for the imaginary
voltage contribution from the amplifier, shown in (C.6). The result of (C.6) is then
inserted into the imaginary contribution of (C.5) to solve for the VSD imaginary voltage
as in (C.7).
jV AMP   j V AMP  VT  (C.6)

j VVSD   j VVSD  VT  V AMP  V AMP  (C.7)


Now that both the phasor magnitude and the imaginary components of the VSD voltage
are known the real contribution can be solved for as shown in (C.8). Finally the real
components of (C.5) are equated and the real contribution of the VSD voltage is solved
for, (C.9). From this point all the real and imaginary contributions necessary to compute
the phasor voltage drops of VAMP, VLOW, VPCC, and VVSD are known; and serve as the script
output.

VVSD   VVSD  VVSD  (C.8)


2 2

V AMP   VVSD  VVSD  VT  V AMP  (C.9)

89
C.2 MATLAB SCRIPT
%clc;clear all; I_pu_input=1; I_phi=0; V_pu_DURIP=1; ;f=20;
%"insert file name here to run";

% EXAMPLE
% clc;clear all; I_pu_input=1; I_phi=0; V_pu_DURIP=1/3;f=60/3;appendix_POC_script

%Line parameters and constants


w = 2*pi*f;
n = 480/208;
Sb = 45000;
St = Sb;
Vb = 480/sqrt(3);
Zb = Vb^2/Sb;
Rline = 0;
Lp = 0.0006;
Xp = w*Lp;
Xp_prime= Xp*n^2;
Ld = .0024;
Xd = w*Ld;
Xt = 0.0518;
Z_ohm = Xt*Zb;
Zapp = Rline+j*(Xp_prime+Z_ohm+1*Xd);

%Parsing Input
Id_rated= 37.2;
Id = -1*Id_rated*I_pu_input;
Vd_mag = Vb*V_pu_DURIP;
Id_rect = Id*[cosd(I_phi),sind(I_phi)];
Id_rect = Id_rect(:,1)+j*Id_rect(:,2);

%Impedance Voltage Drops


V_Xd = Id_rect*(0+j*Xd);
V_Xt = Id_rect*(0+j*Z_ohm);
V_Xp = Id_rect*(0+j*Xp_prime);

Vp_imag = -imag(V_Xp) - imag(V_Xt);


Vd_imag = Vp_imag + imag(V_Xd + V_Xt + V_Xp);

Vd_real = sqrt(Vd_mag^2 - Vd_imag^2);


Vp_real = Vd_real - real(V_Xd + V_Xt + V_Xp);

Vd = Vd_real + j*Vd_imag;
Vp = Vp_real + j*Vp_imag;

disp(sprintf('%s','RECT: Transformer Side of DURIP Sine Filter as Reference Point'))


disp(sprintf('%5.0f %5.0f',abs(Vp ),angle(Vp )*180/pi))
disp(sprintf('%5.0f %5.0f',abs(Vp +V_Xp ),angle(Vp +V_Xp )*180/pi))
disp(sprintf('%5.0f %5.0f',abs(Vp +V_Xp +V_Xt ),angle(Vp +V_Xp +V_Xt )*180/pi))
disp(sprintf('%5.0f %5.0f',abs(Vp +V_Xp +V_Xt +V_Xd),angle(Vp +V_Xp +V_Xt +V_Xd)*180/pi))

90
C.3 SCRIPT RESULTS
Table 10 organizes the script results for consistent VSD excitation
(160VLL, 20Hz) into four categories for analysis: strictly real and reactive power flow,
both, and reverse power flow. Maximum current is requested for all cases to exploit the
distinction between voltage potentials. Active current is requested by removing the angle
offset between current and voltage; zero degree phase shift (1st column of voltage
potential results). Notice the voltage potentials all have the same magnitude, but varying
angles; thus verifying that active current (and ultimately active power draw) is
independently controlled via excitation angle. Likewise, reactive current control via
magnitude differences is shown. Specifically, as the measurement point approaches the
VSD, the magnitude increases. Such should be intuitive as current flows from a higher to
lesser voltage potential, therefore to act as a sink the amplifier needs a lower voltage.
Note that for this body of work the direction of current flow is not of primary concern
since the AFE provides bidirectional power flow capabilities. The impedance networks
voltage drop could have been added to the amplifier references (instead of subtracted) to
create reverse power flow. Next, a hybrid case is shown depicting an equal amount of
reactive and active current. Phase and magnitude variation between the four potentials
maintains the same behavior. To emulate reverse power flow either the current magnitude
or phase was negated, as expected magnitudes decrease as potentials move from the
amplifier to the VSD. Phase differences between converters follow the behavior defined
by the current magnitude’s polarity. Finally, note that VPCC has no polar angle for any
case, as it is the zero angle reference.

91
Table 10: Script results proving current flow concept
Active Reactive Both Reverse Power Flow
Excitation
f 20 Hz
frequency
VSD
voltage VVSD 0.333 p.u., 160 VLL, (92VLN)
applied
Commanded
current I VSD 1.0 p.u., 37.2 A -1.0 p.u., 37.2 A
magnitude
Commanded
current  I 0° 90° 45° -45° 0° 90° 45°
phase
V AMP  AMP 93 11 63 0 72 10 114 7 93   11 122 0 114   7

LN - voltage VLOW  LOW 92 2 78 0 82 2 102 1 92   2 107 0 102   1
potentials VPCC  PCC 92 0 81 0 84 0 100 0 92 0 104 0 100 0
VVSD VSD 92   7 92 0 92   5 92   5 92 7 92 0 92 5

92
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BIOGRAPHICAL SKETCH
Fletcher Fleming (IEEE Student Member since 2004) was born in Milton, Florida
on July 24, 1985. His home town is Crestview, Florida. He received B.S. degrees in
electrical engineering and computer engineering in December 2007 from Florida State
University, in Tallahassee, Florida, U.S. He is currently pursuing a MS/PhD in the school
Electrical and Computer Engineering at Florida State University. Since January 2008, he
has been working as a graduate research assistant in the area of motor drives and power
and control systems under Dr. Chris S. Edrington and Dr. Mischa Steurer at the Center
for Advanced Power Systems.

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PUBLICATION LIST
(1) R. Bennett, C. S. Edrington, F. Fleming, “Application of a maximum torque per
ampere control strategy for DSRM drives,” Vehicle Power and Propulsion Conference,
September 2008, pp. 1-6

(2) F. Fleming, C. S. Edrington, R. Bennett, “Evaluation of the failure modes in a reduced


parts converter for switched reluctance drives,” Vehicle Power and Propulsion
Conference, September 2008, pp. 1-6

(3) E. El-Kharashi, C. S. Edrington, F. Fleming, R. Bennett, “Turn-on and conduction


angle selection for a disk-type rotor SRM,” 34th Annual Conference of IEEE Industrial
Electronics, November 2008, pp.1433-1438

(4) F. Fleming, C. S. Edrington, M. Steurer, O. Vodyakho, “Development and


Implementation of a 25 kW Virtual Induction Machine Test Bed Utilizing the
Power-Hardware-in-the-Loop Concept,” International Electric Machines and Drives
Conference, May 2009, pp. 1161-1166

(5) F. Fleming, C. S. Edrington, M. Steurer, O. Vodyakho, “Development and


Implementation of a 25 kVA Virtual Machine Test Bed Utilizing the
Power-Hardware-in-the-Loop Concept,” Grand Challenges in Modeling and Simulation
Conference, 2009

(6) F. Fleming, O. Vodyakho, C. S. Edrington, M. Steurer, S. Azongha, M.


Krishnamurthy, “Influence of DC-Link Fluctutations on Three-Phase Induction Motor
Drives,” Vehicle Power and Propulsion Conference, September 2009, pp. 748-753

(7) C. S. Edrington, O. Vodyakho, M. Steurer, S. Azongha, F. Fleming, M.


Krishnamurthy, “Power Semiconductor loss evaluation in voltage source IGBT
converters for three-phase Induction Motor Drives,” Vehicle Power and Propulsion
Conference, September 2009, pp 1434-1439

(8) O. Vodyahko, C. S. Edrington, M. Steurer, S. Azongha, F. Fleming, “Synchronization


of Three-Phase Converters and Virtual Microgrid Implementation Utilizing the Power-
Hardware-in-the-Loop Concept,” IEEE 25th Annual Applied Power Electronics
Conference and Exposition, February 2010, pp. 216-222

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