PART – A
4. What is the maximum size of the address space generated in a processor with has 32 bit
address?
Ans:
The maximum size of the address space generated in a processor with has 32 bit
address = 232 = 4 Giga Locations.
5. What will be the number of address and data lines required for a 512K X 8 memory
system?
Ans:
No. of address lines = 19
No. of data lines = 8
7. How many memory chips are required to construct 8M X 32 memory using 512K X 8
chip?
Ans:
No. of Memory Chips required = (8M X 32) / (512 X 8) = 64
8. How many 128 X 8 RAM chips are needed to provide a memory capacity of 4K bytes?
Ans:
No. of Memory Chips required = (4096 X 8) / (128 X 8) = 32
9. An application program in a computer with cache uses 1400 instruction fetch from
cache and 100 from main memory. What is hit ratio?
Ans:
Hit Ratio = No. of Instruction fetch from cache / Total no. of instructions
= 1400 / 1500 = 93.333%
10. Show how the virtual address translation divides the 32bit address with page size 16K.
Ans:
Page size = 16K No. of address bits = 14
No. of bits for page numbers = 32 – 14 = 18 bits
18 14
11. Explain the two possible address assignment for bytes with a word of 32bits.
Ans:
Big-endian: The lower address is assigned to the most significant part of the word.
Little-endian: The Lower address is assigned to the least significant part of the word.
0 0 1 2 3 0 3 2 1 0
4 4 5 6 7 4 7 6 5 4
. .
. .
. .
k k k
2k-4 2k-4 2k-3 2k-2 2k-1 2 -4 2 -1 2 -2 2k-3 2k-4
16. Give the expression for average access time for a memory system with cache.
Ans:
The effective access time Tav = hc + (1 – h)M
where c be the access time to cache
M be the access time of Main memory
h be the hit ratio
18. Compute the number of external pins required for 1K X 1 memory chip.
Ans:
No. of external pins required = 15 (Address Lines – 10, Data Line – 1, Control Line –
2[R/W & CS], power and ground – 2)
20. What is SIMM & DIMM? What are the advantages of SIMM & DIMM?
Ans:
SIMM – Single Inline Memory Module
DIMM – Dual Inline Memory Module
The memory chips are mounted on a small PCB which in turn plugs into socket on
the mother board, such memory modules are called SIMM & DIMM
SIMM uses 100 pin & DIMM uses 168 pin socket
Advantages:
Modules occupy less motherboard space
allow easy upgradation
allow each troubleshooting and maintenance
5. Give the classification of Read only memory technologies and explain each.
Ans:
Classification of Read Only Memory (ROM)
a. ROM (Read Only Memory)
b. PROM (Programmable Read Only Memory)
c. EPROM (Erasable Programmable Read Only Memory)
d. EEPROM (Electrical Erasable Programmable Read Only Memory)
e. FLASH Memory
To avoid this access time and degradation of performance, recently translated virtual page and
its corresponding physical page is kept in a buffer and this buffer is called Translation Look
aside Buffer (TLB)
When a processor i.e. MMU finds the page table entries in TLB, it does not have to access the
page table and saves substantial access time.
8. List three secondary storage devices and briefly explain Magnetic Hard Disk.
Ans:
Secondary Storage Devices
- A huge amount of cost effective storage is provided by secondary storage
devices.
- Popular secondary storage devices.
o Magnetic Hard Disk
o Magnetic Tape
o Optical Disks
DVD – ROM, DVD – R, DVD – R/W are identical to CD – ROM, CD –R, CD – R/W
The logic circuit of 1 bit Associative memory is shown in diagram. This comprises
The cell is D Flip Flop for data storage
The match circuit (exclusive Nor gate) for comparing the F/F content to an external
data bit D
Circuit for reading (Select)
Circuit for writing (WE & Select)
The results of comparison appears on match output M when M = 1 denotes match and
M = 0 denotes no match.
The cell is select4ed by addressed for both read and write operation by setting select
line S = 1
New data is written into the cell by setting WE = 1 which in turn enables D F/F clock
input
The stored data can be read out via Q line
The mask control line MK is activated (MK = 1) to force the match line M to 0
independent of the data stored in the D F/F
MK also disables the input circuit of F/F by forcing CK = 1
Disadvantages
o The cell of this type needs about 10 transistors for more than single transistor
required for dynamic ram.
o Hence the associative memory is costly, large associative memory are rarely used
outside cache.