(i) Common signal, which are used in minimum as well as maximum mode
(ii) Signal for minimum mode
(iii) Signals for maximum mode.
• A HIGH on HOLD pin indicates that another master (DMA) is requesting to take over the system
bus.
• On receiving HOLD signal processor outputs HLDA signal HIGH as an acknowledgment.
• At the same time, processor tristates the system bus.
• A low on HOLD gives the system bus control back to the processor. Processor then outputs low
signal on HLDA.
When MN/MX(bar) low 8086 is in maximum When MN/MX(bar) high 8086 is in minimum
mode. mode.
In maximum mode a bus controller is required to In minimum mode direct RD WR signals can be
produce control signals. This bus controller used. No bus controller required. A simple
produces MEMRDC, MEMWRC, IORDC, IOWRC, demultiplexer would do the job. of producing
ALE, DEN, DT/R control signals. the control signals. This demultiplexer
produces MEMRD, MEMWR, IORD, IOWR
control signals.