VFD Volume 1 PDF

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CUSTOMERTRAININGMANTTAL
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Safety Symbol Legend
Commands to an operatingproceedure,
attention practice,
WARNING conditionor statement,which,if strictlyobserved,could
resultin personalinjuryor death.
CommandsAttentionto an operatingproceedure, practice,

CAUTION condition or statement, could
which,if notstrictlyobserved,
result in damageto or destructionof equipment.
Commandsattentionto an essentialoperatingor main-

NOTE: condition,or statementthat must be
tenanceprocedure,
highlighted.
\-
CAUTION 1. Do not attemptto repairPrintedCircuitBoards(PCB)at site.

Pleasesend them to supplierr'swork for trouble shooting
/Repair.
2. Do not attemptto replacleThyristorin a powermodulewhere

the thyristorsare in series.The Thyristorshaveto be checked
for IRR and QRR bandmatching.
L
lnstructions
LOAD COMMUTATEDINVERTER
AC ADJUSTABLE SPEED DRIVES

AC ADJUSTABLESPEED DRIVES
NOTE:
TYa't'n'ntY
Thls ls a standard nrf"r*"{ Manualcoverlng all the Load Commutated
Invenor drlves supplled by BHEL Only such parts are relenant as
appllcable for this prclect. Please refer the drive Schematlc dlagram
for the same
ff
:
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Table of contents
ChapterI 1-1
1-1 BASIC LCI SYSTEM 1-1
1-2 BASIC POWER CONVERTEROPERAT]ON 1-2
1-3 LCI CONTROL 1-6
1-3.1 BasicOperation 1-6
1-3.2 Starting/Force Modes

Commutated 1-6
1-3.3 Mode
Self Commutated 1-8
1-4, TWELVE.PULSEOPERA]]ON 1-11
1-5. SEFUESTWELVE- PUISE OPEBAT1ON

(Option). 1-11
Chapter2
Power Equipment 2-1

,
2-1 EQUIPMENT OP'NONS 2-1
2-1.1 1.2 l$/ Air Cooled Bridge 2-1
?-1.2 2 l(/ Air Cooled Medium voltage Bridge 2-2
2-1.3 4 l(/ Air Cooled Medium voltage Bridge 2-2
2.1.4 2l<\ll4l{l Water Cooled Medium Voltage Bridge 2-5
2-2 TI-IYRISTOR MODULES 2-5
\ 2-2.1 Air Cooled MVB Thyristor Modules 2-5
2-2.2 Water Cooled MVB Thyrlstor Modules 2-12
2-3 CIATE DRIVER TRANSFORMER 2-12
2-4 GATE DRIVER CARD (HPTI$ 2-13
2-5 VOLTAGE FEEDBACK ATTENUATOR CARD 2-1s
2-6 AIR COOLED MVB SIGNAL DISTFUBUNON 2-14

BOARD{XTFH}
2-7 WATER COOLED SIGNAL DISTRIBUTIONBOARD 2-14
(xDcK)
2-8 P(CITER VOLTAGE CONTFOI LER (EVC) 2-16
Chapter3
Control ElectronicsPanel 3-1
3-1 INTRODUCTION 3-1
3-2 ELECITION|CSMODULE(LCG,LCL) 3-1
3-3 DESCRP'NON
CONTROLOPERATIONAL 3-3
3-3.1 Basic principles 3-3
3-3.2 Pulse Locked LooP OPeration 3-7
3-3.3 ElectronicsModule Printed Wiring Board (PWB) Descriptions 3-7
3-3.4 Microprocessor- HMPC{DMPB 3-7
3-3.5 ROM DMPB

Electrically-alterable, 3-8
3-3.6 LCI Processor Exciter Board - HLCB 3-8
3-3.7 Analog/Digital Intedace Card HAIA 3-10
3-3.8 Flux lntegrators- NLIB 3-1s
3-3.8.1 VOLTAGE INTEGRATORS 3-15
3-3.8.2 UNE / LOAD CT RECEVERS 3-15
3-3.8.3 VOLTMETER DRIVER 3-18
3-3.8.4 OVER VOLTAGE PROTECTION 3-18
3-3.8.5 UNDER VOLTAGE SENSING 3-18
3-3.8.6 SUPPRESSION 3-18
3-3.8.7 CURRENT METER DRIVER 3-18

3-3.9 Gating ReferenceBoard - NSFC 3-20
3-3.9.1 R BUS INTERFACE 3-20
3-3.9.2 FIFUNGMASK LArcH 3-20
3-3.9.3 GATE DRIVERS 3-20
3.3.9.4 PULSE TRAIN GENERA'I'ION 3-21
3-3.9.5 BUFFERS 3-21
3.3.9.6 UNE.TO.UNE VOLTAGE SIGNAL CONDITIONS 3-21
3.3,9,7 CELL STATE SENSORS 3-21
3-3.9.8 D-C UNK VOLTS 3-21
3-3.10 Field ExcitationControl Board - NSFE 3-22
3-3.10.1 R BUS INTERFACE 3-24

.
3-3.10.2 FIRING MASK I.ATCH 3-24
3-3.10.3 GATE DRIVERS 3-24
3-3,10.4 CURRENT FEEDBACK CONDITIONING 3-24
3-3.10.5 CURRENT UNBAISNCE DETECNON 3-24
3-3.11 AI{ALOG LCI BOARD - NLCB 3-26
3-3.11.1. SPEED FEEDBACK 3-26
3-3.11.2 DfiERNAL SPEED TIEFERENCE 3-26
3-3.11.3 TEST SPEED REFERENCE 3-27
3-3.1.I.4 TORQUE REFERENGESIGNAL CONDI]]ONING 3-27
3-3.11.5 SELF TEST FEATURES 3-27
3_3.11.6 +20 MA S|GNAL DRIVEFIS 3-27
3.3.11.7 GROUND FAULT DETECTOR 3-27
3-3.11.8 POWER APPUED RESET 3-27
3-3.11,9 FAULT REI.AY DFUVEF€ 3-27
3-3.11.10 HOFBEPOVI/ERMETER DRIVER 3-28
3-3..I1,11 CONTINUITVDETECT]ONCIFCUITS 3-28
ilf
3-3.11.12TEST SWTCH 3-28
3-3.11..13 FiESTARTUPON POWER LOSS 3-28
3.4 RELAY DFUVER BOARD - HRDA 3-30
3.5 INPUT SIGNAL CONDITIONING- HISA 3-31
3.6 TACHOMETER INTERFACE- HTCA 3-31
3-6.1 Tachometer Power Supply 3-31
3-6.2 TachometerInput Conditioning 3-31
3-6.3 Position Counter 3-32
3-6.4 High Accuracy Speed Circuit 3-32
3-7 SLAVE BRIDGE CURRENT INTERFACE= NBIE 3-33
3-8 D|SP|-AY MODULE (LDM) 3-34
3-s l/o MoDULE(tOM) 3-3s

3-10 STGNAL TSOLAT]ONMODULE(StM) 3-36
Chapter4
Software Tuneup and Public Variables 4-1
+1 SOFTWARETUNEUP CONSTANTS +1
+2 DESCRIPT]ONOF PUBUC VARIABLES +30
Chapter5
Diagnostic Monitor Specifications c-l
5-1 INTRODUCTION 5-1
5-2 OPERAT'ING INSTRUCTIONS s-2

5-2.1 General lnforination 5-2
5-2.2 TemrinalFormat 5-3
5-2.3 Power-upStafus fr4essages 5-3
IV
5-2.4 Editing Functions s-3
5-2.5 Command Syntax 5-5
5-2.6 ProtectedCommands 5-6
5-2.7 Help 5-6
5-3 MONITOR COMMANDS 5-6
s-3.1 ASStcN 5-7
5-3.2 Display 5-11
'3.3 HELP s- l2
s-3.4 PASSCODE 5-13
s-3.s QUIT s- 13
5-3.6 RESTART 5-13
5.3.7 SYMBOLS 5-14
5.3.8 TERMINAL 5-14
5-3.9 VERIFY 5-15
5-4 TUNEUP ;5'16
5.4.1 APPLY 5-17
5.4,2 HELP 5-17
s-4.3 MODTFY 5-17
5-4.4 MODIFY REFERENCE 5-18
s-4.s QU|T 5-20
5.4.6 REMOVE *20
5-4.7 SETPASSCODE 5-20
5-4,8 SAVE 5-20
s-4.9 SIAVE D TO A (SDA) 5-21
5.4.10 TUNEUP SYMBOLS s-22

5.4.11 TUNEUP 5-22
5.4.12 ENGINEERING 5-23
V
s-4.13 D|SPIAY 5-23
5.4,14 HELP 5-24
'
5-4.15 TNPUT 5-24
s-4.16 PUT 5-24
5-4.17 MOVE 5-25
5.4.18 OUTPUT 5-25
s-4.19 QUIT 5-25
5.4.20 SUBSTITUTE s-26

LOADING DISPI-AY MESSAGES s-26
CHAPTER6
INSUTATIONAND STARTUPGUIDE 6-1
6-1 PRELIMINAFIY CONSIDERATIONS 6-1

6-2 MEGGER TESTS 6-1
6-2.1 Air cooled bridge 6-1
6-2.2 Water cooled bridge 6-1
6-2.3 Meggeirpower busses 6-2
6-3 CHECK CONNNUITY ACROSS CELLS 6-2
6-4 APPLY AUXUAFV POWER 6-2
6.5 CHECK SIGNAL INPUT POWER SUPPLY d2
6-6 CHECK ELrcTFilSNICS POWER SUPPLY 6-3
6-7 CHECK ClATlNc POWER SUPPLY 6-3
6-8 ELECTFIONICS MODULE INITIALIZAT'ION 6-3
6-9 SET UP DOOR PRINTER 6-4
6-10 PERFORM CONTHOL SELF TEST 6-4
6-11 SET AD.'USTMENT POTS PER ELEMENTARY 6-4
6.12 CHECK BRIDGE CURRENT FEEDBACK CAUBRA. 6-4
TION
6-12.1 Air cooled bridge 6-4

6-12.2 Water cooled bridge
VI
6-4
6-13 PERFORM SCR GATE TESTS 6-5
6-14 SOUrcE NO LOAD FUII VOLTAGE TESTS 6-5
6-14.1 Sourcevoltagesignal phasingand balancing: 6-5
6-14.2 Set source under voltage detection: 6-6
6-14.3 Set source overvoltagedetection: 6-6
6-14.4 Source slave bridgephasing(series12 pulse only): 6-7
6-15 LOAD TESTS USING VOLTAGE SIGNALS FROM 6-7

SOUFICE SIDE BFUDGE
6-15.1 Load voltage signal phasing and balance: 6-7
6-15.2 Set load overvoltagedetection: 6-8
6-15.3 Set motor speed and voltage indications: 6-8
6-15.4 Motor speed signal: 6-8
6-15.5 Speed Indications: 6-8
6-15.6 Motor voltage indication: : 6-8
6-15.7 Set Overspeed: 6-9
6-16 F(CITA]ION TESTS 6-9
6-16.1 Phase SequenceCheck: 6-9
6-16.2 EVC Power Test: 6-9
6-17 CRO\AAAR TEST 6-10
6.18 FIUN MOTOR UNCOUPI-ED: 6-14
6-18.1 Considerations: 6-14
6-18.? Test Connections: 6-14
6-18.3 Start and Run Motor: 6-15
6-18.4 Motor Starting Notes: 6-15
O-fe.S Tachometer Set Up (For Drive with Tach Only): 6-16
6-18.6 Speed Range Test: 6-17
6-18.7 Speed Ramp Test: 6-17
vtl
€
6-18.8 RemoteOperation: sl8

6-18.9 12 PulseCheckOut: 6-18
6-19 RUN WITH MOTOR COUPLED 6-18
6-19.1 TestConnections:1 6-18
6-19.2 StartingTune-up: 6-19
6-19.3 Drivewithouttach: 6-20
6-19.4 Drivewith tach: 6-20
6-19.5 CurrentRegulatorTunrup:
ForcedCommutation 6-20
6-19.6 MotorFlux FeedbackcalibrationCheck: 6-21

,!
6-19.7 FluxRegulatorResponse: 6-22
6-19.8 SpeedRegulatorResponse: 6-24 {

6-26 {
6-19.9 Load lnvertionUmit Tune Up:
"1
&19.10 Source-side
Une lmpedance: 6-28
6 - 1 9 . 1 1 DualChannelTests: 6-30
{.
6 - 1 9 . 1 2 SourceMinimumAngleControl: 6-31
6 - 1 9 . 1 3 CalibratePower Meter/ RemotePowersignal: 6-31 G
{
6 - 1 9 . 1 4 CalibratePanelAmmeter/ RemoteAmpereSignal: 6-32
CHAPTER7
DIAGNOSTICAT{DTROUBLESHOOTING 7-1
7-1 SELF TEST 7-1
7-'1.1 Basic Structure 7-1
7-1.1.1 PWB - specifictesb 7-1
7-1.1,2 PairedPWB Tests 7-1
7-1.1.3 Panel-LevelTests 7-1
7-1.2 Executing the Tests 7-3
7-1.3 Diagnosingfailures 7-3
v-1.4 Descriptionof Tests. 7-4
vill
l1 ?
I
1 3 '
l
ii i
e
7.2 GATE - TEST. MODE 7-32
7-2.1 Generai 7-32
7-2.2 Getting Into Gate-Test-Mode 7-33
7-2.3 Gate-Test-ModeCheckout 7-33
CHAPTER8
LCI regulatorcontrol biock diagrams 8-1
to
Standard LCI AC and DC field 8-19
q
CHAPTER
'2 PA6ES
C0r1 PENDtunoF ALARtls f rauns
4+tf conp€rlD/Lct REv 0 !- Dr ' o+f otf zoo{
IX
Figure3-OLCG ControlElectonics Interface 3-2
Figure3-1 LCLCorrtrolElectronicsInterface 3-3
Figure3-2 LCG ElectronicsModule(SEM)Card and Connectorl-ayout 3-4
Figure3-3 LCL ElectronicsModule(MEM)Card/ConnectorLayout 3-5
Figure3-4 ElecbonicsModuleInpuVOuput 3-6
Figure3-5 ElectronicsModuleBlockDiagram 3-9
Figure3-6 LCI SystemRegulatorBlockDiagram 3-11
Figure3-7 Flux WaveZero Crossing 3,16
Figure 3-8 Analog Typical Waveforms. 3-23
Figure6-1 FiringSignaland CurrentSignals. 6-13
Figure6-2 IFBduringSEGFIRE. 6-21
Figure6-3CRALPH1/2TUN E-UP. 6-22
Figure 6-4 Motor Une to Une Voltage Waveform. 6-23
Figure6-5 ldealFluxWave 6-26
Figure6-6 Flux RegulatorResponse. 6-27
Figure6-7 Speed RegulatorResponse. 6-27
Figure6-8 LoadSide FAI-AP 6-?9
Figure6-9 SourceSide FiringAngle. 6-30
Figure7-1 FidngAngle Limits 7-34

L- Figure7-2 SourceFiring- FullAdvance 7-35
Figure 7-3 Typical Firing Gate PulseTrains 7-37
Figure7-Afypical FiringPulse(CellGateCunent Pulse) 7-37
Figure7-5 Softwarelnterrupts- FullAdvance(Source) 7-38
LCI regulator control block diagrams 8-1

to
8-19
XI
LOADCOMIIUTATEDINVERTER BHEL
Chapter 1
1.1 BASIC LCI SYSTEM
The Load commutatedInverter(Lcl) is static, adjustablefrequencydrive

system that controlsa synchronousmachineform near to rated speed.
The basic system consistsof line commutated,phase controlledthyristor
converterthat'feeds a load commutatedthyristor convertorthrough a
dc link reactor, Fig 1.1 is a simpliliedone-line diagram of a single
channel LGl. The transformerprovides isolation from the ac system
bus anil provides the conect voltage at the terminals of the rectifier.
Also, the internal impedanceof the transformerlimits the magnitude
of any downstreambus faults.
The rectifier is a thyristor bridge whose gating is controlledto produce

a variable dc voltage at its output. The output of the rectifier is
fed throughthe dc link reactor,whose functionis to smooththe current
and keep it continuousover the operating range of the system.
The dc link reac'toroutput is then fed into the inverter bridge, which
providesvariablefrequencyac the stator terminalsof the synchronous
machine. The inverter bridge and the rectifier bridge use the same
powerhardwareand are controlledby microprocessor- basedelectronics.
Althoughthe bridgesare labled "rectifier"and "inverter," lt is possible
for their roles and hence power flow to reverse. In this case, the
synchronousmachinewould be braked by pumping its energy back
into the ac line. A more general nomenclatureis to call the line
bridge the source converter,and to call the machineside bridge the
load converter.
EXCITATION
VOLTAGE
CONTROLLER
1.1 mpllfled
1-1
LOADCOMMUTATEDINVERTER BHEL
The synchronousmotor field is usually excited by a brushless exciter
coupled to the motor shaft. The brushiess exciter is a wound rotor
inductionmachinewhose rotor voltage is rectifiedto supply field current
to the synchronousmachine.
The stator voltage for the brushlessexciter is supplied from a static

excitationvotlage controllerincluded as part of the LCI control panel.
This controller is gated/controlledentirely by the LCI electronic control
module. The LGI controlsthe excitationto producethe requiredmachine
flux and provides field over/under current protection.
A more detaileddiagramof an LCI is shown in Figure 1-2. As shown

in this figure, the electroniccontrolreceivesthe followingsignal inputs:
1. Attenuatedline and load bus voltage signals.
2. Attenuatedline and load currentsignalsfrom cunent transformers.
3. Speed referencesignal.
4. Process commandssuch as stop, start, etc.
The attenuatedbus voltagesignalsare used by the controlto synchronize

thyristorfiring with the line and load voltages,to providevoltagefeedback,
and over/undervoltage detection. The attenuatedcurrent signals are
used for regulatorcurrentfeedback,electronicover-current detection,and
softrruare-implemented fault detection.
The el€ctroniccontrol evaluatesthe process commandsand internal

status signalsto determinewhetherthe drive should be in a stopped,
started,alarmed,
or faultedcondition.lf in a startedcondition,the electronics
provides gate signals to control the thyristor bridges and the excitation
voltage controller. These signals are low level and are conditioned
in the power bridge circuitryto providethe necessaryisolationand
power level.
1.2 BASIC POWER CONVERTEROPERATION
The power bridgessh pulse,doubleway types and the thyristorbridge

legs 'fire' in the order that are numbered in figure 1.2 and shown
in figure 1.3.
The source convertor cunent is succossfullytrpnsfered from one log

to the next by the synchronousmachine stator voltages.
The process of switching machine/convertercunent from one leg to

the next is illustatedin Figure 1.4 The principlesillustratedhere apply
to rectifier bridge as well as to inverter bridge. This phase-controlled
switchingis accomplished by usingthe followingtwqthyristorcharacteristics:
(1) when the voltage across the thyristor is positive,it can be kiggered
into cohduction.
1-2
LOADCOMMUTATEDINVERTER B}IEL
SOURCE DC UNK LOAD

BRIDGE REACTOR BRIDGE
SYI,ICHRONOUS
MACHINE
Ac Ja
SOURCE
VOLTAGI
3 PHASE
AC PO$ER
CURR FDBK CURR FDBK
I. SPEED
REFERENCE
PROCESS PROCESSOUTPUTS
INPUlS (TO RELAYS.LIGHT,ETC)
(REI-AYS,PUSHBOTTONS.
ETC)
Flgure 1-2 LCI Drlve
1-3
FIREl FIRE3 FR
I E5 F I R E7
!r^'--lt
t i
t i
l
I a 7
cJl_ _
C O N D U C T SCONDU
CONDUCTSC O N D U C T S
6 2 4 6
- C$LUIn T c C ON DUCTS CONDUCTS

CONDUCTS
II +
t ll ll
I
F IR E2
l
F IRE4 FIRE6
l
FIRE2
l
Flgure 1-3 Thyrlster Brldge Leg Conductlon Sequence
and (2) it will not permit currentflow in the reverse direc{ion. Thus
in an alternatingvoltagecircuit,thyristorcondcutionwil ceaseand reverse
voltage will begin to appear when the current becomes zero.
Current transfer must be completed before voltage cross-over with a

positivemargin angle. The angle must be long enough to allow the
previouslyconductingleg thyristorsto recover to their blocking state
beforefonrvardvoltageis applied. This is why the fundmentralcomponent
of current must lead the voltage,from an inverter/machineviewpoint.
Fromthe rectifier/sourceviewpoint, the fundamental componentof current
will atways lag the voltage; but for sucessfull commutation,the angle
cr=1800 -0=180-p-y must always be less than 18Oo. a practical
limit is 1550' Conespondingly, a practicalminimun value for p for
the inverter bridge is 25o.
The machine power-factorangle is thus always greater than zero'

of the synchronous
TheLCIcontrolsystemmustconformto the characteristics
machine operatingat leading power factor. A phasor diagram for
a synchronousmachine operatingat leading power factor is shown
in figure 1.5.
With a fixed amountof field excitation,the machinevoltagecharracteristic

is mainlya fucntionof the rotorfield EF,and the de-magnetizing
excitation,
action of direct-axiscurrent, This produces the loXlo voltage in
oppositionto the voltage producedby field excitation.
1-4
INVERTER
LOADCOMMUTATED BHEL
c-B(c M|NUSB)
L]NE TO NEUAAL
AND DC LINK VOLTAGES
7 =MARGINANGLE
COMMUTAT1ON
(CURRENT
TRANSFER)
BEGINS
MOTORCURRENT
1-5
LOAD COMMUTATEDINVERTER BHEL
Note that an increasein stator currentresultsin higher direct-axiscurrent,

which increase'loXlo. This in tum decreasethe machinevoftage Ee
availablefor commutation, therebyincreasingdisplacement angle 0. This
increasgof angle 0 furtherincreasesstatorcurrent,etc, until equilitbrium
is reached at new operating point.
{, ln actual practice,themachinefield in the speed range of approximately

O-lO%,andcontrolledto producea desiredprofileof machineflux higher
tl
speeds greaterthan 10% the LCI operatesin a flux regulatedmode
and adjuststhe outputs of its static voltage controller(EVC) to maintain
machine flux at the desired level.
1.3 LCt CONTROL
1.€.1 Baslc Operatlon
When operatingin any mode, the electroniccontrol must synchronize

firing of the source and load converterto the ac line and synchronous
machinebusvoltages,respectively. Theprimaryfeed-backfor accomplishing
this is the attenuatedbus-to-ground signalsfor both converters.attenuated
bus-to-ground voltagesare broughtintothe electroniccontroland combined
to produceline-to-lineanalogsfor bothconerters. Theseline-to-linevohages
are then integqated to obtain flux signals,the zero crossingsof these
signals are then integratedto obtain flux for both conveters. These
line-to-linevoltagesare used in the synchronization of the phase locked
loop for the firing controt of both sotlrce and load converters. At
low speed, before the phase locked loc,p is effective on load side,
the zero crossingmarks are used as a timing reference for firing
in force-commutated oPeration'
The source side conveterfor the LCI always line-commutated: i.e., the
ac line providesthe meansfor transfering conductionfrom one thyristor
to the next. The load side convertermay operateload (selfl commutated
or force commutated,dependingon motor speed and flux level.
As the synchronousmachinerotor (field) rotates,the near sinusoidally

shaped field flux cuts the stator windings, producinga set of three
sinusoidalvoltagesin the stator. Thesesinusoidalvoltagesare angularly
displacedby 120 electricaldegrees. The magnitudeof the counter
emf is proportionalto speed and field strengh. At low speeds, the
to commutate
inducedemf is insufficent thyristorsin the loadside converter.
In this mode, the load convertermust operate forced commutated'
1-3.2 Startlng/Force Commutated Modes
_ Force commutatedoperatiionis used when starting the synchronous

machinefrom zero or low speedand continuesuntil the machinecounter
emf is sufficientfor self commutation.ln forced commutatedoperation,
conductionof the load converteris stopped by phasing the source
converterto inversionlimit until the dc link (reactor)current is zero
as shown in figure 1-6. Thus the dc link current is chopped into
60 degree wide segmentsof motor frequency (angle)'
1-6
There are several modes of forced commutationinvolved in the starting

of the synchronousmotor,in tachtessLCI application,the startingcurrent
is the made large enoughto acceteratethe machineto 0.5H2 in one
or two inverter firings. This is opproximatlythe minimum frequency
at which the LCI can sense machineflux and begin to control torque
and speed.
When a start lrom standstill is initiated,the LCI applies fixed current

level at a fixe$ lrequencyto the stator of the motor. The frequency
is set by funeupSTIM and startingcurrentlevel set by tuneup CRSTART.
AXIS
DIRTCT
lp
loxno
QUADRATURE
Fr AXIS
Flgure 1€ LCI-DrlvenSynchronousMachlne Dlagram;LeadingPF
When the LCI controlsensesflux of sufficientmagnitude,it transitions

into the segmentfiring mode of forced commutatedoperation. In this
mode, inverterfiring is synchronizedto crossoversof the machineflux
and the machineis operatednear unity powerfactor to obtainmadmum
torque. lnverterfiring is adjustablein 30o steps or segmentsin this
operation. The speedregulatorbecomesactivein segmentfiring mode.
At approximatly2.5H2, the load phase locked loop is able tc lock
and inverterfidngresolutionincreasesto 0.35 degree. This ends segment
firing mode.
1-7
INVERTER
LOADCOMMUTATED BHEL
Forced commutated opeation continues until the synchronous machine

reaches a frequency whete its emf is suffcient to commutate the load
side converter. At this point the control transitions to self commutated
operation.
For LCI drives using a pulse tach for high starting torque applications,
the tach pulse are counted to keep track of the rotor position and
starting from standstill does not depend on zero crossings of motor
flux. ln this case the stator current is ramped up until shalt rotation
is detected. At that point cttrent is frozen and firing is based on
rotor position determined from the tach/counter. This continues for several
firings to insure the motor is rotating and then the speed regulator
is enabled. Stator current is then controlled by the speed regulator
to produce the torque required to accelerate the motor as required.
Force commutated operation continues until the motor cemf is sufficient
to commutate the load side converter.
1-3.3. Self Gommutated Mode
ln the self commutated mode, the machine must be operated at a

leading' power factor in order to be able to insure commutation of
the load converter. The electronic control acts to keep the machine
power factor, and therefore torque per ampere, as high as possible.
This accomplished by firing the load converter as close to inversion
of current from one cell to the next. The commutation time required
is a function of machine current, machine (commutating) inductance,
and the voltage difference between the lines involved. in the attempted
commutation.
For a given load current and machine inductance,a correspondingamount

of volt seconds is required for a successfull commutation. The control
reads the peak volt-secondsof the integratedline- to-line machine voltage
and machine current. The machine commutatinginductance is a constant
stored in the microprocessorsystem memory. Using the current and
inductance,the amount of commutationvolt-secondsrequired is calculated
by the microprocessor. Using this value of voh-seconds and the peak
volt-seconds of the previous flux wave, the latest possible time to fire
is calculated to give a specific margin after commutation is completed.
The relationship of the system voltages, currents and flux waves are
illustrated in figue 1-7.
"notch" identifiedin the A-C line-to-linevoltage is equal
The commutating
"bump" on the B-C voltage'
in amplitudeto the simultaneouscommutating
The corresponding notch in the A-B voltage (A and B are the two
lines which are commutatingtogether at this instant) is twice this ampllude'
notch area is twice the commutating inductance per phase times the
current. The voltage at the commutating point, where the lines are
temporarily connected by the thyristor legs, is practically zero during
commutation; the line-to-line voltage is only the fonrard voltage drops
of the conducting thYristor legs.
1-8
LOADCOIIMUTATEDINVERTER BHEL
tA l
+
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PHASE-ONOCCURS SIMULTANEOUSLY
WI1HFIRINGOF A NEWLOAD
LEGPAIR
TIJYRISTOR
LINK VOLTAGE
AT SOURCE FIRINGLE\EL REQUIRED
TH\RISTOR BRIDGE TO MAINTAINDESIRED
OUTPUT. UNK AND MOTORCURRENT.
INIERIINGTO
SHUTOFFCURRENT.
UNK
CURRENT
1-9
INVERTER
LOADCOMMUTATED BHEL
rotil r.rE-lE riAL

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Ffgurc 1-7 Load Voltage And Current
1-10
INVERTER
LOADCOMMUTATED BHEL
'seen" by the
At high load on the motor, the apparent power factor
power source increases. This is because the source converter firing
angle advances (is reduced)to obtain more current. The hormoniqs
in the voftage,dueto commutation
in the currentandthe resultanthormonics
'notching",will decrease.
The fundamentalcontrol statergy iS; To increase motor current in

responseto a load torque increase,the link d.c voltageon the source
side is increased,thereby raising motor cunent so as to keep motor
speed constant.
14 TWELVE.PULSEOPERATION
Twelve-pulseoperationis like two identical,separateslx pulse drives

operatingfrom commonsource at the same cunent and firing angle'
with the tiring reference angles shifted 30 degrees by the isolating
transformers.
The two motors are combinedinto one frame. This reducesthe motor
cost, includingisolation,and reducesthe torquepulsationamplitudewhile
raising the torque pulsationlrequency. This is achierredby separating
the stator winding into two identicalwindings,but isolatedand phase
shifted 30 degrees.
utilizinga commonmagneticframe,includinga common

This construction,
field, cause the load-sideconvertervoltage to be equal in amplitude
and frequencybetweenthe two drive channels. The transformerdesign
makes the source-sideconvertervoltage equal, but also 30 degrees
apart betweenthe two channels. lt is not necessarythat source-side
and load-sidevoltagesbe phase-shifted.The motor windingsare shifted
to obtain smoothertorque for equal cunent. The transformerwindings
are shifted to reduce harmonicdistortionon the power system and
raise the harmonicfrequencies.
lnter-channelcbmmunication allows one channelto be master and the

other the slave,which takes its torque referencefrom the.master. This
communication allows the two motor winding currentsto be balanced.
Thus the channels deliver equal power, take equal current, and fire
at the same relativefiring angle, this best utilizesthe motor and drive
capabilitiesand also minimizesthe harmonics presentin each six-pulse
channelcancel (Sth and 7th harmonics). Other higher-orderharmonics
also cancel, but their amplitudesare much smaller.
A twelve - pulse system also presentsthe capabilityof shutting down

one channelfor maintainance while the motor continuesto run on the
other channel (with reducedtorque and usually reducedspeed range).
when the out of service channel is ready for operation, it may be
returned to service without interruptingthe drive system'
1-11
\
INVERTER
LOADCOMMUTATED BHEL
1-s SERIES TWELVEfULSE OPERATION (Optlon).
Some drive configurations include series 12 pulse operation for the

source converter. This is done primarilyto reduce the harmonic distortion
imposed by the drive on the power system. Twelve-pulse operation
eliminates half the harmonics produced by six-pulse system starting with
the Sth and 7th harmonics. The twelve-pulse converter consists of
two identicalSCR bridges connected in series, each of which is operated
at roughly half of the motor voltage. The ac source for the two
bridges are displaced in phase by 30 degrees. The ac sources are
supplied from delta and wye transformer secondary windings to give
the required phase shift.
1-12
INVERTER
LOADCOMMUTATED BHEL
Chapter 2
POWER EQUIPMENT
2-1 Equlpmcnt Opllons
The power convertersmay be either of 1.2 l(V, 2l(/ or 4 l(/ bridge

construgtion.The 1.2 l(/ design uses 2 SCR's in series, 2 l(V uses
3 SCR's in series and 4 l(V uses 6 SCR's in series per leg' The
equipmentis supplied in air cooled design. Some of the desings
are available in Liquid (water) cooled also'
2-1.1 1.2 l(\/ Cooled Brldge
Each powerconverterconsistsof six thyristorleg modulesstackedvertically

as shown front-viewin Figure 2-1.
Each leg consistsof two thyristorsconnectedin series, mountedwithin

a heatsinkassembly. An R-C snubbernetwork is also containedin
the leg module box.
Five attenuatedvoltage signals are derived from the bridge. Note that
there is no attenuatorconnectionto leg module 6.
The attenuatedvoltagesignalsare combinedin the electronicsmodule

to produce scaled ac line-to-lineand rectified dc bus voltages.
The pulse transformerdelivers a cunent pulse to the thyristor(s)in

the leg. The red light on the card front is illumintedif the HPTF
is delivgringgate pulses. The neon lamp across the cell goes out
if the cell shorts.
The burden resistor for the current transformersare contained on an

XTFX board. The auxiliary cT leads plug into the board and small
ribbon cables route these signalsto the electronicsin the control cabinet.
l-r-T-r-l
I l- Eeqll
i@i
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Flgure 2-1 1.21(V Brldge AssemblY
2-1
LOADCOMilUTATEDINVERTER BHEL
2-1.2 2 l$/ Alr Cooled lledlum voltage Brldge
Figure 2-1 shows the anangements of the power converter siltcon controlled
rectilier (SCR) stack assembles. This figure and elementary diagram
show major pouler components.
SCR's are stacked horizontally three in series between four heat sinks'
The SCR's connected to the source and load P-buses (P1,P21, are
on the left side in the bridge compartment. oT1,CT3,FU1-4 and FU-6
are also on the let side. The N-bus SCR's CT4,CT6,FU5 andFU
7-10 are on the right side of the bridge compartement.
The blower compartment contains the blowers, source and load ac and
dc filters, and MOVs. This compartment also contains the blower starters,
the 7O V gating power supply, the thyristor fan-out PCB XTFH, and
bottom blower selection relay, See Figure 2-2 medium Vohage Bridge
Assembly, 2l(/.
A variant of this design has blower starters, 70V gating supply, PGB
XTFH and bottom blower selection rel in the control and Excitation
Comparlment. Refer to the schematic diagram(drg).
2-1.3 41(\/ Alr cooled ltledlum Voltage Brldge
The anangement of the power converter SCR stack assemblies is shown

in figure 2-3. This figure and elimentary diagram sheets AC,AD and
AE show the maior power components.
Thyristor (SCRs) are stacked horizontally. All SCRs connected to the

source and load P-buses (P1,P2), are in the left bridge compartment.
cTl, GT3,FU1-4 and FU-6 are also in the left compartment. All N-bus
scRs, cT4, cT6, FU5 and FU7-10, are in the right bridge compartment.
Leg modules A are on the left side in each compadment; these

are the master stacks containing a full complement of cards in the
stack (module) insulating box. Leg modules B are the slave moules'
and contain only XPTN card below the cells. The left blower compartment
contains blower numbers 1 and 2, dcfilters, MOVs, and termina! boards.
Also, the hinged base contains btower strater numbers 1 and 2, the
70 v gating power supply, and thyistor fan-out PCB XTFH'
The right blower compartment contains blower numbers 3 and 4, load

ac filters, and dc fifters, blower starters 3 and 4, and the bottom blower
selection relays.
The last paragraph about variant in the design for 2l(/ bridge 2-1.2
- above, also applies to this 41(\/ MVB design.
2-2
INVERTER
LOADCOMMUTATED BHEL
- - -rcr+
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Flgure 2-2 lledlum Voltage Brldge Assembly, 2lC/
ARE MOUNTED
NOTE:IN CERTAINDESIGNS,THE FUSESFU1......FU10
HORIZONTALLY AT THE REAR SIDE OF THE COMPARTMENT
2-3
LOADCOMIIUTATEDINVERTER . BHEL
-EE.[E-
t: { Rro frrz
Flgure 2-g lledlum Voltegc Brl4ge Assembly, 4l(/
NOTE: lN CERTAINDESIGNS,ilE FUSESFUl......FU10ARE TTOUNTED

HORIZONTALLYAT THE REAR SIDE OF THE COMPARTIIENTS
2-4 ! *
INVERTER
LOADCOMMUTATED BHEL
2-1.4 2|KJtl4lKJtWater Cooled lledlum voltage Brldge
The typical anangementof the power conveter componentsand stack

assembliesare shown in figures2-4 through2-9. The Bridge elementary
drawing gives which VPe is used.
The source bridge (21ry/41ry)contains the 70 VPS for gating power'

the dc filter circult components. MOVs, dc filter fuses, MOV fuses,
the voltage attenuation(NAru, the signal distributioncard (XDCI$ and
the cell stack assembles. At the back of the bridge compartment
are the cTs. The MOVs for the 4l(/ bddge also located at the
back of the bridge comPonent.
There are two source compartmentsfor the source series twelve-pulse

configuration.The master"A" bridgedoes not have the signal distribution
'A' bridge is the bridge nelt to
card (XDC10. Normallythe master
'B' bridge is the bridge next to
the load (4lC/) bridge. The slave
the control comPartment.
The load bridge (21(\//4l(\/)containsthe load ac filter circut, the MOVs,

the ac - filter fuses, the voltage attenuationcard (NATL) and the cell
stack aisemblies. CTs are mountedat the back of the bridgecompartment.
For the 4 1(/ bridge, the MoVs are also mounted at the back of
the bridge comPartment.
tn generalthere are 3 cells per leg for 2l(/ bridge and 5 cells per
leg for 4 t(\/ bridge, with variati6ns as per requirement'
,,2.2 THYRISTORMODULES
Each power converterleg module containseither two or three thyristors

arranged in series heatsink assembly.
2-2.1 Alr cooled MVB Thyrlrtor lloduler
The master leg module is mountedin an insulatedbox with associated

printed wiring boards in front as shown in figure 2- 10. The master
module always has three SCRs. An R-G snubber network is also
containedin the leg module box and is located above the cell stack.
Each cell stack assembly conslsts of three cells sandwichedbetween

heat sink as shown figure 2-11. The stack assembliesare oriented
horizorilally in the module as shown. Air flows over the heatsinks
from frbnt to back of the bridge enclosureand the cell modules.
The cells stacks are assembledat the factory under the correct amount
of pressure and it is recommendedthat the entire stack be replaced
if a cell failure oocures. The defective stack must then be sent to
the factory for rePair.
2-5
LOADCOMMUTATED
INVERTER BHEL
FRONTVIEW
DC DO DO FttA RJzA FUJA
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2-6
LOAD COIIIIUTATED INVERTER BHEL
FRONTVIEW
DO DC tu^ ruz ru:t
HBH
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'A' Source Series 12 Pulse

Figure 2-5 Front Vlew of 2KV llaster
Water Cooled Brldge
2-7
INVERTER
LOADCOMMUTATED BHEL
FRONTVIEW
FUlA tu2 tu5

tr V1
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DC DO DO
fi-]
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Uaster "B" Source Serles 12 Pulse

Water Cooled Brldge
2-8
INVERTER
LOADCOMMUTATED BHEL
FRONTVIEW
FUlA FU2A FU3A

7OV PG
T HHHi
s
T
l,
5
A
s
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2
A
,rar.{
. Flgure 2{ Front vlew of 4l(v sOurcc water coolcd Brldge

LOADCOMMUTATED
INVERTER BHEL
LOAD BRIDGE
FRONTVIEW
L
T
L
+
A
L
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A
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Flgure- 2-8 Front Vlew of 2l(V Load Water Cooled Bridge
2-10
LOADCOMilUTATEDINVERTER BHEL
FRONTVIEW
N
A
T
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Figure 2-9 Front Vlew of {KV Load Water Cooled Bridge
2-11
Each cell in the module is paralled by a voltage-equalizing resistor

and by a neon lamp and dropping resistor network to indicate when
voltage is present across the cell. These lights, visible through the
front doots of the equipment,can be used to detect a shorted cell.
The cell light network is mounted on a small card (NTDA) located
above each celt on the front of teh thyristor modules. Figure 2-10
shows the locationof the cards. The NTDA card also containsthyirstor
gate interfacecircuity,as shown in Figure 2-12. Thyristorgating signals
are routed from the gating transformersthrough the NTDA cards on
the thYristor gates.
2A.2 Water Cooled MVB Thyrlrtor modules
. There are two types of water cooledthyristor modulesfor LCl. Module

.A. (WCSC) dnd Module ,B. 'Au has three cells
WCSD). Module
in series and Module 'B' has two cells in series.
'A'' For
For a 2 Kt bddge, each leg contains only one module
one module 'Ao and one module
a 4 K/ bridge, each leg contains
nB' in series.
The .rr- Module consists of 3 SCRs. chill blocks, snubber resistors

and capacitors,equalizingresistors,gate pulse transformer,gate driver
card (HP'n$ and thydstor indication card (NTDL).
The cells are selec{ed,matched and assembled at the factory under

the coneCtamount of pressure. For these reasons,it is recommended
that the entire stack be replacedif cell failure occuftl. The defective
stack must then be sent to the factory for repair'
Each cell in the module is paralled by a voltage equalizing,resistor

and a neon lamp and dropping resistor network which indicateswhen
voltage is present across the cell. These lights are visible from out
side the brldge door.
2.3 OATE DRIVER TRANSFORTER
lF. gall gates are ddven through pulse transformeF mounted on the
'.#n,E|, the module, as shown in figure 2-10 for air cooled designs
ttp,fg*'" 2-4 through2-9 for watercooleddesigns. The pulsetransformers
for eaitr module wired so that all their primary windings are in series.
The primary winding is simply a . conduc{or through the centre hole
of the transformer. Cunent pulse are applied In this conductor by
. the gate driver circuitry. This circuit ensurcs that all thyrisstor in the
string are gated simultarcously and it fudher provides voltage isolation
betrreen the thyristor gates and the elec{ronic gate pube generation
circuitry.
2-12
'r,s
{
INVERTER
LOADCOMMUTATED BHEL
GATE DRTVER CARD (HPTK)
Gate pulse of proper duration and timing are developed in an electronics

module located in a control enclosure at the left end of the MVB.
these signals do not possessthe necessarydrMe and isolationto inerface
directly with the gate driver current transfomers. This interfaceis provided
by the HPTK gate driver and card located in the master thyristor module
in each leg. .The HPTK gate driver and card located in the master
thyristor modul6 in each leg. The HPfi receives the low level signals
and after conditioning,passes them through a pulse transformerto provide
isolatio4. The pulse transformer output divers a pulse amplifier circuit,
which is powered by a 7o Vdc gating power supply located in the
fan and filter compartment of the MVB. the pulse amplifier output
drives all gate pulse transformers in the leg. as described above'
A red light emiting diode (LED) on the board glows to indicate when
gate pulses are Present.
A Second function of the HPTK card is to detect an undervoltage

condition of the 70 vDc supply. lf it detects an undervoltage, HPTK
outputs a logic signal to the electronic moudle indicating the fauft. The
electronic control then takes appropriate action to shut down the drive.
Additionally,the undervolageon each gating card detects wiring defects
in the gating power. Figure 2-13 is a block diagram of the HPTK
card. The pulse driver delivers a current simultaneouslyto all thyirstors
in the leg module.
VOLTAGE FEEDBACK ATTENUATOR CARD
In order to properly control the gating signals to the MVB, the electronics
in the control. enclosure must have available analogs of all ac and
dc bus voltages. The XPTN attenuatorcards in the air cooled thyristor
module to reproduce bus-to-bus signals for each converter bridge. The
water cooled bridge uses a NATL card containing 5 attenuator networks.
Figure 2-14 shows overall attenuator connections for developing bus

uoltug" feed back signals for entire bridge. The aftenuator network
tied to each bus has resistance of 5 megaohms. note that only five
bus-to-groundsignals are required. . Consult MVB elementary for details
of attenuator connections.
In figure 2-14, series string of thyristors is represented by a single

SCR symbol.
Note that the line-to-groundattenuator in leg module 4 is not used.
As discussed in an earlier section, the voltage signals are used to

control firing of the scRs and to provide various functions.
The XPTN containsa iumper that is posilionedto provide proper attenuator

between the bridge and the electronics. For the water cooled design
these jumpers are located on the XDCK signals distribution card. See
system elementary of proper setting'
2-13
LOADCOMMUTATED
INVERTER BI{EL
The arrangement of the attenuator for the converter and inverter is

identical.
AIR COOLED MVB STGNAL D|STR|BUT|ON BOARD O(TFH)
All signal interchangebetweenthe drive electroniccontrol and the medium

voltage bridge is the made through the XTFH signal distribution board
located in the^fanfilter compartment. A small ribon cable from each
HPTK gating card connects to the XTFH board. these twelve ribbons
each contain gating control signals, attenuated bus voltage signals. and
70 voh. power supply undervolagesignals. The six undervohagesignals
from each bridge are combined in the XTFH card to produce a composite
undervoltage signal for each bridge. The gating signals originate in
the electronics module in the control compartment, while the remaining
signats originate in the medium vota$e bridge and must terminate in
the electronic module. Signal interchange to the electronics module
is made via two large ribbons that connect the XTFH cards with firing
cards in the electronics module.
The XTFH contains the burden resistor circuits for the source and load
line current transformers. The CT leads plug into the XTFH board
and two small ribbons route these signals to the electronics module
in the control cabinet.
WATER COOLED STGNAL DISTRIBUTION BOARD (XDCKo)
All signal interchange between the drive elctronic control and the MVB
is made through the XDCK signal distribution card located in the left
side of the source bridge compantment. ln a source series twelve-pulse
"B" bridge. 10. pin ribbon
configuration,the XDCK card is in the slave
cables from each HPTK gate driver card connects to the XDCK card.
Each ribbon cable contains the gating signal and 70 volt power supply
undervoltage signal. The six undervoltage signals from each bridge
are combined in the XDCK card to produce a composite undervoltage
signal for the control.
The XDCK card also receives the attenuated signals from the NATL
card. Further attenuation is done on XDCK card by a means of
Berg jumpers to select the correct attenuationfor 2 K/ or 4 l(/ system'
The XDCK card contains the burden resistor circuits for the souue
(master and slave for a series twelve pulse system) and motor line
current transformers. The CT leads plug into the XDCK card 2
lO-pin ribbon cables route these signals to the electronics module. The
gating and attenuated voltage signals for each bridge are combined
on the XDCK crad and routed through a 314 ribbon cable to each
NSFC firing card in the control electronic module.
2-14
MASTER(3) CELLMODULE SLAVE(2) CELLMODULE
tilirAl m [iTrrl
tr_l tr_l toj
E E E T t n
E I T
HPTK XPTN XPTN
NTDA _ CELLLIGHTAND GATEINTERFACEBOARD

HPTK _ GATEDRIVERCARD
XPTN - ATTENUATOR CARD
PT _ PULSETRANSFORMEER
NOTE: 2 CELL SLAVE MODULEUSEDON 4KV MVB ONLY
Flgurc 2-10 MVB Thyrlster Modulc
il l.ll
II
HEAT SINK
Flgun 2.11 I\rB Goll Strck Arrombtyr
2-15
INVERTER BHEL
LOADCOMMUTATED
EXCITER VOLTAGE CONTROLLER (EVC)

machine
The Lcl drive requires controllableexcitationin order to maintain
and speeds' The. exciter package
flux as required for varying loads
is :"ated to supply the excitation
'the SFE or SFF and
suppftA is type
required for drive. The SFE module is rated 480 Vac, 30/60
EVC contains
Aac and the SFF module is rated 480 Vac, 150 Aac' The
entirely by the
a three phase scR static switch which is controlled
output' The
LCI electionics module to produce a variable ac voltage
per an internally
LCI controls the exciter gating to maintain machine flux
generatbd program which is set for the application'
The EVC consists of the following major components:
1) SCR modules-total of 3 modules of 2 SCRs'
2\ACcurrenttransformers-ACCTsareprovidedontwooftheac
inputlinestothebridgetogiveacurrentfeedbacksignalto
the LCI control.
of the bridge
3) Line fuses-A fuse is provided in each ac input
to limit available short circuit current'
propellor fans
4) Bridge cooling fans, SFF version only-Two small
aremounteo"onthebridgeenc|osuretoprovidecooling,Acircuit
isprovidedtosensesta||cunentintheeventthatthebearings
circuit is wired
size on either fan. A contact output from this
event of a
to the LCI control and initiates a shutdown in the
fan failure.
2-16
5) NHVL interface board providing the following functions:
a) Provides pulse transformersto isolate between scRs and

the gate pulse signals from the control module.
b) Provides high voltage attenuator circuits to provide signal

level feedbacks of the six ac buses to the Lcl control.
c) providesa rectifierand burden circuit to produce signal level

dc voltage proportionalto exciter output current using the
ACCT signals as an input' This dc signal is used by
the LCI control for field over/under current detection'
The EVC is interfacedto the NSFE board in the LCI control

via a 34 pin ribbon cable that connectsbetweenthe NSFE
and the NHVL boards. The NSFE board in the LCI provides
signal conditioningand interfaceto the microprocessor. The
microprocessor in the LCI generatesfiring controlto the NSFE
board which in turn pioduces gate pulse signals for the
EVC. The EVC and the LCI source bridge share the same
phaselockedloop,so it is necessarythat the phaserelationship
betweenthe source and exciter ac voltage to be fixed. This
phase difference is 'a field set software adjustment'
2-17
HPTX GA]INC BOARD -------1

r----
Flguro 2-13 HPTK Gate Drlver Card Block Dlagram
2-18
LOAD CO]IIMUTATED II{VERTER BHEL
â ,rr{ I
c
VA-!ts - VAB
\ts-vC - \8C
VC-VA - \€A
\F-Vrl-\FN-VDC
Flguro 2-14 BrHge Attenuator Clrcultr.
2-19
BHEL
LOADCOilM UTATEDINVERTER
TO
FROM BRUSHLESS
5-PHASE EXCIlER
STJPPLY
RR|NCCIRCUITS
NHVLCIRCUITS
FEEDBACK
SIGNALS
FROM/TO LCI
Flgure 2-15 Synchronous Fteld Excltor Module (SFE' SFR
2-24
INVERTER
LOADCOMMUTATED BHEL
Chapter 3
Control Electronics Panel

3-1 INIHODUCT|ON
The control electronicspanel is made-up-mainlyof various modules inter

connecfed through ribbon cables and harnessed wiring. The main modules
are:
t LCG or LCL Main Control electronics
' IOM Inputs/OutPuts(l/O)
' SIM Auxilary interface electronics module
' SFE/F Field exciter (Discused in chapter 2)
e LDM Display Module
The modules are typically configured as in figure 3-0 for the LcG
and Figure 3-1 for the LCL following are brief descriptionsof the functions
of the module. For more specific information,the correspondingmodule
elementary and documentation should be consulted'
3-2 ELECTRONICS MODULE (LCG,LCL)
The LCG electronics module is buitt into a 2 row by 6 slot card

cage as illustrated in Figure 3-2. The LCL electronics module is used
to control an LCI with series twelve-pulse source. Because of the
extra hardware required to control additional converter, the LCL module
is built into a 2 row by 12 slot card cage as illustrated in Figure
3-3.
The primary purpose of either of ihese modules to is to control the

firing of the power converters and field exciter for driving a synchronous
machine. They also provide various protective functions for the equipment.
Connection is made to the electronics module (LCG or LCL) through

the plugs located at the top and through card front connectors. From
a functional standpoint, the electronics module processes signals as
represented in Figure 3-4.
The module requires *5, r 15, and + 28 volt which are provided
- by a base-mounted Power suPPlY.
&1
LOAD COIIf, UTATEDINVERTER BHEL
Flgurr 3{ LCG Contrcl lnterface
The hardYvar€of the electronica module is represented from a block

diagram standpointin ligure 3€.There is one microcomputercontrolling
the- firing of lgth of the Power converters and the field exciter.
tre mLrocompqter establishes a local bus (L-bus) stucture on which

the inpuUoutputfor is it is interfaced. In addition, it comunicates to
an 8k-Uyte rbadArrite(RAM) memoryand a 2k byte elecidcallyalterable
memory (EEPROM).Thls memorycombinesfeatureof readArrttememory
-and
(RAM) read only memory (ROM) In that it ls electricallyalterable
(although slow) and d ure same does not lose its contents on power
loss. The primary t|3€ of this EEPROM memory is to store parameters
that must be tailored to eacfr different system. These parameters are
field adiustable for drtue tuneuP.
The local br.rshas a timer and intemrpt card thd Pro/id€s the necessary
hardvyarebr control of intemr$ priotity and timing ior the microcomputer'
These are inPwoutptrt pod on the local bus thd interface static logic
signals tofirom the microcomputer. As an example, thyttstor gating
cohrnanOs aro written out to one of these ports (on each side) and
sent to an analog card to produce the gding signals to the converter
bridge. T?t€ ol€ct'onic conbol contains a number of analog cards that
pro""o" the rotagO feedback, cunent feedback, m€ter signals'etc'
t2
LOADCOMMUTATED
INVERTER BHEL
Flgure 3-1 LCL Control Electronlcs lnterface
Analog to digilal converter cards interface the speed reference, voltage

feedback, current feedback signals, etc., to the microcomputer bus on
each side.
l/O cards interfaceprocesscommandand status signals to the microcumputer.

These inputs are combined logically by a sequencing program in the
microcomputer to control the relays in the lOM. These outputs are
used to control system devices such as panel lights, contactors, etc.
3-3 CONTROL OPERATIONAL DESCRIPTION
3-3.1 Baslc Prlnclples
Refer to the control system block diagram in Figure 3-6. The speed
reference from the process controller is compared to a speed feedback
derived from the integrated motor voltage or an optional tachometer
to develop a speed error input to the gpeed regulator. The output
of the speed regulator is a torque command,
The torque command signal is applied to both the source and load
side control. Machine torque is function of flux, current, and the angle
between them. Therefore, torque can be controlled by adjusting stator
current magnitude at a fixed angle or maintaining a constant current
and varying the displacement angle. The cunent is controlled from
the source side, whereas the angle is rraried from the load side. At
any instant in' time, the torque is actively controlled by only one of
these means.
3-3
INVERT.ER
LOADCOMMUTATED BHEL
* oE n n
il
il
miiH lrdbdtr tr E
JG JA
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Flgure 3.2 LCG Electronlcsmoduld (SEM)Card and Gonnectorlayout.
The torquecommandto the sourceside controlis appliedto a maximum

and minimumcunent limiter. The minimum current levels is set to
maintaincontinuouscunent in the dc link. The minimum current is
usually set at 0.2 pu of rated dc current.
The minimumcurrentlimit also effectsthe load firing angle (and hence

machinepowerfactor)Wheneverthe torque commandproducedby the
speed regulatoris less than the minimumcurrent limit. ln this case'
the load firing angle (and machinepowerfactor) is varied as a function
of the torque command. While stator currentis held constant. Thus,
torque is controlledthrough adiustmentof machinepower factor when
ever torque command is lower than minimum current limit'
The minimumcurrent limit may also be dynamicallyincreasedby the

action 9f the voltage limit regulator. this regulatoracts to reduce stator
vohageby simultaneously increasingcurrentand decreasingpowerfactor.
The voltage limit regulatoris not practicallyuseful except in applications
where the field excitation is fixed.
3-4
INVERTER
LOADCOMMUTATED BHEL
JEB ,rDB JCE ,rBB .,EA .JDA JCA .EA .tr4
trtrEtr trtr
.,(B JJB +IB .IGB .fIB JG .TIA
+IA JGA JAA
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i i i i i i i l ' r l
i r r l i l l l l l l
LCL MEM TAYOIJT
Flgure 3€ LCL Electronlcs Module (MEM) Card/Connector layout.
Whenever the torque command is greater than the minimum current

limit, the load firing angle is either at its rectifying or inverting limit.
lf motoring, the load angle is at its inversion limit. lf regenerating
(braking). the load angle is at its rectifying limit.
when motoring,theload control adiusts the firing delay angle to be

as late as posJibleto maintaina fixed commutationsafety margin (usually
20 degrees). This control adapts to changes in stator cunent and
vohage to maintain the margin angle constant.
3-5
LOADCOMMUTATED
INVERTER BHEL
_______J \
\
AT'TENUATION
SIGNALS ELECTRONIC SCR GATING PULSES
MODULE
LCG/LCL
SIM MODULE, r/o MoDuLE \

-1,/
/'/ | l\
/ \
L|NE/LOAD CURRENTFB rF
TACH USED
\ ./
\ i-------------l .,-
'\
./'
F I E L DE X C I T E RM O D
\r--------------r./
POWERSUPPLY
module
'Fire As
This feature maximizes motor power factor and is desinged
Late As Possible' (FAI-AP).
Referring to Figure 6-8, it is shown that the angle of advance, F,is

the sum of the commutation angle, p and the margin angle, y. For
maximum efficiency, it is desired to keep the margin angle as small
as possible without encounting commutation failure. The objective is
to determine the latest possible point for each oncoming commutation.
When the drive requires regeneration, the load-side thyristors are fired
full advhnce (point "X' in Figure 6-8). and source side controls currenl
by reversing the dc voltage to match the recrified motor voltage.
The drive cunent command is taken to be the greater of the absolute

value of the torque command from the speed regulator and the minimum
current limit. The current command is compared with current feedback
and the error is applied to the cunent regulator. The current regulator
controls the firing of the source coverter (rectifier). Thus, the source
control adjusts the dc link voltage as required to produce the current
and torque needed to drivce the load. lt should be noted that the
load firing control reversie of the polarity of dc link voltage if braking
. torque is required.
3-6
INVERTER
LOADCOMMUTATED BHEL
3-3.2 Pulse Locked Loop OPeratlon
Sinceit mustbe possibleto firethe thyristorsat specificangulardisplacemnets

from the ac bus voltage a means of tracking bus voltage angle is
required. A phase locked loop (PLL) is used by source and load
current for the purpose.
The PLL uses the zero crossings of reconstructedthree phase flux

waves as a iiming reference. At each flux wave crossing. lt is
possible to determinethe angular position within the present cycle of
phase A to neutral of the ac bus voltage. This position or phase
is comparedto the value in a PLL counterto derMe a phase error.
This error is applied to the PLL regulatorwhich acts to increase will
be driven toward zero. The PLL conter divides an electrical rycle
of A-N into 1024 incrementsand resets at the end of each cycle,
The value in the PLL counter can be read at any the control software'
The time to fire a particularthyristor can then be calculatedusing
by using the PLL counterreading. The desiredfiring angle, and an
appropriate offset for the cell being fired.
Electronlcs module prlnted wlrlng Board (PWB) Descrlptlons
Followingis a list of cards used in the electronicsmodule. The function

and condensedtheory of operationof these cards follows the list. lt
is not the intent to describein great detail the inner workings of each
card,butto retate their function in the overall system. For more detall
refer to the appropriateO & M manual, for operating notes and for
elementarydiagram. lt is generallyhelptul to refer to the card symbols
in the SEM elementarydiagram.
Itllcroprocesaor- HMPG/DMPB
The HMPG is a single board computerwith the following features:
1. 80286 microProcessor
2. Programmable communications interface
3. Programmableintervaltimer
4. ln-board RAM memory (16K bYtes)
5. On-boardPROM memory 64K bYtes)

.6. Mapped ll0
7. Bus hog timer
8. Stall timer
3-7
LOADCOMiIUTATEDINVERTER BHEL
RELAYg LIGHTS
CONTACCTS
PUSH BUTTON
REFERENCE
ME'IERSIGGNALS
Flgure 3-5 Electronlcs ltlodule Block Dlagram
llo module output ribbon continuity
Door module ribbon cable continuity
4. Zero crossings detection. Circuitry is included to derive source

and load crossoverinterruptsfrom squarewave informationoriginating
on the NLIB boards. A singal clock pulse interruptis obtained
at each crossover.
5. Two programabletimers provide the functions of:
PLL clock (source and- load)
Time counter (source and load)
Speed calculation
Clock for serial communicationport
3-9
RS-232 compatible port. only the transmist function implemented

at the port is intended for driving a printer located in the door
module. The control line. DSR (data set ready), is also monitored
to' determine the status for the remote printer.
7. Digitalto analogconverters.Three 8-bit D/A convertersare supplied.

On f and D/A 2 are 8 bit non-commited outputs. The 12 bit
D/A is commited to supplying the torque reference between 6
pulseconvertercontrolswhen used in a 12 pulse redundantsystem.
bystem level documentation will define its use (if any) in other
systmes.
3-3.7 Analog/Dlgltal lnterface Card HAIA
The HAIA board dccepts 16 analog input signals, mutiplexesthem to

povides
one line and converts to two byte digital word' The ly'D
11 bits of magnituderesolution. Aslo provided are three, 8-bit digital
input port and one 4-bit digital port' (See Table 3-3)
Table 3-lA, RS232C connector Slgnals
Pin Name Signal Dircction Function
JB-2 BA TXD output transmitdata
JB-3 BB RXD inpuil receivedata
JB.4 CA RTS output requestto send
JB-5 CB CTS input clearto send
JB-6 CL DSR input data to set ready
JB.7 AB DCOM input signalground
JB-8 CD DTR output ready

dataterminal
3-10
U E
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Flgure 3€ LCI System Regulator Block Dlagram.
3-11
LOADCOI'MUTATEDINVERTER BHEL
Table 3-lB, HIIPG Jumpers, Testpolnts, LEDs
JUMPERS
Nomenclature Functlon posltlon
J1 selects type of PROM 8116
J2 selects type of PROM 16k
J3 selects bootup method (ory'off bd) DGN
J4 selects 8 or 16 address segments 8

on L bus
J5 ground for RS232 GND
TESTPONTS
Nomenclature Functlon
ffi"t"t. Jumperto commonto reset processor.

a _
DCOM DCOM. Digital common.
r/s lnhibit stall. jumper to common to aciivate.
STNMI Test nonmaskableinterrupt.Jumperto commonto active'
LEDs
BHOG Bushog. On when non-existantaddress is called by

software.
TST Softwarecontrolledand define. On during initializationI

t I
self test.
3-12
INVERTER
LOADCOTIMUTATED. B]{EL
Table &1C. DilPB - LEDs and Swltches
olr, is off if self test is not passed.
Write enable, On when wdte capability to board is

enabled with switch WREN.
Activates the board to allow alteration of the drive

tune up parameters.
3-13
3-2 HLCB - LEDs and testpolnts
Functlon
Sofirare controlledas a functionof self test. Normally

oD, is off self test is not passed.
Digital to analog output 2. Normally uncommitted.
Digitalto analogoutput3. Noramllyused for horsepower

output.
Digital to analog output 4. Normally used for torque
Executionflag for source crossoverand angle control

motion.
Execution flag for load crossover and angle control

routine.
Executionflug for EVC angle control routine
Executionflag for backgroundprogram.
Phase A signal for source power.
Phase A signal for motor voltage.
Digital common.
€ee Figure 3-7 tor Typical wave forms.
3-14
INVERTER
LOADCO'TIMUTATED BHEL
3€.8 Flux Integratorc - NLIB
The NUB contains various analog signal conditioning as follows:
1. Voltage integrators
2. Line/load cunent transformersreceivers
3. Voftmeter driver
4. OvervoltageProtection
5. Undervoltagesensing
6. Suppression
7. Current motor drMer
3.3.8.1 VOLTAGE INTEGRATORS
A signal proportional to each line-to-line voltage is obtained from the

., NSFC board. The signal is applied to an analog integrator to obtain
a replica of motor flux,
Components of line currents are used to compensate for drops due

to motor resistance and commutating impedance so that the flux represents
the motor internal counter-emf or the so the so called voltage behind
the commutating reactance. The analog sine wave corresponding to
flux is then available to the HCLB for phasing information. The analog
flux signals are also read by the microprocessor based software for
use in the control algorithms.
3.3.8.2 LINE /LOAD CT RECEVERS

receiversare includedfor line cunents
differential
Two signalconditioning
A and c. Line current B is calculatedfrom A and c assurning a
balancedload. Delta currentsare also determinedfor use in the flux
reconstruction.
3-15
a
LOADCOTIIIUTATEDINVERTER BHEL
i X-CELLlrulI
ADVANCE
E
EE Z - IN\ERSIONUMIT
+F
r{
z.
f
Y - CELL1 ruLt RETARD
2
J
F
J= o-
-<
ed
6
H
2
Flgun.3-7 Flux Wavu Zcrc€rcollng
3-16
Table 3€. HAIA lumpen and Testpolnts
Functlon Poeltlon
Selects either a fixed + 7.5V inputA to P

to channel 15 or a vadable inPut
through pin 12. The vadable inPut
is selected.
Selects either a fixed + 7,5V inputA to N (SRC)

to channel 14 or a vadable inPut
through pin 12. The vadable input
is selected.
Selects L bus address for board. F
Selects L bus address for board T
Selects L bus address for board. F
Selects filter for analog side of A/D

converter. Filter is selected.
Power supply analog common.
Test input. Tie to common to

latch internal card data bus.
Analog slgnal at input to A/D converslon.
Data buffer direction. High transmits to

microprocessorand low receives.
'O' data valid signal.
"1o busy signal.
Card clock - 1.152 mhz
3-17
INVERTER BHEL
LOADCOMMUTATED
3€.8.3 VOLTIIETER DRIVER
The magnitudeof the line-to-linevoltage is determinedby a 3 phase

absolutevalue nefirvork.the absolutevalue is then scaledby an operational
amplifier for use as a line voltage signal'
3€.8.4 OVERVOLTAGEPROTECTIOI{
The absolutevalue of line of line/motorvolts obtainedabove is compared

with an adiustablereferencefor a. time determinedby daughter board
component,c37, then the overvoltagelatch is set. The signal is wired
toanuoportforfault|oggingbythecontro|software.
3€.8.5 UNDER VOLTAGE SENSING
The absolutevalue of line/voltsis comparedwith an adiustablereference.

.lf the voltage is less than the referencefor time delay set by daughter
'1LV' becomestrue. this signal
board comionent, C17, then signal
is used by the software system sequencingto determine low source
volts condi'tion. The function is not used on the load side'
3€.8.6 SUPPRESSION
to
The absolute yalue sum of the line currents is taken and applied
comparator. it tt " rectified cunent exceeds the reference threshold
for 26 ms. a fault latch is set. The time delay is included since
the primaryprotectionis in software,which includesan on-line recoverry'
the function implementedhere is strictly backup'
3.3.8.7 CURRENTMETER DRIVER
The absolutevalue of current is scaled and availablefrom either source

or load for meter driving. Scaling is 5v = 1 pu (See Table 3-4)
Table 3{. NLIB lumpes, Adtustments, LEDs and Testpolnts
Functlon PGltlon
Selects voltage integrator scaling 12OHz or

for 6o Hz or 12o hz (var)
3-18
LOADCOMI'UTATEDINVERTER BHEL
Scale flux integrators that calculate flux. Scaling

is 4,75 volts RMS conesponds to l.PU.
Set overvoltageprotection trip point.
Set undervoltageprotection trip point.

(Not used on load side).
Set trip point for overcurrent backup fault.
On when overvoltagefault latch set.
On when overcurrentfault latch set.
On it microprocessorbased self test is passed and

saturation conditions are present.
Analogdc voltageproportionalto setpointof overvoftage

fault latch.
Analog dc volage proportional to setpoint of source

undervoftage sensor.
Analog dc voltage proportional to setpoint of overcurrent

fault latch.
Analog voltageproportional
to motor/lineflux reconstructed
for lX drop. See Figure 3-6 for typical wave form.
Analogvoltageproportional
to motor/lineflux reconstructed
for lX drop. See figure 3-8 for typical wave form.
Analogwave form representative

of invertedline current.
See Figure 3-8 for typical wave forms.
3-19
LOADCOMMUTATED
INVERTER BHEL
Gatlng Reference Board - NSFC
The NSFCs primary task is to convert inlormationfrom the microprocessor

based control to cell selection and timing for firing 6 thyristors configured
into a 3 phase double way bridge in performingthis task. The following
functions are used:
1. R bus interface
Firing mask latch
3. Cell state sensors
4. Line-to-line voltage signal conditioners
5. Pulse train generation
6. Gate drivers
7. Attenuator buffers
8. DC vohmeter driver
A Separate NSFC is used for the source and load converters.
3-3.9.1 R BUS INTERFACE
Control logic is provided for decoding read and write strobes. Eight
data lines (either upper or lower byte) are connected. All information
exchange with host processor takes place through the R bus interface.
3.3.9.2 FIRING MASK LATCH
The particularcell pair to be fired is selectedin sofiware and communicated

to the NSFC over the R bus. The mask information is temporarily
stored in the primary firing masklatch. Also obtained from the software
is time delay corresponding to the number of degrees the cell pair
firing is to be delayed. This infromation is routed to a timer. At
the end of the delay, an interrupt is generated and on the load side
the cell mask is clocked into the final latch. On the source side,
"excute firing" program which (if all
the generated interrupt catls an
permissives are met) signals the NSFC to move the firing mask to
the final latch.
3.3.9.3 GATE DRIVERS
. Six darlington transistors shift the gating information from logic level
to ana[og levels sufficient to drive the remotely mounted gate pulse
amplifiers. These drivers operate at 28 Vdc levels.
3-20
INVERTER
LOADCOMMUTATED BHEL
3.3.9.4 PULSE TRAIN GENERATION

"o" true pulse trains
The gate pulse reference signals consistes of
normally 120 degrees long during the conduction period. The reference
pulse train is generated from a crystal clock and shaped for a duty
cycle of 15 microseconds on and 30 microseconds off by a timer
and control logic.
3.3.9.5 BUFFERS
attenuator buffers are provided to receive each attenuator string conected

to phases voltage 1,2,3 and also the positive and negative bus. These
butfered signals are then used for analog line-to-line voltage signals'
3.3.9.6 LINE.TO.LINE VOLTAGE SIGNAL CONDITIONS
The buffered phase to neutral converter voltage signals are differentially

combined to recreate line-to-linevoltages. These are used after further
processing (on NLIB) as informationfor the software control algorithms.
3-3.9.7 CELL STATE SENSORS
From a cuFory check of the standard three phase double way bridge
configuration, it can be seen that the voltage across each cell is a
combination of one phase voltage and one D-c bus voltage. since
each of these voltages is avilable from an aftenuator, the voltages
"onstate" may be uniquely determined' Circuitry
across each cell or
"state" of all cell at a particular instant
is provided for reading the
and for making the information available to the microprocessorvia the
L bus'
3€.e.8 D-C LINK VOLTS
. The positve and negative D-C link bus voltages are combined differentially
to obtain a dc link volts signal suitable for driving a remote analog
meter with approximately 10 Vdc maximum scale. (see Table 3-5).
3-21
LOADCOMTIIUTATED
INVERTER BHEL
Table 3-5 NSFC Jumperc, Adjustments, and Testpolnts
Determinesif new mask should be NINT

clocked into final latch at termination
of count down timer.
Sets remote meter full scale to

correspondingdc link volts
IMOK I board hardware status indication. on normallyOff if

self diagnostics determines a board hardware failure.
.
slc 1-stc 6 Gate pulse command. "On true. Steady state length
of 120 degrees relativeto operatingfrequenry. Each
gate pulse is shifted 60 degrees relative to lower
numberedones. SIG numberscorespond to thyristor
leg being gated.
Output of dc link voltage meter driver.
Analog output proportionalto motorftourceline-to-line

voltage.
Power supply analog common.
3-3.10 Fleld Excltatlon Contral Board - NSFE
The NSFEs primary task is to convert informationreceived form the

microprocessorbasedcontrolto cell pair and timingfor firing 6 thyristors
configuredin a 3 phase bridge configuration. lt atso providesanalog
interface and diagnostic interafce for the extermal power converter.
The following functions are provided.
1. R bus interface
Firing mask latch
3-22
FAB
E.72VPK-TPU
RECONSIRUCTEDFLUX TES1POINTS
7V PEAK -1 PU
,IA
4.964 - I PU
,IB
4.964 - I PU
,tc
4.964 - 1 PU
IFB
-5V - IPU
Flgurc 3€ Analog
3-23
INVERTER
LOADCOMMUTATED BHEL
3. Cell state sensors
4. Attenuatorsignal conditioning
5. Pulse train generation
6. Gate drivers
7. Current feedback conditioning
8. Current unbalancedetector
3.3.10.1 R BUS INTERFACE
Control logic is providedfor decoding read and write strobes. Elght

data lines (either upper or lower byte) are connected. All information
exchangewith the host processortakes place through the R bus.
3.3.10.2 FIRING MASK I.ATCH
The particulariell to be fired is selectedin softwareand communicated

to the NSFE over the R bus. the mask informationis temporarily
stored !n the primary firing mask latch. Also obtained from software
is a time delay corresponding to the number of degreesthe cell firing
is to be delayed from present time. This information is routed to
timer. At the end of the delay and interrupt is generated and the
cell mask is clocked into the latch to selected cell pair.
3€.10.3 GATE DRIVERS
Six darlington transistors shift the gating informationfrom logic level

pulse
to analog levels sufficient to drive the remotely mounted gate
amplifiers. These drivers operate at 28 Vdc levels'
3€.10.4 . CURRENTFEEDBACKCONDITIONING
A different amplifier is used to receive the field cunent signal from

the field excttei module (remotefrom SEM). The scaling is ananged
tor 2v correspondsto 1 per unit field on the input and + 5.0 volts
equals 1 per unit El. An additionalsignal (EIMTR) is also available
formeterdrivingwithapotadjustab|egainrangeot2:l1
3.3.10.5 CURRENT UNBALANCEDETECTION
. To detect fault conditions within the motor exciter' the field current
is applied to a filter tuned to the excitation fundamental frequency'
It can be shown that conditionsof unbalancecause a dramaticincrease
in currentfeedback'sharmonics. The conditionof the sensor is available
tothesystemprooessorthroughthedatabus.(SeeTab|e3.6).
3-24
LOADCOMMUTATED
INVERTER BHEL
Table 3.6. NSFE Jumpers, Adlustments, Testpolnts
JUMPERS .NONE
ADJUSTMENTS
EIMTR Sets full scale reading on field current signal.
TESTPOINTS
Nomenclature Functions
ctP Cable in place. When the cable from the NSFE board
front is properly installedin the external module, voltage
at CIP is less than .5V. lt the cable is not in place,
the voltage is below 15V.
VABS Signal proportional to the absolute value of exciter

output voltage. Always posistive and scaled for
approxmately 10 volts at 1 per unit output.
LVAC Signal showing the exciter module input wave from

on lines A-C. The scaling is approximately 4.5 Volt
peak corresponds to peak line volts.
FUN Outputof fundamental bandpassfilter monitoring Field

current. ls near zero volts under normal conditions.
EIMTR Output of field current meter driver. Range o-1o volts,
IFB Field current signal with 5 volts correspondlng to 1

per unit.
SIGl-SIG6 Gating signals to externalthyristors. Nomenclature

correspondsto the firing order. Each signal is 28
Volt level and is 0 when true.
ACOM Analog common,
CONT Continuity.Signal for checking continuity of ribbon cable

to external excitation module.
3-25
LOADCOI'MUTATEDINVERTER BHEL
3.3.11 ANALOG LCI BOARD . NLCB
The NLCB providesmiscellaneoussignal conditioningand test functions

required for the LCl. These feature includes:
1. Speed signal generationfrom load voltage zero crossingsignals

with overspeed protection and indication.
2. External referencesignal conditioning.
3. Test reference signal conditioning
4. Torque referencesignal conditioning
5. Self test features.
6. +20 MA signal drivers.
7. Ground fault detector.
8. Power applied reset.
9. Fault relay drivers.
10. Horsepowermeter driver.
11. Continutydetectioncircuits.
12. Test Switch.
13. Restart upon power loss.
3.3.11.1 SPEED FEEDBACK
A pulse rate signal proportinalto drive speed is obtainedfrom zero

crossingdetectioncircuityon the HLCB. A pulse rate to analogconverter
then produces a corespondingdc level proportionalto speed suitable
for driving a meter and protective functions.
The overspeedfunction is implementedby comparing and overspeed

setting referece to the analog speed signal. The overspeed detector
is latchbd when activated. A red LED indictesthe overspeedcondition
until reset.
3€.11.2 EXTERNALSPEED REFERENCE
A differentialamplifiercommitedto acceptingthe remote speed reference

_ is supplied. Berg jumpers are used to configurethe circuit to accept
a 0 to 10 volt signal or a 4-2O MA signal. In either case, the
output voftage is transmittedto one channel of the HAIA analog to
digital converter for reading by the system processor.
3-26
I]{VERTER
LOADCOMMUTATED BHEL
3€.11.3 TEST SPEED REFERENCE
A differentialamplifier is includedto condition a voftage source signal

from a potentiometerlocated on the UO module. This is also known
as the local sPeed reference.
3€.11.4 TORQUE REFERENCESIGNAL CONDITIOI{ING
A differentialamplifier for roceiving the mastor torque reference form

the other six pulse drive (in a 12 pulse system) is also supplied.
3-3.11.5 SELF TEST FEATURES
An array of static swithces and voltages sources is included for use

in testing the analog circuitry of this and other boards in the module
during the module self test mode.
A sinewaveoscillatoris used to simulateline and motor voltage dudng

gate test mode. This is to allow the power converter electronicsto
be tested withoutthe necessityof applyinghigh voltageto the associated
bridges.
3€.11.6 4-20 MA SIGNAL DRIVERS
Two voltage to current convertersprovide capabilltyof remotely driving

system'informationto customer interfaces. The signals selected for
transmisionare machine stator cunent and speed. In each case, 4
mA corresPondsto 0.
3€.11.7 GROUND FAULT DETECTOR
The ground fault detector sums line-to-neutralvoltages Va,Vb and Vc.

It operates on the principlethat when all impedancesfrom phase to
neutralare balancedthat the summationof the phase-to-neutralvoltages
will be zero. Any unblanced impedancewill cause an error to be
detected and ground fault noted by the system prressor'
3.3.11.8 POWER APPLIED RESET
A power applied reset is generated and distributed through out the

e|ectronicsmodu|e'|tisusedtopreventfa|seoperationsofrelay
driversand fault latchesduringthe processof poweringup the module.
3.3.11.9 FAULT REI-AY DRIVERS
Relaydriverno.l is generallyusedfor trippingthe sourceside switchgear

from both hardwareand softwaresensed fault conditions. lt is inhibited
from false operationsduing the power up phase by the power applied
reset.
Relay ddver no.2 is generallyused for trippingthe load side isolator

(could be contactor or ckt breaker)from both hardware and software
sensed fault conditions. lt is also inhibitedfrom false operationsduring
the Power trP Phase.
3-27
LOADCOIIiIUTATED INVERTER BHEL
3€.11.10 HORSEPOWER ltlETER DRIVER
. An adjustable gain meter driver for poweing a door mounted meter

indicating horsepower is also included. The horsepower signal is calculated
in software and converted to analog on the HLCB board.
3-3.11.11 COI{TINUITY DETECTION CIRCUITS
Four circuits are included to monitor the continutty of various ribbon

cables connected to the electronics module when it is integrated in
to a system control panel. These signals areoonly monitored during
the panel self test. An appropriate diagnosic message is printed out
'is
il a cable not in the conect location.
3-3.11.12 TEST SWITCH
The test switch on the board front edge is used to initiate the panel
self test mode. When the switch is operated , the electronic module
begins to execute a self test routine, which extends to other Gomponents
of the control panel. upon completion of the self test, the control
enters gate mode using the three phase test oscillator as a source
. of sYnchronous wave forms.
3€.11.13. RESTART UPON POWER LOSS
lf the drive has been previously running and the control power is lost
for a time (determine by setting of HTD potentiometer), a pulse at
signal J RSRT automaticalty restarts the drive when power retums.
Note that this is an option, and the l/o module must be properly
configured. (See Table 3-4.
Table 3-7. NLCB Jumpers, Adlustments, testpolnts, LEDs
Function Posltlon
Selects remote speed reference for Variable

either cunent inptrt or voltage input'
ADJUSTilENJS
Adjusts analog speed leedbackcircuit for 1O volts at

60 Hz.
Adjusts door mounted speed meter for proper full

scale reading.
Hardware oversPeed reference.
Adjusts allowable time for auto restart after loss of
3-28
LOAD COIIMUTATEDINVERTER BHEL
Output of analog sPeed circtit.
Relerence to hardware overspeed detection circuit. Scaled

same as speed i.e.10 volts = 6O Hz.
Ouput of channel A current source.
Output of channel B cunent source.
Output of remote speed reference. With a voltage

input will be O to 1O volts.
Output of local test reference. Varies from O to 8.3

volts.
Outputof torque referenceobtainedfrom other channel.
Neutral. Summation of line to neutral voltages. Normally
Run time delay. Sets allowabletime for loss of control

power while still allowing an auto restart. Scaled o
to 10 volts
Test oscillator,phase A, shows a 55 Hz sine wave.
Test-osdllator, phase B. Shows a 55 Hz sine wave

lagging phase A bY 120 degrees.
Red LED indicating that the hardware overspeed latch

is set.
Green LED that is pulsed when the auto restart circuit

is aclivated
Green LED indicating the status of f;ault relay driver

NO.l. Will be on when the relay driver is energized'
Green LED indicating the stattrs of fault relay driver

No.2. Will be on when the relay driver is energized.
Green LED trat is on when the Test switch is closed

and the system softrvare indicdes gate test mode
3-29
Yellow indicating light will be on normally. An off

condition indicates a possible hardware problem with
the board. lt can be turned off either locally or from
the processor as' a function of self test.
REIAY DRIVER BOARD . HRDA
The HRDA is relay board with 16 open-collectoroutputs. output voltage

can range from 5 to 50 volts. In the LCI system. it is applied
at a nominal voltage of 28 volts dc. The board is connected to the
computerR bus for accesibilltyby the system control' The relay driver
UoaiCls used prinipallyas interfacebetweenthe system softwarecontrol
and the power devices located in the uo module.(see Table 3-8).
Table 3-8. HBDA Test Polnts and LEDs
Reset. Connectingtestpoint 1 to testpoint 2 resets

onty this board. This function isn't usefull in the the
LCI system.
A red LED for each of the 16 relay drivers indicates

the energized status of each circuit.
Yellow LED. Turns on when the board is addressed;

stays on if the board is addressed at least every 2OO
microseconds.
Parily check. Not used in this system will always

be on.
3-30
"b&-
INVERTER
LOADCOMMUTATED BHEL
3-5 . HISA
INPUT SIGNAL CONDTTIONING
HlsA is designedto work in coniunctionwith HRIA (in l/o module)

to conditionthirty high (105 Vdc) signals to logic level and allow access
to them throughthe processorR bus. Each signal is separatelyisolated
by a photocouplerand indicated by a bar LED. Two relay drives
included are only used in the l/O module's hardware seJf test. (See
Table 3-9).
Table 3-9 Input slgnal condltlonlng ' lumperc,adlustments'

Testpolnts , and LEDs
JUMPESRS -None
ADJUSTMENTS .NONE
TESTPOINTS .NONE
LEDs -None
100-l1D Green bar LEDs. Each indicatesthe status of its associated

input.
IMOK Yellow LED On during normal operation Will be

otf only as the resuh of module self test.
Electronlcs Module OPtions
The follwingfunctionsare optionaland may not be supplied Reter

to system documentation to determinepresence,
3.6 TACHOMETERINTERFACE. HTCA
The HICAaccoptstwo-phasepulsetachomotorintputto calculateelectrical

positionof the synchronousmotor shaft. Additionalcircuitryis included
to allow a high accuracy calculationof motor speed. This board is
optional on an LCl.
3-6.1 Tachometer Power SuPPIY
A + 12 volt regulatedpower supply is providedwith output at the

1O-PinJA connectorat the front edge. This supply will source loads
demandinguP to 150 mA.
36.2 Tachometer lnput Condltlonlng
Threedifferentialamplifiersare availablefor conditioningtachometersignals.

Two circuitsare dedicatedto conditioningchannelsA and B, the two
phase shifted frequencysignals originatingat the tachometer.
3-31
INVERTER BHEL
LOADCOMi,IUTATED
The third may be used to buffer either a Marker pulse or a d.irection

signal. For all of the circuits, inputs are received differentiallyand
filtered (5 microsecondtime constant)'
The two frequency singnals are applied to a counter control circuit,

position
constituted bi a state machine, which instructs the 12- bit
counterto countup, countdown,reset,or reload, dependingon tachometer
state changes. This state machineis responsiblefor maintainga position
count whiih truely reflects the position of . the tachometer.
3€.3 Posltlon Counter
The 12-b1tposition counter is allowed to attain values between zero

and some maximum count depending on tachometer activity. Each
electrical rycle of the tachometer changes the state of the counter'
The Informationheld by the position conter's output is to be stable
during anY read Position'
36 .4 Hlgh AccuracY SPeed Clrcult
The hig'haccuracyspeedcircuit,when combinedwith appropriatesoftware,

can calculaterotationalspeed with sufficientaccurauyto yield a o'o5%
speedreso|ution'Thehighacu]acyspeedcircuitmakesuseoftwo
tach
banks of counters, each constitute by a counter to accumulate
pulses and a counterto accumulate1 micro second clock pulses. speed
the
is determinedby digidingthe accumulateadtachometer pulses by
accumulatedclock Pulses.
Table 3-10. Tach Interface Tetpolnts, LEDs'
Tachometer signal-Channel A
Tachometer signal - Channel B
TachometerPower suPPlY
Y.ll^^, LED, *-uring normal operation, will be off

onlyas a result of self test.
&32
INVERTER
LOADCOMMUTATED BHEL
3-7 SI-AVE BRIDGE CURRENTINTERFACE= NBIE
The NBIE card is used in sourceseriestwelve pulse only. The NBIE

card contains several analog signal conditioning.
1. 2 channels of CT, Interface
2. 2 channels current suppressionlogic
3. 2 channels of current imbalancelogic
4. 6 filtered analog/logiclevel circuit
5. 2 reJay circuit
6. Panel reset logic
Only function1.2 and 3 are used in the seriestwelve'pulseLGI control.
CT interface-thecurrent conditioningcircuitry provides two channels of

CT interface. Each channel providesfiltered difierentialinput for phase
currentsvia line A and C. Line A and C signal are used to construct
the missing phase form line B. The three phase currents are used
to generatethe dc link current equivalent,lFB. In LCL MEM only
the second channel is used.
NBIEprovides2 channelsof currentsuppression
logic-the
Currentsuppression
logic. The suppressionlogic monitorsthe generateddc link current
equivalent,lFB. The suppressionlevel is set via the PoT usuPP
which is locatedon the DBIE daughterboard. The setting range is
from 3.9 vdc to -10.2 vdc. The suppressiontrip level set. by vsUP
is commonto both channels. In LCL MEM only the second channel
is used.
Each channelsof the currentsuppressicnlogic providesa 26 ms delay

before the overcurrentconditiontrips h fault logic. Once the fault
'sUPP"
logic is tripped,output 1SUPP = SVdc and the red "OPAR" LED lites
up-. The iault logic is reset by power..up reset or pahel
reset 'ORST'
Currentlmbalance-the boardis designedto provide2 channelsof current

imbalancecircuitry. Only one circuit is used in the LCL MEM control'
"A" and source
The currentimbalance circuitmonitorsthe sourcemaster
slave uBo dc link equivalentcurrent'
&33
INVERTER
LOADCOMMUTATED BHEL
Table 3-ll.Brldge Interface Jumpers, Adlustments and

Tcrtpolnts.
Not used in LCL control
Nomenclature FuncUon
set trip point for overcurrent backup
set trip point for imbalance cunent fault
inverted analog waveform of line A current
inverted analog waveform of line B current
inverted analog waveform of line. C current
analog waveform of dc link equivalent cunent
analog dc volt proportionalto I/SUP POT setting'
analog dc volt proportional to l/lMB POT setting'
3-8 DTSPLAYMODULE (LDM)
The LDM is the display modulefor the Lcl control panel. The display
providesfault, alarm and diagnosticinformation. The dispplay modules
provides the tollowing features.
3-34
LOAD COMMUTATED.INVERTER BHEL
' 24 column printer with real-time clock
t 4 push-to-test indicator lights (RUN.ALARM.FAULT AND READY)
o 2 push btittons (RESET and DRIVE STATUS)
t 4 meters (machine speed, current, voltage and horsepower)
All lights and push buftons are on 28 V circuits. The functions and
color codes for each light are:
' Red for the motor RUN light.
. Red for a system FAULT light.
. Amber for a system AI-ARM light
r Green for the system READY light
The push buttons are connected to a 28 V circuit and direct a 28

V signal to the output when the button is depressed. The RESET
push button is used to reset latched faults in either software or hardware
(NLIB and NLCB latched faults - overspeed, overvoltage, etc). The
DRIVE STATUS push bufton; when depressed, provides information
on the motor voltage, current, speed, etc, via the printer.
The four analog meters are 10 volt movement meters.
The printer included in the display module is Digitec Model 6610 panel
mount printer. The 24 column printer inputs data and control signals
via serial RS232 connection and uses an impact print head mechanism
to output the data. The printer also supplies a real-time clock that
is used to log the time of status information and system failures.
The LDM interfaces to the Electronic Module through a 26 pin ribbon

cable JK.
3-9 vo MoDULE(rOM)
The purpose of the IOMA (l/O) module is to provide signal conditioning
and connectionfor interpaneland purchaserwiring in a load commutated
inverter (LCl) control panel. The following functions are provided.
1. Signal conditioningand isolation for interface wiring at the 105

vdc level.
2. lsolated signal interlocks (form C) to remote locations as a fucntion

of programmedsystemrequirement.Rated,25 A,115 Vac (Resistive).
3-35
INVERTER
LOADCOMMUTATED BHEL
3. Fused 105Vdc power supply to provide a source of high level

power for interface.
4. Power relay control for interface with the load isolator as well
as interface with a line-side switchgear device. Rated 10 A, 600
Vac (lnductive).
5. Local operator's station for running the drive during maintenance

modes. (Channel selector, local/remote, starUstop. Local speed
reference).
6. Terminal boards for terminating interconnecting wiring.
The IOMA module is designed to be intergratedinto a system diagnostic

test function residing in the system electronics module. Therefore, no
local diagnosticmessagesare displayed. However, the necessary circuits
and feedbacks are provided to allow the system function resident in
the electronics module to isolate failed components to the replaceable
board level.
3-10 S|GNAL ISOIATION MODULE (SlM)
The SIM is used to provide optional functions to an LCI control panel.

ln particular, it provides four impedance isolated signal outputs for use
in a purchase/s external control system. The four signals may be
selected as 0 to 10 volts or 4 to 20 mA outputs by header connection
jumper at JM. Each circuit may be selected independently. Inputs
io the module (TEM) are received from the LCI control SEM via 26-pin
ribbon cable (JM). The four inputs the isolation circuits may be chosen
by header connector jumper at JB from the following list of signals:
Source volls, source current, SPD ref,, motor SPD, horsepower, DA1,
DA2, exciter current, motor volts.
A NVAA providesthe functions of voltage to current source transformation

and isolation. A differentialamplifier accepts the signal from the remote
control sEM. The signal isolated from the NVAA on-board ground
by approximately10ok ohms of resistance. The isolated signal is then
applied as a reference to a current source with the gains weighted
such that a 0 to 10 volt signal provides a delta output of 16 milliampers'
An additional bias is provided to give the 4 millamperes at 0 volts
input. A chopper isolated power supply is present on the NVAA board
to power the output stages of the signal isolators. The output of
each of the four circuits is referenced to XCOM, the on-board power
supply common. lt is intended that the XCOM connection be tied
to the customer's external circuit common. While it is not necessary
for the signals used as inputs to the isolators be referenced to the
customer,scommon or XCOM, the difference between ACOM and XCOM
must not exceed 3 volts steady-state or transiently. The voltage developed
across any external impedance in series with a current source must
not exceed 10 volts. The output signals are also available as voltage
followers (0 to 1OV). Maximum output load is 1 mA.
3-36
INVERTER
LOADCOMMUTATED BHEL
Chapter 4
SOFTWARETUNEUPAND PUBLIC VARIABLES

4-1 Software Tuneup Gonstants
EEPROMon the DMPB board serves as a non-volatilememory space

used to hold criticaldrive constantsthat may be system dependent.The
use of EEPROMMemoryallowsfield changeto the drive constantsfor
fine tuningthe systemperformance.EEPROMMemoryis configuredto
contain 1024 bytes (1K x 8).
The drive constantsare burnedinto the ROMs residingon the HMPG

(the ROMs also containthe executablesoftwareto run the drive). These
. default values are intendedto provide a resonablestating base when
tuning the drMe. They may be loaded into the EEPORMMemory by
"ON'. Jumperingtestp_ointTINO
turminigthe DMPBwrite enableswitch
on the HLCB pwb to DCOM,and then executinga hardware sEM reset
turn, ln orderto changea value in the EEPROM Memory,turm tne plne_a
writeenableswitch"ON"and use the monitor(referto Chapter5) MODIFY
command.
After powerup to hardwarereset,the microprocessor on the HMPG makes

a local copy in RAM of the EEPROMMemory. During nolmal running,
the microprocessoraccessesthe driveconstantsfromthis localRAMshadow.
Table 4-1 providesa descriptionof the availabletuneup constants. The

"group' column are defind as follows:
abbrevationsin the
1. CR-Currentregulator
2. Ml-Miscellanceous
3. SR-Speedregulator
4. PT-Printer
5. PR-Protectionvariables
6. OV-Overuoltageregulator
7. RR-SpeedramP
8. SQ-Generalsequencing
9. FL-Flux reference
10. FR-Fluxregulator
11. FC-Fieldcurrent
+1
LOADCOMMUTATED
INVERTER BHEL
Table 4-l Descrlptlon of varlables
Name Group Funetlon
CRALPHl (cR) Variables used in current regulator to shorten time

to reestablish current after a forced commutation.
The variable sets the initial value of the source
liring angle such that the desired value of current
is obtained after the first firing. The following
value is recommeded as start. gpAl-pl{'l=86
degrees
Resolution is 1 degrees and the range is 60 to
90 degrees
The associated software variables and its
relationship To CRALPH1 is given below.
CURREGFIXEDALPH1= 16384*COS(CRALPHI)
CRALPH2 (cR) Varibleusedincurrentregulator to improvetransient

reponseof currentdurringforcedcommutation. The
actionof thevariableis to precondition
the regulator
integratorto cornmanda firing angle necessary
to maintainthe currentlevel establishedusing
CRALPH1- CRALPH2
= ARCCOS[[(4NE + lR) + (.75FPU*VM) +
(XTpu* lpt-/2)l/ (1.3s * E11)l
Where
E = cell drop (1.25 V)
N=numberof cells /leg
FPU= per unit field at ,075 per unit speed
l= cur€Dt (amps)corresponding to current limit
value
lpu=valueof cunent in pu
R=systemresistance(mostlyreactor)
VM= motor L-L volts (RMS)
E11=transtormer sec volts (rms)
XTpu=trasformercomm reacfance
Resolutionis 1 degree and range is 60 to 90
degrees. The associatedsoftwarevariable and
its relationshipto CRALPH2is given below
CURREGFIXEDALPH2 = 16384*COS (CRALPH2)
+2
LOADCOMMUTATED.INVERTER BHEL
Name Group Functlon

CRGAIN (cR) Sourceside currentregulatorgain. The variable's
relationshipto systemparametersis given belt,w.
cRGAtN = (7s9 * WC * L ) /(VL-L)
lM = fund rms rated motor current
VL-L = rated rms L-L source volts
WC =desiredregulatorcrossover(250RAD)
L= inductancein conductiongpath
= reactor+ 2 ( load comm. inductancel+ 2
(transfcomm. inductance).
Resolutionis units and range is 10 to 1000.
Theassociated softwarevariable
and its relationship
to
CRGAINis given below.
CUR REG G2 = 16 * CRGAIN(6-*FROS)
CRMIN (cR) Variablesettingthe minimunvalue of dc current.

Normallyset to maintaincontinuouscurrent. The
linkreactoris usuallypickedto maintaincontinuous
currentat. .2 per unit.
CRMIN = per unit current
Resolution.Ol and the rangeis O to 2.0 per unit.
Theassociated softwarevariableand its relationship
to CRMIN is given below.
CUF REG MIN LMT = CRMIN * 1024
CRSTART (cR) Value of current used in fixed fire for braking away
the load. Also, the current command in speed
regulatoropen test mode. The value of CRSTART
should be that which would give ma< allowable
torque & current at stand still. CRSTART=
Allowable current at start.
Resolutionis. 01 and the range is O to 2.0 per
unit. The associated software variable and its
relation to CRSTART is given below.
CUR REG REF START = CRSTART*1024
CRTC (cR) Time constant used to stabilize the source side

current regulator
CRTC=time constant (in seconds)
Resolutionis .001 seconds and the range is .001
to 500 seconds.
The associated software variable and its relation
relation to CRTC is given below.
CUR REG Gl = 4* CRGAIN*CRTC
4-3
INVERTER
LOADCOMMUTATED BHEL
Functlon
FANGLAG Variable used to compensate lield firing algoritm

for phaseshift betweensourceside and field power'
The variable positive for lagging and negative for
leading.Resoiutionis 1 degree and range is t30o
Associated software variable and its relationship
to FANGI-AG is given below
FIELD PHASE ZERO E = (FANGI-AGi/360)*1024
FCDEI-AY Timer controllingthe delay to allow field to build

up before attemptingto drive start.
FCDELAY= delay time in seconds.
Resolutionis 1 and rage. 1 to 10 seconds'
to FCDELAYis given below.
FLD DELAY LIMIT = FCDETAY* FRQS
FCFNME Controlsnumber'of consecutivefield overcurmts

allowed. A penallyfunctionis implemented such
that 6 good firings followingan firing'
overcurrent
This allows recoveryfrom non- repetitivefaults.
FCFflME = numberof consecutiveovercurrents.
The resolutionis units and the range is 1 to 6.
The associatedsofhrarevariablesand its relation
to FCFTIMEis given below.
*
FLD FAULTPERIOD= (FCFflME-1) 6
FCGAIN Field current limit function gain. The gain is set

to affowa2"/olield currentlimitwith 3O%overdriving
flux. A value of 1OO is tYPical.
FCGAIN = required regulator gain
Resolution is 1 and range is O to 2OO'
to FGGAIN is given below.
FLD CURR GAIN = FCGAIN
+4
INVERTER
LOADCOMMUTATED BHEL
FCLIM Sets the trip level for the field overcurrentfunction.

The spilloverfield current limit value is set at 94%
of this value.
FCLIM = desired per unit field where 1 per unit
field is on the base of the field exciter'
Resolutionis. 01 and range is 0 to 2.0 per unit.
The associatedsoftwarevariableand its relationship
to FCLIM is given below.
FLD CUR LMT = FCLIM * 1024
FCLOSS Field loss setting for field loss fault function'

FCLOSS = desired per unit field loss setting.
Note that one per unit field is on the base of
the field exciter rating.
Resolution is .01 and the range is 0 to 1'2 per
unit.
to FCLOSS is given below.
* 1024
FIELD LOSS SETT]NG = FCLOSS
FCMAX Field thermal overloadfuncdon. Scales minimum

field thermal rating at zero speed.
Must be entired on the base of the field exciter.
Resolutoin is .01 and the rage is O5 to 1'2.
to FCMAX is given below.
MAX FLD LIME = FCMAX " 1024
FCMIN Field thermal overload function' Scales minimum

field thermal rating al zero speed.
Must be entired on the base of the field exciter.
Resolutionis .01 and the range is .05 to 1.2
The associatedsoftwarevarible and its relatioship
to FCMIN is given below.
MIN FLD LIME = FCMIN 1' 1024
Field thermal overload function. Used to enable

or disable the field thermal overload function.
"T' rue or "F"alse.
Possiblevalues for FCOLEN are
4-5
LOADCOMMUTATED
INVERTER BHEL
FCSLOP Variable used in field thermal overloadfunction

to define cooling effect as funtion of speed.
FCSLOP= DELTA PU field current.
Note the per unit base is the base rating of the
field exciter.
Resolutionis .01 and the range is ,01 to 1.2
per unit.
to FCSLOP is given below.
FLD SPD FACTORE= 16*[FRQMM/601 FCSLOP
FLAGAIN Variable used with the flux regulator routine to

set gain of flux adjust integratorto allow source
fire-as-early-aspossible.
FLAGAIN = required gain.
The recommended value is 1. The range is .01
to 2.0 with a resolutionof .01
The associatedsoftwarevaribleand its relationship
to FLAGAIN is given below.
FLUX REG ADJ G = FLAGAIN* 100
FLALEN Variableused to control enabling/disabling of the

fluxadjustintegratorto allowfire as earlyas possible
on the souce side.
FI-ALEN REGUI.ATORCONDITION
F disabled
T enabled
Only values of F or T are allowed.
to FLALEN is given below.
FLUXADJ MODEE= FLASENor SHL (FLALEN)
FLALIM Variable used with the flux regulator controlled

from source fire as early as possible regulator.
Fucntionis to limit the range of flux adjustment.
FLALIM = desired per unit flux.
Resolutionis.01 units.and the range is 0 to .50.
to FI-ALIM is given below.
FLUX REG ADJ LMT = FI-ALIM * 8254
+6
I
INVERTER
LOADCOMMUTATED BHEL
Name Group Functlon
FLASEN (FL) Variable used to control enabling/disablingof the

flux adjust a function of source voltage variations.
FI-ASEN REGUI.ATOR CONDITION
F disabled
T enabled
Only values of F or T are allowed
to FLASEN is given below.
FLUX ADJ MODE E= FI,-ASENor SHL (FLALEN)
(PT) "print status" routine to define

FLDPU Variable used in
the value of 1 per unit exciter current. The value
should be enteredin terms of actual exciter current
rating (in amps).
FLDPU = t?ted exciter current.
Resolution is 1.0 and the range 0 to 100.
FLEARLY (FL) Enables source fire-as-early-aspossible regulator

as a function of drive speed.
FLEARLY = desired per unit speed.
Resolutionis.0O1units range is .1 to 2.0 per unit
speed.
The associatedsoftwarevarible and its realtionship
to FLEARLY is given below.
SFAEAPR SPD ENABLE = FLEARLY*(1024160)"
FRQMM
"FLUX SETPOINTVS SPEED"
FLPBRKl (FL) Variaableused in
function in flux regulator. Sets beginning of first
slope. See -variable FLPMAX1 for profile.
FLPBRK1 = desired per unit speed.
Resolutionis .001 and the range is 0 to 2.000
per unit.
to FLPBRK1 is given below.
FLUX PROFILESPD BRK1 = FLPBRK1*(1024/60)
*FRQMM
+7
FLPBRK2 Variableused in "FLUXSETPOINTVS SPEED"

functionin flux regulator.Setstakeoverfor second
slope. See variable FLPMAX1 for profile.
FLPBRI€ = desired per units speed.
Resolutionis.001 and the range is 0 to 2.000
per unit.
The associatedsoftwarevariable and its relation
to FLPBRK2is given below.
FLUXPROFILE SPDBRl(2= FLPBRK2*(1024/60)*
FROMM
FLPLIM Variable speciffing flux level at top speed. See

variable FLPMAX1 for profile.
FLPLIM = desired per unit flux.
Resolutionis. 01 unists and range is 0 to 1.5.
The associatedsoftwarevariable and its relatlonship
to FLPLIM is given below.
FLUX PROFILE FINAL=FLPLIM*82S4
FLPMAXl Variableused in "FLUXSETPOINTVS SPEED"

functionin tlux regulator.Sets initialper unit flux
FLPAMX1= desired per unit flux
Resolution is .01 unilsand the rangeis 0 to 1.50.
to FLPMAXis givernbelow.
FLUX PROFILEMAX 1 = FLPMAX1*8254
FLPMAX2 Variableused in "FLUX SETPOINT VS SPEED"

function in flux regulator. Sets peak flux. See
variable FLPMAX2 for profile.
FLPAMX2 = desired per unit flux.
Resolutionis .01 units and the range is O to 1'50
to FLPMAX2 is given below.
FLUX PROFILE MAX2 = FLPMAX1*8254
+8
LOADCOMMUTATED
INVERTER BHEL
Name Group Functlon
FRFCCOMP (FR) Determinesamountof CCMNDthat is added to

FRSTARTfor the flux regulatorprecondition.
FRFCCOMP = numberof timesCCMNDis divided
by 2.
Resolutionis 1 and range is 1 to 7.
FRSCCOMP (FR) Determinesamountof CCMNDthat is added to

outputof flux regulatorfor determiningthe field
firing angle.
FRSCCOMP= pu of CCMND
Resolutionis .01 and range is .01 to 0.25 pu.
FLUXS (Mt) Usedin the startingroutinefromzero speed. Sets

the amountof flux requiredto transitionto segment
firing mode.
FLUXS = desired per unit flux.
Resolutionis.01 and the range is 0 to 2.0 pu.
to FLUXS is gMen below.
START FLUX E = FLUXS t' 2752
FRCLMP (FR) Sets the mar<imumadvance angle of the exciter

voltage controller. Generally will be set to 1 per
unit exciter volts. When set to some other value
the maximum RMS exciter voltage will be
approximately proportional to the value of this
variable.
FRCLMP = desired per unit output volts.
Resolution is.01 and the range is 0 to 1.2
The associatedsoftware variable and its relationship
to FRCLMP is given below.
FLUX REG OUT CLMP = FRCLMP * 255
FRGAIN (FR) Variableusedinthefluxregulatorto setthe regulator

integralgain for a nominal5 radianregulator. The
followingequationholds,
FRGAIN= U(63.68*Geq *ME1/)
Where Geq = equivalenttransfer gain from EVC
outputvoltageto flux feedbackintergratorvoltage.
MEV = maximumexciter volts.
Resolutionis .01 and the range is .01 to 2.00.
to (contd)
+9
INVERTER
LOADCOMMUTATED BHEL
FRGAIN is given below.

FLUX REG G2 = FRGAIN * 16384/FRQS
Source side nominal frequency. The variable is

used in various regulator gain and time constant
calculations. This variable only goes into effect
after resetting the processor.
Resolution is 1 Hz and range is 45 to 9O Hz.
Frequencyat which motor reaches rated voltage.

This variable is used in various regulator gain
and time constant calculations. This variable will
only affect the drive tune-up after resetting the
processor.
Resolution is 1 Hz and range is 4O to 90 Hz'
FRQMM Motor maximumfrequency.Should not be set less

than FRQM. ResetHMPG afier FRQMM changed.
FRQMM= desiredtop lrequencymachinewill run.
Resolution is 1 Hz and range is 40 90 Hz.
FRSTART Variable used to initializethe flux regulatorto call

for a value of excitervolts which gives approximately
the correct flux at start. ln forced commutated
mode when the flu< regulator is not active'
FRSTART = desired per unit output volts'
Resolution is .01 per unit and the range is 0
to 1.0.
to FRSTART is given below.
FLUXREGPRECONDITION=(FRSTART*S1 0) -255
Variable selecting the flux regulator stability time

constant. Normally the value is selected equal
to the machine field time constant.
FRTC = desired time constant (seconds).
Resolutionis.1 and the range is .2 to 10 seconds.
to FFTTCis given below.
FLUX REG Gl = 2O48 * FRGAIN * FRTC
+10
LOADCOMMUTATED
INVERTER BHEL
Name Group Fucntlon
HPPU (PT) Variableusedin the "printstatus"routineto define

thevalueof 1 perunitdrivehorsepower.Generally,
the per channelhorsepoweris used as the base
12 in pulse systems,
HPPU= rated channelhorsepower
Resolutionis 1.0 and the range is 0 to 10,000.
IDCPU (PT) Variableusedin the "printstatus"routineto define

the value of 1 per unit link currentin amperes.
IDCPU = rated link current(amperes).
Resolution is 1.0 and the range is O to 2,000.
INTOSTOL (Mt) Variableusedin testto determine thatf lux integrators

are balanced before enabling the load side
phase-lock-loop
INTOSTOL = desired setting (in per unit flux).
Resofutionis .01 and the range is 0 to 1.2 per
unit.
to INTOSTOL is given below.
INTEGRATOROFFSET TOL = INTOSTOL*1376
LIMARG (Mt) Variablecompensating load-sidefiring angle for

loadcommutating impendance.Adjustedto obtain
constantcommutationmargin angle.
LIMARG= per unit load commutaingreactance.
Resolutionis .01 per unit and the range is .03
to .30 per unit.
Theassociated softwarevariableanditsrelationship
to LIMARGis given below.
ALPH LD IMP MARG = 180,15*LIMARG
LKLIMD (PR) Sets allowableditferencebetweensource and load

side measurementsof link current. lf the difference
is exceeded then Commutation failure fault is
declared. LKLIMD - per unit and the range is
0 to 2.0 per unit.
to relationship to LKLIMD is given below.
lDc DTFFERENCELlMlT = LKLIMD "1024
+11
Name Group Functlon
Sets level of load currentwhich is declaredand

overcurrentfault.
LKLIML = desirecd per unit current setting.
Resolutionis.01 and the range is 0 to 2.0 per
unit.
to LKLIML is given below.
fDC LINK LMTLD = LKIML * 1024
LKLIMS Sets level of source curarentwhich is declared

an overcurrentfault.
LKLIMS = desiredper unit cunent seting.
Resolutionis.01 and the range is 0 to 2.0 per
unit.
to LKLIMS is given below.
fDC LINK LMTLD =LKLIMS" 1024
LKOCTIM Controlsnumber of consecutivesource overcurrents

allowed. A penalty function is implemeted such
that 6 good firings following a failure will cancel
a fauli firing. This allows recovery from
non-repetative faults.
LKOCTIM = number of consecutive overcurrents.
The resolution is units and the range is 1 to 6'
The associated software variable and its
relationship to LKOCTIM is given below.
*
tDc L|NK LMT PERIOD = (LKOCTIM-I) 6
LMARG Variableusedto set the commutationmarginangle

for the load. side. A fixed margin angle of 20
degrees is normallYused.
LMARG = desiredmargin angle in degrees.
Resolutionis 1 degree and the range is 0 to
30 degrees. The associatedsoftrare variableand
its relationshipto IAMARG is given below'
A L P H F I X E D M A R G L D = 1 3 7 6 *[ 1 + C O S
(18o-LMARGII
+12
INVERTER
LOADCOMMUTATED BHEL
LPLLTIM Sets time delay before a load phase lock loop

fault is declared following an error determination.
LPLLTIM= required time in seconds.
Resolutions is .01 seconds and the range is 0
to 1.5 seconds. The time delay will be as set
at top speed and is inverselyproprtionalto speed
otherwise.
to LPPT1M is given below.
PLL OUT OF TOL LD PERIOD = LPLLTIM*12
*FRQMM
Modifiesthe motorf lux integratorenor compensatioh

accordingto the time constant the flux integrator
in the NLIB pcb.
Values are available as follows:
"F" for .220 sec (standard config.)
MICOMP =
= "T' for .086 sec (optional config.)
MKPHASE Positionmode varible. Scaled in electricaldegrees.

this variable defines the numbeTof degrees that
the motor A-N voltage (-to+ transition) lags the
tachomter marker pulse when the motor power
range is 0 degrees.
Resolution is 1 degrrees and the angle is 0 to
360 degrees.
MKPHASE = MKPHASE
"print status" routine to define
Variable used the
the value of 1 per unit machine RPM.
MRPM = machine RPM at FRQMM frequency'
Resolutionis 1.0 and the range is 0 to 5000.
MTRFMIN Variableused in test to determineif the magnitude

of generator flux is adequate to enable the load
side phase lock loop,
MTRFMIN = desired setting (in per unit flux).
Resolution.01 and the range is O to 1.2 per unit.
The associatedsoftwarevariable and its relationship
to MTRFMIN in given below.
MTR FLUX MIN TOL = 2* 1376*MTRFMIN
+13
LOADCOMMUTATED
INVERTER BHEL
Name Group Functlon
MVPU (PT) Variableusedin the "printstatusnroutineto define

the value of 1 per unit load volts.
MVPU = rafed load volts.
Resolutionis 1.0 and the range is 0 to 5000.
OVCLIM (ov) madmumcurrrentlimitcalled

Variablecontrollingthe
for by the overvoltageregulator.A seftingis 1.5
per unit current.
OVCLIM= requiredper unit stator current.
Resolutionis .01 and the range is 0 to 2'O per
unit.
to OVCLIM given below
is
CUR REc LMT OWOI-1 = OVCLIM * 1024
OVGAIN (ov) variablecontrollingthe gainof the spillovervoltage

limit regulator. Presentlythis regulatoris set for
a crossoverof 10 radians.This resultsin OVGAIN
=2.4,
Resolutionis 1 units and range is 0 to 20.
Theassociated softwarevariableanditsrelationship
to OVGAINls given below.
OV VOLT REG GAIN = 256 * OVGAIN
OVSPIL (ov) Variable controllingthe setpoint of the spill over

voltage limit regulator. When used.
OVSPIL = Per unit load volts'
Resolution is .01 per unit and range is O to 2'O
per unit.
The associatedsoftwarevariablean its relationship
to OVSPIL is given below.
*
OV VOLT REG SPLOVER=1'1s * FRQM OVSPIL
owc (ov) Variablecontrollingan adjustablelag in the forwared

loop of the voltage limit regulator. The filter is
in the forward loop of the voltage regulator and
therefore, affects stability. The following table
shows the values available.
+14
LOADCOMMUTATED
INVERTER BHEL
Name Group Functlon
owc owc T(SECONDS) T(SECONDS)

(contd) 60Hz 50Hz
OH 0.01662 0.0199
1H 0,050 o.06
2H 0.1166 0.140
3H 0.245 0.30
4H 0.s166 0.62
5H 1.05 1.26
6H 2.116 2.54
7H 4.2s 5.O7
8H 8.52 10.22
9H 17.05 20.6
The recommended value is OVTC =6.

The associated software varible and its relationship
to OWC is given below.
OWOLT REG TC = OVTC
PLLMODE (Mt) Variableused with the load phase lock loop regulator
to determine the speed at which the phase lock
loop switches from 6 to 3 calculations per cycle.
PLLMODE = desired speed(Hz).
Resolution is 1Hz and the range is 1 to 90 Hz.
to PLLMODE is given below.
PLL SPD MODE 3 LD = 7200/PLLMODE
PLLTOL (PR) Sets mar<imumallowable error in load phase lock

loop. lf error is exceeded, then a phase lock
loop fault declared. PLlTOL=allowable error (in
degrees).
Resolution is its units and the ranges is O to
20 degrees.
to PLLTOL is given below.
PPLL ERROR TOL LD = p1-g1gL * (1024/360)
+15
II,IVERTER
LOADCOMMUTATED BHEL
Variableused in the print stafus routineto select

the data from the followinglist to be printed on
the door mounted printer. The number of the
informationto be printed is entered as data into
each variable. lf no data for a particularentry
is required,then it should be set to zero. Note
that the print- out will be formaftedin the order
of the PO variables with POl first.
0 No print out
1 Motor RPM
2 Speed reference (RPM)
3 Motor line current
4 Field current
5 Motor horsepower
6 DC link volts
7 DG link amperes
I Motor line volts
9 Source amperes
10 Source line volts
11 Source firing angle
12 Load firing angle
13 Motor power factor
14 Source power factor
15 Source l(/A
16 Current limit setPoint
17 Voltage limit setPoint
18 Motor kvars
19 Source kilowatts
Drive status messages

4-16
BHEL
'printstatusnroutineto
Variableusedin the
the auto print feature' ln this mode, the
prints the selected information at time intervals
selected by the variable
"T"rue enables function
POT.POE =
= "F"alse disables function
Variable used in the load side position mode

calculation. Sets a minimum fixed margin even
if current reading is near zero.
Resolution is 0.1 and range is O to 3'0'
POSF = Degrees margin.
ls related to the corresponding tuneup variable
according to the following equation:
POSE=2.84*POSF
RR6PAO Family of variables controlling the rate-oJ-t

1 of the ddve speed. selection of a particular
2 accelarationiate is controlledin the background'
3 Consultthe drive ladder diagramto determine
4 mode. Resolutionis 0.01% and the input range
5 is O.OO01 to 0.100 Per uniVsec.
RRGPA( ) = Per unit speed change/second'
The rated softwarevariable array is SPD RATE
ACCL 6P (o-s)
and is relatedto the correspondingtuneupvariable
accordingto the followingequation:
ACCLee 1o-s1= (RR6PA(o-s) * 1677720(FROMM
/60)/FROS
RR6PDO Family of variable controlling the rate-of-t

1 of the drive speed. Selection of a particular
2 deceleration iate is controlledin the background'
3 Consultthedriveladderdiagramto determinemode'
4 Resolutionis 0.01%an the input range is 0.0001
5 to 0.100 per unit/sec.
RRGPD1 1 = Per unit speed change-/-second'
The rated softwarevariable array is SPD RATE
DECEL 6P(o-5)
and is relatedt6 tne corresponding tuneupvariable
according-oeto the following equation:
" --,
DECEL 1o-s1= {RR6P(0-5)} 1677720
(FRAMM/60)/FRQS
+17
LOADCOMMUTATED
INVERTER BHEL
Name Group Function
RRl2PAO (RR) Family of variable controlling the rate-of-change

1 of the drive speed. Selectionof a particularspeed
2 accelarationrate is controlled in the background.
3 Consultthedriveladderdiagramto determinemode.
4 Resolutionis 0.01% and the range is 0.0001 to
5 0.100 per uniVsec.
RR12PA ( )=Per unit speed change /second.
The rated software variable array is SPD RATE
ACCL 12P(0-s)
and is relatedto the correspondingtuneup variable
according to the following equation:
ACCL 12P(0-s) = {RR12PA(0-5)}* 1677720
(FROMM/60)/FROS
RRl2PDO (RR) Family of variable controlling the rate-of-change

1 of the drive speed. Selectionof a particularspeed
2 decelarationrate is controlled in the background.
3 Consultthedriveladderdiagram to determinemode.
4 Resolutionis 0.01% and the input range is 0.O00'l
5 to 0.100 per uniVsec. l
RR12PD0 = per unit speed change/second. ]
The rated software variable array is SPD RATEI
DECEL 12 P (0-5) and is relateddto thel
correspondingtuneup variable according to thel
following equation:
DECELI2 P (0-s)= {RR12PD (0-5)} * 16777201
(FRQMM/60)/FROS I
RRBPO (RR) Selectsthe regions of drive speed where different

1 acceleration/decelerationrates may be selected.
2 The resolution is O.1o/oand the range is 0 to
3 2.0 per unit speed. RRBP ( ) = desired per unit
4 speed
The related softwarevariable is SPD REF BREAK
PO|NT (o-4)
The relationshipbetween the variable is defined
below:
BREAKPOINT( )= RRBP (l ), 1024* (FRQMM/60)
RRMAX6P (RR) Maximumspeed referenceclamp active in 6 pulse

operation.
RRMM6P = Desired per unit speed where 1 per
unit speed is defined by FRQMM.
Resolutionis 0.1% and the range is O to 2.0p.u.
The associatedsoftwarevariableis SPD REG REF
MAX6 PE
The relationshipbetweenthe variable is REF MAX
6 PE = (RRMAX6P) " 1024 * (FRQMM/60)
+18
RRMAXL Variable controlling maximum speed reference

scaling in the following speed modes:
Mode Defintlon
3 Local volts ref-fwd operations only
RRMAXL = Desired per unit speed where 1 per

Resolutionis 0.1% and the range is 0 to 2.0
per unit speed.
The related software variable is SPD REF MAX
LMT This is related to the subject variable by
MAX LMT = RRMAXL * 1024 * (FRQMM/60)
RRMAXR Variable controlling maximum speed reference

Mode Deflnition
0 Remote volts ref-fwd operations only
1 Remote 4-20 mA reference
2 Remote volts ref-reversing operation
4 UP-down contact closure mode
RRMAXR = Desired per unit speed where 1 per

Resofutionis 0.1% and the range is 0 to 2.0
per unit speed.
The relatedsoftwarevariable
is SPD REF PROCESS
MAX
This is related to the subject variable by
PROCESSMAX = RRMAXR"1024 * (FRQMM/60)
RRMINL Variable controlling maximum speed

Mode Deflnition
3 Local volts ref-fwd operations only
RRMINL= Desiredper unit speedwhere 1 per

unit speed is definedby FRQMM.
+19
INVERTER BHEL
LOADCOMMUTATED
RRMINL Resolution is 0.1% and the range is 0 to 2'

(contd) per unit sPeed. aFF ',,
The related softurare variable is SPD REF MIN
LMT
This is related to the subiect variable by
t' 1024 * (FRQMM/60)
MIN LMT = RRMINL
RRMINR Variable controlling minimum speed reference

Mode Deflnltlon
0 Remote volts ref-firvd operations only
1 Remote 4-20mA reference
2 Remote volts ref-reversing operation
4 Up-down contact closure mode
RRMINR= Desiredper unit speedwhere 1 per

unit speed is defienedbY FRaMM'. -
Resolutionis 0.1% and the range is 0 to 2'
per unit sPeed. . ÂA hr
The relatid sofrtwarevariable is SPD REF
PROCESSMIN
= * 1024 * (FRQMM/60)
PROCESS MIN RRMINR
RRMODE Variableselectingthe speed referencefor normal

operation.That ii the modewhichwill be selected
itihedriveis notinlocal,turinggear,or in emergency
stop.The value of the RRMODEdeterminesthe
mode accordingto the following:
RRMODE=0
O to f OV unipolarreferenceproportionalto speed
throughthe iemote speed referenceinput-votage
source.
RRMODE=1
rt-20mAcustomerreference through the remote
reierenceinput. This is a unidirectionalmode'
RRMODE =2
Bipolar 10 volts reference through remote
ieierence inpr"n. Allows reversing operation'
+20
INVERTER
LOADCOMMUTATED BHEL
Name Group Functlon
RRMODE RRMODE=3 l
(contd) Selects local speed reference and non-reversing
operation onlY.
RRMODE =4
Allows control of speed reference by raise/lower
interlocks via l/O module'
RRMODE = 5
Selects the turning gear speed reference set by
RRTG.
RRMODE = 6
Selects the reference set by variable RRMINR
RRTG (RR) Varibalesetting drive fixed speed when speed set

point mode 5 is selected. This is normally used
for turing gear function'
RRTG= Desired per unit sPeed
where 1 per unit is defined bY FRQMM
Resofution is. 1% and range is 0 to 1'2 per
unit speed.
The relatod software variable is
SPD REF TURNING GEAR
The following relationshiPholds
* *
TURNfNG eenn = RRTG 1024 (FRQMM/60)
SIMARG (Ml) Variablecontrolling source-sideretard limit as

a functionof current. Compensatesthe firing
as a functionof link currentfor sourceimpedance'
SIMARG= pel unit commutatingimpedance'
Resolutionis 0.01 per unit and the range is 0'01
to 0.25 Per unit'
The associatedsoftwareand its relationshipto
SIMARGis give below.
* (XPU)
ALPH SRC IMP MARG = 67
+21
.\.
SMARG Varible controllingthe fixed source side margin

when invating. Notmal margin is 20 degrees.
SMARG = desired fixed margin in degrees.
Resolution is 1 degrees and the range is 0 to
30 degrees
to SMARG is given below.
ALPHFIXEDMARGSRC=25611..COS(1 8Odegrees
sMARG)I
SPLLT1M Sets time delay before a source phase-lockloop
fault to declaredfollowing an enor determination.
SPLLTIM= required time in seconds.
Resolution is .01 seconds and the range is 0
to 1.5 seconds.
to SPLLTIM is given below.
PLLOUTOF TOL SRC PERIOD=SPLL'IIM*6*FRQS
SQFEC , (sso) Family of flags that enable various test or operating

modes. Setting a bit to "1" enables the designated
function. The flag's encoding is as follows:
bit Function
0 enables testing of field exciter during

SELFTEST
1 - enables operating of field exciter without

running drive
2 - select dc field exciter operation

('O' = ac excitef)
sQMcH | (so) Selects the master channel when two channels

a r e c o n n e c t e di n a 1 2 p u l s e m a s t e r - s l a v e
configuration.
SQMCH = 'F" alse (selectschannelsas slave)
= "T' rue (selectschannel as master)
+22
INVERTER
LOADCOMMUTATED BHEL
Name Group Functlon
SQOPTl (so) This is a family of flags which control the enabling

of various options in the ladder logic sequencing
program.
The flags are encoded into SQOPTI.
"1' state masks out of
Setting a variable to th€
the function so that ladder diagram logic does
'Oo allows
not affect the sequencing. Setting to
the function to affect the sequencing. Refer to
the ladder diagram logic. The value of SQOPT1
is obtained by setting ls and 0s in the bit positions
and converting the binary number obtained to
decimal.
SQOPT2 (so) This is a family of flags which control the enabling

of various options in the ladder logic sequencing
program The flags are enabled into SQOPT2.
u1' state masks ottt
Setting a variable to the
of the function so that ladder diagram logic does
nO' allows
not affect the sequencing. Sefting to.
the function to affect the sequencing. Refer- to
the ladder diagram logic. The value of SQOPT2
is obtained by setting ls in bit positions and
convertingthe binary number obtained to decimal.
SQDRTST (so) Familyof flags that enablevarioustest operating

'1' enablesthe designated
modes. Settinga bit to
funciion. The flag encoding is as follows.
bit Function
o disables intenupts to l/O can be tested
1 enables testing.of UO relay outputs
2 enables crowbar test mode
3 enablesdeterminationof degrees tach

marker lags Van
4 enablesuse of tach for high statingtorque

(positionregulation)
5 enables use of tach for speed feedback

in the speed reg. calc.
may want to defeat the speed regulator

error filter because SRNFTC filters tach.
+23
ilI
SQDRTST 6 - enablesuse of softwareon SEMs

(cont$ HTCA (i.e. lrom A sems)
bits 4.5 must be "0" (mustdo a handreset

if changed)
8 - disablefield exciter card usage (should

a microprocessor reset if changed)
9 enablesseries 12-pulsesource-side
(should do a microprocessor reset if
changed)
A 1- slave leads masterfor series 12

liring
lagsmasterforseries12-pulsefiring
O-slave
(30')
bit 9 must"1" (shoulddo a microprocessor

reset if changed)
Bit 7,8,9,4 apPliesto LCL MEM onlY
SQPLTIM Variable setting the delay after a loss of source

power is sensed and before a power loss fault
is declared. The time delay is a based on
backgorund program executions and is
approximately 3 milliseconds per pass.
SQPLIM = (time delay)/3 E-03
The resolutionis l count and the range is 0 to20'000.
to SQPLTIM is given below.
POWER LOSS TIMER = SQPLTIM
Selectsexciter mode of operationfor slave converter

in 12 pulse system.
SQRA ="F'alse slave exciter does not operate
=nTorue slave exciter operates
SQSPl Per unit speed at which MAMS (motor above min

speed) picks-up.
SQSPI= per unit speed based on FRQMM
Resolution is 0.001 and range is 0 to 2.O.
Associatedsoftware vadable : SPD POINT E(1)
= SQSPI * 1024* FRQMM/60
+24
INVERTER
LOADCOMMUTATED BHEL
SQTMRl Timers used in the drive sequencing module to

SQTMR2 implement ladder logic tunctions. The defintim
SQTMRs of each timer's use is given in the background
SQTMR4 program. Note that the base for the counter
SQTMR5 is the source -side crossover interrupts.
SQTMR6 SQTMR= setting (in seconds)
The resouftion is 0.1 seconds and the range
is 0 to 20 seconds.
to SQTMR is given below.
*
BKGND TIMER ( ) LIMIT = SQTMR rRQS/1o
SRCLFC Speed regulartorquecommand limit when drive

operationis in one of thelorced-commutedregions'
A typical value is.2 PU torque'
Resolutionis 1% and the range is 0 to 2.0 per
unit.
The associatedsoftware variable by
CURLMTt=SRCLFC'1024
sRcLsc Speed torque command limit when drive operation

is in selfcommutation.
A typir:al value is 1.0 PU torque.
SRCLSC = Desired per unit cunent.
Resolution is 1% and the range is O to 2.0 per
unit.
SPE REG CURLTI,T2
CURLMT2=SRCLSC*1024
SRERRF Variable controlling the selection of the speed

regulator sPeed enor filter'
RERRF break frequencY

60 Hz souoe
0l-l filter is bYPassed Fifier is

bYPassed
1H double d' 17 rd 14 and 14 rad
2H double at 4O rad 28 and 28 rad
+25
LOADCOMMUTATED
INVERTER BHEL
Name Group Functlon

SRERRF The related software variable is SPD REG ERR
(contd) FILTER whose value is equivalent,
SRETOL (SR)) Variablesettingthe allowablespeederror (difference

between reference and feedack). lt this error is
exceeded. A signal to initiate an "EXCESSIVE
SPEED ERROR" alarm is generated.
SRETOL = Desired 7o speed error where 1
per unit speed is speed at 60 Hz
The associated software variable is
SPD REG DELTA TOL
The relationship between the variable is
DELTA TOL = SRETOL * 1024 * (FRQM/60)
SRGAIN (sR) Variable setting the speed regulator gain. The

following equation definep the required gain:
(6.2E-7x(N')x(WK") 60
-,-_ * - -_
(HP)xFl) FRQM
N = rated motor rpm

Tr= reoulatorresoonsetime
WK2=tortaldrive WK2 at motor shaft
HP=driveHP/channel
Resolutionis 0.01 and the range is O to 2OO.
SRLI.ADJ (SR) Variable for selecting the speed feedback time

constant. This time constant is normally
coordinatedwith the speed regulator crossover
desired to give critical damping. (Usually SET
FOR.94 RAD).
+26
LOADCOMMUTATED
INVERTER BHEL
SRLISDJ Spd reg T.C 60Hz T.C SoHz SRLLADJ

(contd) crossover
OH
1H
34.25 .0292 .0243 2H
3H
4H
3.80 .2629 .2191 5H
.s30 .4417 6H
1.064 .8867 7H
software variable
SPD REG LEAD LAG ADJ
takes on values equivalent to SRLI-ADJ and is
directily in the software
SRMN(R Maximumspeed referenceclamp.

SRMA)(R=Desiredper unil speed where 1 per
unit speed is the motor rated speed.
Resolutionis 0.17oand the range is 0 to 1.2
per unit.Theassociatedsoftwarevariable is SPD
REG REF MAX LMT
The relationshipbetween the variables is
REF MAXLMT = SRMAXR1'1024* (FRQMM/60)
SRMINR Minimumspeed referenceclamp.

SRMINR=Desired per unitspeedwhere1 per unit
speeed is the speed at 6OHz.
Resolutionis 0.1% and the range is 0 to 1.2
per unit.
The associatedsoftware variable is SPD REG
REF MIN LMT
The relationshipbetween the variables is REF
MIN LMT = SRMINR * 1024 * (FRQM
+27
SRNFTC Time constant of the double pole noise filter on

he tach speed feedback. Used to remove noise
and smooth coarsely calculated data at lower
speeds.
SRruftO=Oesired time constant(in secs)
Resolutionis 0.0001 seconds and ranges is .0084
to 1 .
SPD FIL TEMP=SRNFTC * FRQS/S
Numberof tach pulsesper mechanicalrevolution

SRTACH=#pulses per rev.
Resolutionis 1 and the range is 120 to 3600.
Variablesettingthe locationof the speedregulator

'Zero' for stabilitYcomPenstion.
SRTC=Desiredtime constant where the time
constant is specified in seconds.
Resolutionis 0.01 secondsand the range is 0.05
to 3 seconds.
Softwarevariablesrelatedto SRTC and SRGAIN
are:
SPD REG G1 and SPD REG G2
The following relations hold:
-G1=8f (SRGAIN)* (SRTC)
-G2=1o24* (SRGAINV(FROS)
Where FRQS = sourGeline frequencY
STHRUTIM Controlsnumber of consecutivecommutation

failuresallowed.A penaltyfunctionis implemented
such that 6 good firings following a failure will
cancel a fault fidng. This allows recoveryfrom
non+epetitivefauits.
STHRUTIM=number of consecutiveovercurrents.
The resoutionis units and the range is 1 to 6.
The associatedsoftwarevariable and its
to FCCOUNT is given below.
SHOOTTHRU CNT=(STHRUTIM-1)*6
+28
LOADCOMMUTATED.INVERTER B}IEL
Name Group Functlon

STIM (Ml) Used in motor starting strategy to set the time
lor one cycle.
Resolution is.l second and the range is . 1 to
6 seconds.
The relationship to the software variable is given
below.
TRANS START FREQ E=181/STIM
SVPU (PU) Definesthe of 1 per unit sourcevoltage. Used

in "print status" routine.
Resolutionis units and the range is 0 to 5000
volts.
SWINDTOL (PR) Controls the allowable tolerance on generator flux

ware unbalance before a shorted winding fault
is declared.
SWINDTOL=desiredper unit flux error. Resolution
is 0.01 and the range is 0 to 1.2 per unit.
to SWINDTOL is given below.
SHORTEDWl NDING FLUXTOL=SWINDTOL*1361
TRSPD (Mt) Sets the transitionspeed for entering

self-commutiationmode.
TRSPD=desired per unit speed.
Resoulationis 0.001 per unit and the range 0
to 1.2 per unit.
Where 1 per unit speed is the drive speed at
60H2.
The associatedsoftware variableand relationship
to TRSPD is given below.
t-AC MODE3 TRAN SPD = TRSPD * 1024 *
(FROM/60)
QCBTOL (Ml) Varible used by Factory QC Personnel.

QCMAX
QCMIN
QCVTOL
+29
INVERTER BHEL
LOADCOMMUTATED
Per unit summationof the generator

axis leakage reactance and magnetizing reactance.
Used to calculate the rotor pow€r angle when
load-side is operating in position'mode (LMODE
= 71. Used only when a tach is provided for
speed feedback.
XQ=X1 + Xaq (in per unit)
Resolution is 0.01 and the range is O to 1'6'
The assoicated sotware vadble is given below'
XQ E=XQ*47
PUBLTCVARIABLES
Public variables are softwarevariablesthat can be accessed by name

r.rsingthe LCI diagnosticmonitor(describedin Chapter5). These variables
".n i. Uyt". Intlger, or bit cod.edquantities. The byte variablesshow
togi. "t"t6t in the lequencing. The LGI diagnosticmonitordisplaystheir
u"]r", as T (true) oi f 6aise1. Integer variables show the value of
piolortionat qdantiies(such as voltage or current) used. in, the regulator
"otrr.t". fne UCtdiagnosticmonitordisplaysbit-codedvariablesas positive
decimal numbersthai must be convertedto represent a logic state or
operatingcondition.
The system elementarydiagram- prwides a completelist of publicvariables

Jong'wih their difinitions. Mosi of these variablesappear in either the
so'ftri.re ladder or the reguldor block diagrams, Located in the system
elementarY.
+30
INVERTER
LOADCOMMUTATED BHEL
4.2 DESCRIPTION OF PUBUC VARIABLES
AI.ARM
EquivalentsoftwareVariable- ATARM-WORD
Variabletype- WORD
Scaling- BIT CODED
modulesto the background
usedto passalarmstatessensedinvarioussoftware
Delinition- Variable
(sequencing)program. The bits of the variableare coded as follows:
Bit O Field inPut volts not Present

1 FlotorPositionstart failed
2 llO addressingProblem
3 DivisionbY Zero
4 lmproperrunningmode for UP
5 runningmodefor UP
lmProPer
6 Numericaloverflowin calculation
7 interruPtservice
Non-maskable
8 lmproperinterruptrequestpn HLCB
9 Systemtime interruPtrunning
A InterruPtrequestunresolved
B spare
C Wflag
D Fieldthermalmodel
E Loss of sPeedreference
F SPare
'RESET'lS OPERATED'
The AI-ARMwill remainset until the
4-31
BHEL LOADCOMMUTATED
INVERTER
ALPHFLD
Equivalent software variable- ALPH-CMND-FI.D

Variable type- INTEGER
Scaling- + 255 counts .> APHA = 0 degrees
-255 counts -> ALPHA= 180 degrees
Definition - sets the firing angle of the feld exciter voltage controller. lt is normally calcutated
by the Flux regulator but may be set by RAc if the Flux regulator is opened.
ALPHLD (
Equivalent software variable- ALPH-CMND- U) r - €
Variable type- INTEGER f
Scaling- + 256 counts - ALPHA = 0 degrees 4
*
.255 counts - ALPHA = 180 degrees
Definition - Sets the firing angle for the lod side power converter. During motoring operation,
ALPHA ranges between 90 and 180 degrees. Values between 0 and 9o indicated
regenerativemode. The load angle control regulator calculates variable value in self
-commutationmode when the phase'lock-loopis locked. In seg_firemode, the variable G
is not calculated. l
ALPHSRC
Equivalent software variable- ALPH-CMND-SRC

Scaling - + 256 counts -> ALPHA = O degrees
-255 counts-> ALPHA = 18O degrees
Definition Sets the value of the source side power convertertiring angle. The variable is cdculated
in the source current regulator.
4-32
C
f
f INVERTER
LOADCOMMUTATED BHEL
i ALPHSRCO
f
Equivalent software variable- ALPH-SPISVR-SRC
variable type- INTEGER

(
SCAUNG - 0 TO 97 counts
Definition- Wtrenthe source side angte reachesfull advance,the current regulator can maintain
current by advancingthe load side firing angle.Thisis known as the crosstie regulator.
The excess angle comrnand is set in ALPHSRCOfor transmissionto the load angle
regulator
BBFS
Equivalentsoftwarevariable- BBFS
Varibletype - BVTE
Scaling- TorF
Defnition- Bottomblowerselected.Thisvariablerepresentsthe state of the blowerswitch input
from the power conversionbridge. lt is used in the blower alarmlfaultlogic.
BFDIFSW .
Equivalentsoftwarevariable- BFDIFSW
Variable type- B|TE
SCAI.JNG- TorF
Definition- Bridgedifferentialpressureswitch. Representsthe state of the power conversion
Usedin thebackground
switch.Thisis an optionalfunction.
bridgediffersrtialpressure
prograrnfor fault alarm monitoring.
BFIIf
VariableType- S/TE
Scaling- TorF
Deftnition- Bridgefilter fuse indication.Representsthe state of the interlocksoperatedby the
'
ac and dc filter fuses. Used in the backgroundprogramfor faulValarmmonitoring'
4-33
BHEL LOADCOMMUTATED
INVERTER
BFILF
Equivalent software variable

variable type- BYTE
Scaling T or F
Definition - Bridge filter fuse indication. Representsthe state of the interlocksoperated by the
ac and dc filter fuses used in the backgroundprogram for faulValarmmonitoring.
BFNDR
Equivalentsoftware variable- BFNDR

Variable type- Br/TE
Scaling- TorF
Definition- Bridge fan door compartment open indication. Used in the background program \-
for faulValarmmonitoring.This is an optional function.
CBMODE
Equivalentsoftware variable- CROWBAR MODE

'
Variable type- BYTE
Scaling- TorF
O.t'tign- This variable indicateswhen the load side is operating in crowbar mode which is
a test mode where current is circulatedthrough diametricallyfired load side thyristors
bypassing the motor. Crowbar mode is obtainedthrough the monitor tuneup mode.
CCMND
Equivalentsoftwarevariable- CUR_REG_CMND
Variabletype INTEGER
Scaling- 1024 counts -> 1 PU motorlng torque
-1024 counts -> 1 PU regenerativetorque
Definition- Variablecalculatedas the output of the speedregulator.ltis then separatedinto two

parts to controlthe drivetorque. Whenabovethe minimurncurrentcurrentlevel,
currentis increasedto increasetorque. Belowthat level,the load side powerfactor
is modifiedto controltorque.
4-34
INVERTER
LOADCOMMUTATED BHEL
CFBK
Equivalent software variable- CUR-REG-FDBK
Variable type INTEGER'
Scaling- 1024 counts '> 1 pel unlt cunent
Definition - Current feedback is derived in hardware from CT signals and read into the software
via A/D converters. During forced commutated modes,currentfeedback is a function
only of source.sidecurrent read 3Odegreesaftersource firings. During self commutated
modes, current feedback is calculated from the average of source current read 3O
degreesfrom firingsand load currentread at sourcefirings.This more complex scheme
minimizesthe effect of operation near beat frequencies'
cFc
\- i Equivalentsoftwarevariable CFC
' variabletYPe- RYTE
Scaling- T or F
I
is the field contactorcontrolsignaldevelopedin the back-
gdi1iti,orr- Closefield contactor.This
groundsequencingProgram.
! l
, I
CHRNG
Equivalent software variable- CHAI'INEL-RUNNING
Variable type- F/TE
Scaling- TorF
Definition -The channel running variable is passed between master and slave channels to in-
dicate the other's status. lt is used in the background sequencing Program to determine
the mode of operation. This variable seryes no function on 6 pulse drives.
t,t I EttM
Equivalent software variable- INTEGRAL-TERM
Scding - not aPPllcable
Definition - This variable representsthe product of the current regulator integral gain and the
current summing iunction error.
4-35
BHEL LOADCOMMUTATED
INVERTER
CPTERM
Equivalentsoftware variable- PROPORTIONAL_TERM

Scaling - not appllcable
Definition
This variablerepresentsthe product of the current regulatorproportionalgain and

the latest current summing junction error.
CRERR
Equivalentsofttware variable CUR_REG ERR
Variable type INTEGER
Scaling 1024 counts -> 1 PU error \r
Definition Differencebetween current regulator referenceand feedback after after being limited L
by the current regulator error clamp.
CROUT
Equivalentsofrryarevariable CUR-REG-OUTPUT
Variabletype - TNTEGER
Scafing- 22528 counts max
range+ or -22528
Definition- Currentregulatorcontroloutput.Controlssourcefiringangleto full advanceand then

advancesload side angleto maintaincurrent.
CRSTAR
Equivalent software variable- CUR_REG_STAR

Scaling- 1024 counts - > 1 PU cunent
Definition Current regulator reference from speed regulator after being limited by the current
'lower
limit function.
4-36
f
{
( INVERTER
LOADCOMMUTATED BHEL
CURLL
Equivalent software variable' CUR-1OWER-LI|T

Vlariabletype- INTEGER
Scaling- 1024 countg. > 1 Pt current
Definition- Gurrentminimumlimit. The minimumvalue of currentlower limit fixed by a tuneup
variableto maintaincontinuouslinkcunent.Thevaluemaybe raisedby the overvoltage
regulatorwhen r.equiredto limit motor volt4e.
CURRCMD
@uivalentsoftwarevariable' CUR-RATE-IflT-CUND
\lariable type - Ii|TEGER
Scaling - l0il4 countr . > lPU curent
Definition - Glrent referenceafier being rate limited. The rate of referencels limited to 25 PU
I per secondwhilein self-commutation mode.No limit is appliedin force'commutated
mode.
(
(
(
DCL
(
Equivdent sothvae \rariabl€- DCL
(
. \AdSle type' BYIE
.t
Scaling T or F
!
ii
I Definition- Backgroundsequenclngvarlablewhose state ls determined by comparingsource
cunent 4ainst the drive cunent limit. True when the drive is operatingin current
limit.
T
' \--|
I
I
ESPDRO
; Equivdent software variable- ESPDRO
i \rbiable type- BTTE
(
I Scaling - TorF
i Definition - Brckground sequencinginput. When true initiatesan €merg€ricyspeed reduction to
'
mlnimumoperatlngspeed.
I
4-37
BHEL INVERTER
LOADCOMMUTATED
ESTOP
Equivalent software variable- ESTOP
Variable type- BYTE
Scaling- TorF
Definition -Background sequencing variable. True when an emergency stop input is received
from the l/O module.
FLDCN
Equivalentsoftwarevariable- FLDCN
'BYTE
Variabletype-
Scaling- TorF
-
Definition- Signalrepresenting the stateof the field contactoras determinedfrom an determined
from an auxillaryinterlockinput, Used.in the backgroundsequencingprogram'
FLDCUR
Equivalent software variable- FLD-CUR
Scaling - 1024 counts - > 1 PU fleld current
Definition - Signal representing the current transferred to the exciter via the voltage controller'
l,Jsedfor field protectirre functions.
FLDEMODE
Equivalent software variaable - FLD-E(C-MODE
Variable type- BYTE
Scding- T OR F
test
Definition - Field exciter test mode. When true the field contactor will be close, the local
reference will be redirected to control the field exciter angle command, and the field
interrupt will be enabled.
4-38
INVERTER
LOADCOMMUTATED BHEL
FLFLT
Equivalent software variable- FIELO-LOSS-FLT
Variable type- BYTE
Scaling- T or F
Definition- Tiue when lield l.,s> tduli is present.
FLTWD
Equivalentsoftware variable- FAUIT - WORD
Variable type- WORD
Scaling- blt coded
Definition- Faults, sensed by the f<-'regroundprograms,areencoded into FLT\{D for transmission

to the background. The bits are defined as follows;
Bit 0 Field current unlalance
1 Field overcurent
2 shorledwinding detected
3 DC link overcunentsSRC
4 DC link overcurrentU)
5 IDC sourceshoot thru
6 IDC LOADshoot thru
7 snare
S Source PLL fault
9 Load PlLfault
A Field DC overvoltage fault
B Stack fault
C Failure to start
4-39
BHEL LOAD COMMUTATEDINVERTER
D EEPROMtransfer failure
E Spare
F Spare
FLUXADJE
Equivalentsoftwarevariable- FLUX-ADJ-ERR
Variabletype- INTEGER
Scaling- 256 counb ' > 18Odegrees
Definition- Error signal for FL[-D(adiust function'
+
FLUXADJ.
r
Equivalentsoftwarevariable- FLUX-ADJ r
Variabletype- INTEGER q
Scaling- 82511counts ' > lPU flux ,.
Definition- Output of flux adiust function used to modifylhe flux profile. i
t
FLUXERRA
Equivalent software variable- FLUX-REF-ADJ-IF
Scaling- 8254 counts ' 1 PU flux
Definition- Variablewhich reducesthe flux setpointwhen the field current limit function is active;
that is, when the field current limit set point is exceeded,the flux setpoint is reduced
to avoid excessive field current.
FLUXERR
Equivalent software variable- FLUX-REG-FDBK
Scaling- 8254 counts ' 1 PU llux
Definition- Error signal for flux regulator after being clamped.
4-40
l; (
(
FLUXFBK
BHEL
Equivalent software variable FLUX_REG_FDBK

I
Scaling 8254 counts -> 1 pU flux

Definition Feedback signal for flux regulator. Derived by reading the motor phase peak ilux.
FLUXREFL
Equivalentsoftwarevariable- FLUX-REG-LMT
Scaling- 8254 counts - > 1 pU llux
Definition- Limitvariableon flux setpoint.Limitsreferenceas a functionof motorvoltageto prevent
motor overvoltage
FLXSP
Equivalentsoftwarevariable- FLUX_SP
Variabletype- TNTEGER ;
Scaling- g254 counts - 1 pU flux
qeqggn- Referenceto flux regulator.Calclated as a functionof the motor flux profle,source
flux programmingfunction,and fre-as-early-aspossibleregulator.
FLXSRCT
Equivalentsoftware variable- SRC FLI,IXTST

Scaling- 1192counts . 1 PU flux
Definition- Test input to functionwhich programsthe flux setpointas function of source flux.
The input is used to simulatechangesin the source flux.
FIJSRC
Equivalentsoftwarevariablel- FUSRC
Variabletype- TNTEGER
Scaling- 1192 counts - > 1 pU ltux
Definition- Sourceflux read in sourcecrossoverroutine.Theparticularphaseread is Fc which
corespondsto motor voltageVa-c
4-41
BHEL LOADCOMMUTATED
INVERTER
FIJOV
Equivalent oftware variable- FLUX-UM-0V
Variable type' INTEGER
Scaling- 8254 counts '> 1 PU llux
Definition- Variablerepresentingthe value of flux which, at a given speed, will give rated motor
volts. Used as a limit on the value of flux which can be regulated. The variable
is calculated in the overvoltage regulator.
FSTEP
Equivalent software variable FLUX-REG-STEP
Scaling- 8231 counts'> 1 PU flux
Definition- Variable used to step the flux regulator when tuning the transient response.
GTSTM
Equivalentsoftwarevariable GATE-TEST-MODE
Variabletype BYTE
Scaling T or F
Definition Whentrue the controlis operatingin Gatetest Modewherethe controlis synchronised
to a &phse osillatorand the thyristorgate drive can be malyzedwithout the need
for high voltageapplication.
HITQ
Equivalent software variable HI_TQ
Variable type BYTE
SCAUNG. TorF
Definition When true, control is operating in high torque mode. This is a special setup for
drives requiring high starting torques.
4-42
INVERTER BHEL
LOADCOMMUTATED
ILD
Equivalent software variable- IDC UNK-LD
Variable tYPe- INTEGER
Scaling- 1024countg' > 1 PU current
Definition- D-c link current as read bY the load

side CTs
INVUM
Equivalentsoftwarevariable- INVUM
VariabletYPe- WORD
Scaling- lt coded
the sourceand load converterswill be set
Definition- Vvhenany bit of the variableis non-zero,
fzult trip and may recoverto
to fire at inversionlimit. The drive will not necesarily
normal operation' The bits are coded as follows:
Bit 0 Dtfferentialcurrent Jod
1 ffierential cuneni 'source
t 2 Spare
Spare
Field over voltage
shutdown flag
Source dc link orrar current
W flag
Startup llag
Spare
Load dc link over current.
SFI-AGsource
SFI-AGload
D Spare
4-43
- "-
l*@*--
BHEL LOADCOMMUTATED
INVERTER
E Field over current
F Stack fzutt
tRsc
Equivalentsoftwarevariable- IDC UNK-SRC
Scaling- 1024 counts . > 1 PU cunent
Definition- D-C link currentas measuredby sourceside CTs
KVAR
Equivalentsoftware variable- I(\/AR_DA

Scaling- 255 counts - > 1 pU Source I(VAR
Definition- This variablerepresentsthe l(/AR dawn by LCI from the line. lt is clampedto 0.5
PU maximum
LBKRS
Equivalent software variable- LBKRS

Variable type- BfTE
Scaling- T or F
Definition- Variablerepresentingthe status of the source side switchgear.Usedin the background
sequencing progranr.
LMODE
Equivalent software variable- LMODE

Variable type- S/TE
Scaling- blt coded
Delinition- Variable which represents the load side firing atgorithm being used. Values are
as follows:
4-44
9t
f
t INVERTER
LOADCOMMUTATED BHEL
a VAIIJE FUNCTION
I
o look startidle mode
a ;
i 1 segment firing
2 closed loop forced {ommutated mode
3 self-commutatedmode
4 crow bar mode
5 Dummy
6 t oa{ side open loop firip
7 Fgrced commutated mq{e as q function of position counter
8 Using tach positiop at low ppeed
LOCAL
Equivalentsoftwarevariable- I.oCAL
Variabletype EYTE
Scaling- T or F
Definition- tndicatesthat the drive is under c introl of the local operator'sdevicesmounted
on the Uo module
LSPD
Equivalent software variable I-OWER_SPD
Variable type BYTE
Scaling T or F
Definition Input from purchaser's lower lntedock when raise/lower speed reference is used'
4-45
BHEL LOADCOMMUTATED
INVERTER
LTRBLE
Equivalentsoftwarevariable- LTRBLE
Variablesoftwarevariabletype- BYTE
Scaling- T or F
Definition- lnput from link reactorinterlock.
LVLTS
Equivalent software variable- LD_VOLTS_DC

Scaling- range -256 to + 256
258 counts - > 1 PU load DC volts
Definition- Variable representing load side dc link voltage. lt is calculated from speed, fiux, and
firing angte. The variableis used as a feed foruard compensation to the source current
regulator.
MAMS
Equivalent software variable - MAiIS

Variable type - BYTE
Scaling- TorF
Definition Equivalentsoftware variable derived from comparison between motor speed and min:
imum speed reference setting. State controls interlock to the customer.
MBlST
Equivalentsoftware varilable- MB1ST

Variable type - BYTE
Scaling- T or F
Deftnition - Background sequencing variablerepresenting the atate of an interlock from the power
conversion blower number 1 motor starter. tJsed in fzult and alarm logic.
4-46
LOADCOMMUTATED
INVERTER BHEL
MB2ST
Equivalent software variable- MB2ST

Variable type- BYTE
Scaling- T or F
?gl1!gn- Backgroundsequencingvariablerepresentingthe state of an interlockfrom the power

conversion blower number 2 motor starter. Used in fault and alarm logic.
MB3ST
Equivalent software variable- MBIIST

Variable type- BfTE
Scaling- T or F
D_gqj!""- Background sequencingvariable representingthe state of an interlock from the power
conversion blower number 3 mdtor starter. used in fault and alarm logic.
MB4ST
Equivalentsottwarevariable- MB4ST
Variabletype- BYTE
Scaling- T or F
9"1i9!gn- the stateof an interlockfrom the power

Backgroundsequencingvariablerepresenting
conversionblower number 4 motor .starter. used in fault and alarrh logic.
MFPK
Equivalent software variable- MTR_FLUX*PEAK
Variable type- BYTE

Qa=!i'rn. 'tT ?t
COUntS - > l PU
Definition- Instataneoushighest of the three motor flux waves. Only calculated in load side
firing modes 0 and 1.
4-47
BHEL LOADCOMMUTATED
INVERTER
MFWD
Equivalentsoftwarevariable MTR-ROTATION-FRWD
Variabletype 6'rTE
Scaling T or F
Definition Motor directionflag. Calculatedin load PLL routine. Used to determineload firing
mask rotations.
MtsoLs
Equivalentsoftwarevariable- MISOLS
Variabletype- / ErfTE
Scaling- T or F
Definition- lnputto background
sequencing zuxiliary v
programas a funciionof the motorr-;olator
interfock. i
MODEFLG
Equivalentsoftware MODE_FIAG
Variabletype WORD
Scaling blt coded
Definition Variableusedto interfacethe backgroundsequencingprogramto the firingalgorithms.
The variableis coded as follows: t
Bit 0 Flunwith field exciter
1 Fhrn without field exciter
2 RJn field exciter only
3 not used
4 crowbar
5 switchgearclosed
6 twelve pulse
7 master channe
I gate test nrode
4-48
*'
tr
f LoAD coMMUTATEDTNVERTER BHEL
{ 9 not used
{ A High torque
B not used
C factory field exciter
D factorysourceside firing
E factory loadsidefiring
F factorypumpback
MOvTEMP
Equivalentsoftware- MOVTEMP
Variabletype- BITE
Scaling- T or F
Definition- Motor overtemperaturgdeviceinterlockinput. tJsedin backgroundsequencing
programme
[ITRVLTS
Equivalentsoftwarevariable- ilTR_VOLTS
Variabletype- |I{TEGER
Scaling- 128 counts - > 1 PU motor volts
Definition- Motor line to line vohs. Calculatedfrom the equation.
MTFVLTS= K *SPEED*(motorfiux)
Equivalent software variable- NALII

Variable type- SfTE
Scaling- T or F
Definition- Background sequencing variable which is true when no alarms are present in the
control,
4-49
BHEL LOADCOMMUTATED
INVERTER
NBI-A
Equlvalentsoftwarevarlable- NBI-A
Variabletype- BYTE
Scaling- T or F
Definition- Backgroundsequencingvariablewhich is true when no blower alarmsare present.
That is, whenthe powerconversionblowerselectedto operateis the one operating.
NBLF
Equivalentsoftwarevariable- NBLF
Variabletype- BTTE
Scaling- TorF
Defiglgn- Backgroundsequencingvariablewhich is true when.is true when no blower fzults
are true. That is powerconversionblowerselectedto run (or its redundantbackup)
is running.
NCFLT
Equivalentsoftwarevariable- NCFLT
Variable.type- BfTE
Scaling- T. or F
?fd!!gn- BackgroundSequencingvariable. True when faults are present as sensed by the

control.
NPSUV
Equivalent software variable- NPSTV
Variable type- BYTE
Scaling- T or F
Definition- Background sequencing variable. Monitors the state of the P1O5Vpower supply and
- is true when the power supply is okay.
4-54
LOADCOMMUTATED
INVERTER BHEL
NSFLT
Equivalent software variable- NSFLT

Variable type- ryTE
Scaling- T or F
De{nition- Backgroundseqiuencingvariable.Truewhen no faultswhich trip sourceside switchgear
are present.
OVLTE
Equivalentsoftwarevariable OWOLT_ERROR
Scaling - 8254 counts .> 1 PU flux
Dgll,tigl Overvoltageregulatorerror signal. The flux level necessaryto hold the overvoltage
regulatorsetpointis continuallycalcucatedas a functionof speed. A comparison
of these flux setpointand the flux feedbacklevel resultsin OVLTE.
Pt900c
; Equivalentsoftwarevariable- PORT_9OOC
Variabletype- BYTE
Scaling- bit coded
Definition- Background sequencingvariablerepresenting
an inputport, The bits representthe
followinginputs.
Bit 0 Sourceovervoltage
fault
1 Sourceundervoltage
alarm
2 Sourcesuppression
fault
3 Source Gating supply undervoltage
4 Load side overvoltage
5 Load side suppression fault
6 Load side gating supply undervoltage
7 Overspeed fault
4-51
f
BHEL LOADCOMMUTATED
INVERTER
PCROT
Equivalent software variable- PCROT
Variable type- B/TE

Scaling- T or F
Definition- Background sequencingvariable. True when input from PCROTinterlock is closed.
PLLSERR
Equivalent software variable- PLL-ERROR-SRC
Varible type- INTEGER
Scaling- 1024 counts - > 360 degrees
Definition- Source phase lock loop regulator error signal.
PLLSFLGL ;
Equivalent software variable- PLL-SFI-AG-U)

i
-..
Scaling- not aPPllcable
'
Definition- Variableused as a measureof the load phase lock loop reliablility. A cdculation
where the error is excessivewill result in the variable being incremented by 3 counts
A good calculation will decrement the variable by 1 count. t
PLLSFLGS
Equivalent software variable- Pl I ISFI.AG-SRC
Scaling- not apPllcable
Definition- Variableused as a measureof the source phase lock loop reliablility. A calculation
where the error is excessivewill result in the variablebeing incrementedby 3 counts.
A good calculation will decrernentthe variable by 1 count.
4-52
i
f
{ INVERTER
LOADCOMMUTATED BHEL
PLLSLD
Equivalent software variable- PLLC-I-OAD_SRC

Scaling- 120 counts - > 60 HZ
Deftnition- Valueloadedinto sourcePLLcountertomaintainsynchronizmwith source linefrequency.

The equation controlling its value is
PLLSLD = Z2OOI(linefrequency)
RAC
Equivalent software variable- REG-AIIGLF-CMND

Scaling- + 255 counts - > full advance

-255 counts - > full retard
I
Def!d!!gn- Variable used to set converter firing angle when the corresponding regutator is open
I looped.
(
(
RAMPDEL
t'
( Equivalent software variable- ACCL-LMT

( Variable type- INTEGER
t Scaling- 155.3 counts - > 1 HZ per second
Definition- Intermediate variable in the ramp reference functtion. lts value reflectts the rate o{
change of speed.
\
i
I READY
I
Equivalent software variable- READY
Variable type- BYTE

t r Scaling- T or F
Background sequecing vareable.True when the drive ready to run function is satisfied.
I
Definition-
i l
4-53
BHEL INVERTER
LOADCOMMUTATED
REGOPEN
Equivalentsoftwarevariable REG-OPEN-CMND
Variabletype WORD
Scaling blt coded
and control
Definition Variablewhenrnaybe usedin tuneupto openloopthe variousregulators
firing angles directly.lt is coded as follows:
Blt 0 openscurrentregulator
opens speed regulator
2 opensflux regulator
3 opens load angle regulator
RETDLSRC
variable-
Equivalentsoftrrvare ALPH-RETARD-LMT-SRC
Scaling- ' 256 counts ' > 180 degrces
Definition- Variablerepresentingthe maximumangleof retardfor the source powerconversion
bridge. lt is programmedas a functionof current.
RSPD
Equivalent software variable- RASE-SPD
Variable type- BYTE
Scaling- T or F
Definition- Background sequenceing input variable. When raise/ower speed reference function
is used, this variable reflects the state of the raise speed interlock.
RTONI
Equivalent software variable- RTONI
Variabletype- gVTE
Scaling- TorF
Definition- Backgroundsequencingvariable.Reftectsstate of FffON input . This input is used
for return-tonormalin flyingspareconfigurationsand other channelrunningin twelve
pulse configurations lt is not used in other configurations.
4-54
LOADCOMMUTATED
INVERTER BHEL
RTON
Equivalent software variable- RTON

Variable type- BYTE
Scaling- T or F
Definition- Background sequencing variable. Fbflects state of FIION input is used for return
to normallin flying spare configuratios.
RUNPM
Equivalentsoftwarevariable- RUNPM
Variabletype- ryTE
Scaling- T or F
Definition- Backgroundsequencingvariable.Fbflectsthe state of the run permissiveinterlock
-
input.
RUNP
Equivalentsoftwarevariable- RUNP
Variabletype- BfTE
Scaling- T or F
Definition- Backgroundsequencinngvariablewhich controlsthe run permissiverelayfor closing
the motor isolator.
RUNX
Equivalentsoftwarevariable- RUNX
Variabtetype- BYTE
Scallng- | or r
the stateof motorisolatorcontrolrelay.True
Delinition- Backgroundsequencingvariable.Reflects
when a run requestis latched in.
4-55
I
r l
I
o l
i
I
r i INVERTER
BHEL LOADCOMMUTATED
RUN
Equivalentsoftwarevariable- RUt{
\briable type WTE
Scaling- T or F
Dsfinition- B*kground sequencingvariable. Truewhen permissiveto run and run requestare
true. Sets mode flag ,variablefor driraeto leave lookstart.
SFDBKL
Equivdentsoftwarevariable. SPD-FDBK
\toiable type- INTEGER
Scafing- 1024 counts - > N jE r
Definition- \hriable used in the speedregulator.This is the speedfeedback signalafter passing i
through the leadflagsPeedfiher.
SFDBK
Equivdent softrvarevariable. SPEED-FDBK

\Ariabte type. INTEGER
Scding-. 1O24counts' > 60 HZ
Definition- ltriable used in the speed regulator.This is the feedbacksignal variablewhich is 1
equal to SPEEDbelow 95.HZ and the averageof the last 6 SPEEDvalues above
60 HZ.
SFLUXUU
Suivalent software variable- SOTRCE-FLUX-SCAI-E

Scaling- l024counte-> lPU
Defnition- Variablewhich trimsflux profileas a functionof s6urceflux. Variableis proportional
to source flux being filteredand limited.
SPDEFII.
ftuivalent softwarevariable- SPD ERR-FIL

\rlariebletype- filfeegn
Scaling- 1024 cosnts . > 60 lE
Definition: Speed regulatorenor signal after passingthrough the speed error filter.
4-56
;
C
C LOADCOMMUTATED
INVERTER BHEL
a.
-
SPDRP
a
Equivalent software variable- SPD_RAMP
Variable type- BYTE
{
( Scaling- not appllcable
Definition- Background seguencing variable. The value of the variable selects which set of
correspondingaccel \decel \ 6R12P tuneup variavlescontrols the speed reference
input.
SPDSP
Equivalent software variable- SPD_SP

Vadable type- INTEGER
Scaling- (X8 eounts - > 1O volts
t
Definition- Background variable.Reflectsthe value of the presentlyselected speed reference input.
SPDSTP
Equivalent software variable- SPD_STP

Variable type- IiITEGER
Scaling- 1024 counts - > 60 HZ
,Qg[rt!!!on- Speed reference setpoint before the speed ramp function.
SPDSTR
; Equivalent software variable- SPD STR

( Variable type- INTEGER
! Scaling- 1024 counts. > 60 HZ
, , Definition- speed regulator reference (after speed ramp).
( SPEED
Equivalentsoftwarevariable- SPEED
l'
1O23counts - > 60 HZ
a
Scaling-
Definition- Speedfeedbackvariablecalculatedin load PLL routinefrom time betweenflux wave
crossovers. lt is made bi-polarby use of the motor rotationflag.
4-57
BHEL INVERTER
LOADCOMMUTATED
SREFMD
Equivalentsoftwarevariable' SPD-REF-MODE
Variabletype- BfTE
Scding- not aPPllcable
and
Definition- Selectsthe speed setpointsource as selectedby the backgroundsequencing
the tuneup variables' The modes are definedes follows:
Value O Remotevolt4e reference
1 Remotecurrent reference
2 Remoteroltage reference(reversing)
- \__
3 Local voltage reference
4 Flaise/owersPeed rsference
5 S€lecttuming gear function
6 Sel€ctminimumProc€sssPeed
SIEIEU
F4uivalentsoftware variable- STRTPtI
Variable type- B\fTE
Scaling- T or F
the state of the state of the start permissive
Definition- Backgroundsequencingvariable.Fbflects
interlockinPut.
SUVFLT
Quivdent software variabl+ SWFLT
Variabletype- WTE
Scaling- T or F
Definition- Source undervoltagefault ocists when true'
4-58.
LOADCOMMUTATED
INVERTER BHEL
TGRRQ
Equivalent software variable- TGRRO

Variable type- BYTE
Scaling- TorF
Definition- - Background sequencing variable. Shows the state of the
turning gear mode request interlock.
TIMESRC
Equivalent software variable- TIME-SRC

Scaling-'- 1024 counts - > 350 degrees
Definition- - Value of source time counter readingat time of firing.
TRNGR
Equivalent software variable- TRNGR

Variable type- BYTE
Scaling- TorF
Definition- - Backgroundsequencingvariable.True when controle is
operatingin turning gear mode.
TTHBLE
Equivalent software variable- TTRBLE

Variable type- gYTE
Scaling- TorF
Definition- - Backgroundsequencingvariable.Flepresentsthe state of
the transformertrouble contact input.
TWPLSE
Equivalent software variable TWELVE-PUI-SE

Variable type WTE
Scaling TorF
Definition - Background sequencing variable. True when drive is
operating in twefue'pulse mode.
4-59
LOADCOMMUTATED
INVERTER
USERA
Equivalentsoftwarevariable- USERA
Variabletype- ryTE
Scaling- T or F
Definition- Backgroundsequencingvariable. Fteeflects
the stateof the user alarmcontact input.
VLTSECCMD
Equivalentsoftwarevariable- VOLTSECCMD
t
Variabletype- INTEGER ,
Scaling- 1376 counte - > 1 PU fux
Definition- Thisis the loadsidevoltsecond commandand is equalto VL'ITSEGSTR
exceptwhen 6
the crosstieregulatoris active.

4,
€
VLTSECMTR
I
Equivalentsoftwarevariable VOLSECiTTR
I
c
Scaling 1376 counts - > 1 PU flux I
Definition Motorvoltsecondsavailablefor commutatingthe load bridge. Cdculatedfrom peak f

motor flux modifiedbby current com4utated.
VLTSECSTR
Equivalent software variable VOLTSECSTR

Scaling 1376 countg - > 1 PtJ tlux
Definition toad side volt-secondcommand to determinefiring angle. \Mren motoring \trTSECSTR
is equivalent VOLTSECMTR;however, when inrrerting,itis egud to motor peak flux.
4-6q
G
f
('
BHEL
(
(
{
{
Chapter5
{
Dlagnosdc Monltor SPeclflcatons
5-1 INTRODUCTION
regulatorand logic variables,
The LCIdiagnosticmonitorenablesthe userto display
modify system variables
and systemfault and statusinformation.The user can also
and regulator constants for tune-up and troubleshooting'
cK[ hard copy terminal,

The monitor interfacemust be an ffi-232 compatible
slightly modified monitor
or hand-heldterminat.The hand-heldterminalsrequirea
format to accommodate its limited display capabilities'
one stop bit. Acceptable
All Fs-232 communicationis 7-bit data, even parity,with
baudratesare30o,120O,2&O,md€OObitspersecond(baud)'Uponpower
lock into the baud rate
up, the monitor seachesfor carriage return charactersto
used bY the terminal device'
command (fr9m tne

To access monitor tunctions, the user must enter a valid
1-1 shows th6 basic
monitor's instructionset) at the diagnosticterminal. Figure
{rom the monitor
command structure.Many of the commands are called directly
r*, " proglPt, Control returns to this level after the requested
level, indicated by the
process executes.
extended modes
The engineertng and tuneup functions, however,are actually
one of the Engineering
of operationwith theirown instructionsets,For example,after
displaying
Mode commands executes,control returns to the EngineeringMode,
-E> .prompt. To return to the mon|tor |eve|, the user must input the QU|T
the
cornmand. (This is also true for the Tuneup Mode)'
5-t
BHEL LOADCOMMUTATED
INVERTER
Table 5-1. Deflnltons for Command Svntax Notadon
"is defined to be'
Items betweenbrackets are optional
Separatesitems in a list - chose one
Bracesdelimit items for the purpose of minimilng am-

biguity
Optional charecters in a command or parametersare in

parentheses
Userentries(Highlighted)
< 1-5decimaldigits>
< 1-4hex digits>
< 1-5decimaldigitswl or wlo dec.pt.>
CS: < hex no>. or DS:< hex no>
5-2 OPERATING INSTRUCTIONS
5-2.1 General Information

'carriage
To initiate communicationswith the Monitor, the user must enter several
returns"at the terminalkeyboard.The terminalthen respondswith a banner message
and the monitorpromptcharecter"* > ", indicatingthat it is readyto acceptcommand
inputs. At this point (and after entering the pass.code), the operator can input
any of the monitorlevelcommandsor selectone of the extendedmodes of operation
ffuneup or Engineering,describerlpreviously).
The user can terminatethe monitor session by entering the QUIT cornmand.The
terminalthen displaysthe logoff massage,indicatingthat the session is over.The
monitor then idles until the carriage return charecters initiate it again.
5-2
LOAD COMMUTATEDINVETITER BHEL
s-2.2 Termlnal Format
As pre.,4ous!ymentioned,the diagnostic monitor works with either a hand-held

terminal or a standard keyboard terminal. The monitor defaults (at the start of
the terminal session) is the standard keyboard format' ln the hand held mode
of operation,the ouput messagesare sent one at time to accommodatethe limited
displaylengh of the hand.heldteminal (16 charectersmaximumper line). Entering
a carriage return causes ttrl next line of output to be sent to the terminal'
s-2.3 Power-up status Messages
At initial power-up,the drive control performs a sequence of self tests and in-
itializationprocedures.Any test failure is automaticallysent to the panel printer'
lf the printer fails, diagnostic massages are rerouted to the diagnostic terminal'
5-2.4 EdlUng Funcdons
The diagnostic monitor provides text editing functions for correcting errors entered
within a command string. Each function is listed below with a brief description.
NOTE:
l
tn theenmples below thesymbol*> is thediagnosticmonitor
prompt (not typed by the us6r), and the symbot[CUfl rep-
resentsthecursorposiilond theend of thesequenceshown.
DEURUBOUT
Removesthe previouscharecterfrom the messageand echoesthe deleted charecter

the to the terminal.
Example:
Tvped- *> HEKP< DEL> < DEb LP
Echoed- *> HEKP/LflLPICURI
CONTROL.R
Causesall characterscurrentlyin the messageto be transmittedto the terminal

on a new line.Thisfunctionis convenientafter using DEURUBOUT becauseit
shows the state of the messagqdter tlre editing.
Example:
Typed- *> HEK< DEb LP< CONTROL-R>
5-5
g . +
["
F
r BHEL
Echoed- r> HEt(/l(\ LP

HELPtCUfl
INVERTER
LOADCOMMUTATED
ilOTE:
Typing subsquent consecutiveCOMrcL'R keyswitt Inwke

thernonitorrecaltfunction.Thisfedure callsup previouscom'
mands thatwere Wed at the terminal, stafiing with the rnost
racentand progressingto the oldestcommandremembered'
Atotaloffrcommand linesareremembered.Usingtherecall
featurehelpsthe userawid retypingacommandthathe wishes
to etaute repetititrclY.
CONTROL.X
Deletesthe entire messagethat has been entered so far.
1 NOTE:
This hasthe sameaffectre using he DAJHJBOWfunction

to removeall the charectersfrom the message.
Exarnple:
Typed - r> HEKL< CONTTL.b HELP
Echoed - *> HEKL

HELPICUHI
CONTROL.Y
Aborts the current command sequence and retums the monitor to the Currenl
mode of operation (e.g., ENGINEEFUNG,TUNzuP or the main level).
NOTE:
@NTROL-Yor CONTROLCmay be entered at any time to

aboft thecurrentprocess-evenduring thelistingof a message
d the terminal.
5-4
F
IC
I
lc INVERTER BHEL
LOADCOMMUTATED
\-.
i(
rf
1..
Fxample:
ll {l
t, Typed- T> HE< CONTFIOL-Y>
Echoed- T> HE" Y

T> ICURI
CONTROL.C
Aborts the current command sequenceand returnsthe rnonitor to the outermost

(main)level of operation.When a CONTROL-Cis received,the monitor also displays
a message identifying the product as in the login sequence'
Example:
Typed- T> HE< CONTROL-C>
Echoed- T> HE^ C

.-IGTOMONITOR.
*r lCURtr
( CONTROL.S
t
causesthe currentoutputto be halteduntil it is restartedusingthe ooNTROL-O
( switch.
T
CONTROL.Q
i (
t causes the currentoutput to be restartedafter havingbeen stoped using the
CONTROLSswitch.
i
5-2.5 Command SYntax
t
Thegenera|syntaxforamonitorcommandisshownbe|ow:
< command>li= < instruction>

\
( [< delimiter>< parameter>.'.]< crt
where < instruction> is one of the valid monitor instructions (defined in section
a3) and < cr> is a carriage retum. The < delimeteo and < parameteb entrieq'
if necessary, depend on the particular instruction being called. Each instruction
t
has its own set of valid delimetersand parameters'Also, some cornmands may
parameters
requireseveral< delimeter> < parameter> pairs,whilesomerequireno
at all.
5-5
BHEL LOADCOMMUTATED
INVERTER
As an aid to the opeator, and to facilitatehand-heldterminal use,allthe < delimeter>

< parameter> pairs need not be entered on the same line as the insfuction -
each needed parameter wil be requested by the monitor. The syntax for this type
of sequence is:
< command> ii= < instruction>< cr>
< operation>< cr>
After each < cr> entry the monitor displays an appropriate prompt that asks
the user for the necessary parameter.
The use of abbrevatedcommands is another ieature designed to aid the hand-hdld

user. Fbther than typing the complete inskuction word, only the first one or two
letters need to be entered (see the syntax definition tables in sections 3 and 4
for the minimum acceptable abbreviations). :_
5-2.8 Protcctd Gommands
Some monitor commands allow the user to modifi system variable and change
turning pararneters.Thesefunctions, because of their potentially destuctive nature,
are available only after excuting a privilege enabling sequence.
This is so the user will not inadrrertendymake modifications that could inhibit
'
the proper operation of the LCI Drive confol.
The privilegesare enabledby enteringa password at the monitor terminal. ftivileges

are automatically disabled when the monitor is logged of (eUlT).
Help
The user may print out a list of availablecommandsby askingfor HELp From
eitherthe MoNlroR mode, or one ol the extendedmodes,a HELp requestwill
print the list of commandsavailableat the mode only. fur example,if in the EN- t
G|NEER|NGmode, onlytheENG|NEEHNGmodecommands andnottheMoNlroR
mode commands,will be listed.
I,|ONITORCOilMANDS
The MoNlToR levelcornmandsare intendedto be the primarytools used in in-

terrogatingthe drivecontroland monitoringits status.The instructionset provides
displayand modifyfunctions,the abilityto resetthe control,and the powerdirect
variablesto analogoutputsfor strip chart monitoring,among other things.Table
5-2showsthecompletelistof instructions andtheircorrectsyntax.Thecommands
are definedin their singleline entry format,althoughthe "promt-through" type
sequence(as discussedin section 2.3) is laso valid. (see table $2).
5-6
INVERTER
LOADCOMMUTATED BHEL
Table 5-2 Syntax Deflnltlonsfor Monltor Level Commands
ASS!GN: A(SSTGNXUSTIDA)
DlSPI.AY VAR1>,< VAFP>,< VAs>

D(ISPLAY)<
DC<VAR1>,< VAR2>,< VAR3>
DF
DL
DS
HELP H(ELP)
PASSCODE: P(ASSCODE)
QUIT O(UIT)or E((lT)
RESTAffI: RESCTAFTT)
SWIBOIS: SY(MBOLS)[< symbolname>]
TERMINAL TER(MlNAL)
N]
< currentformat>CHANGE?[YI
VERIFY: V(ERlFn [symbolgroupname>]
s-3.1 ASSIGN
Rrnction: To designatethat a perticularvariable be assigned to a circular list

and/or D/A converter.
Usingthe ASSIGNfunction,the user may modify the configuration

of the terminal -circularlists by changing the number of entries
(ma<imumof 8) to be stored at each sarnple interval andlor select-
ing which entriesare being captured.A total of 2Kbytes of memory
are available for storage of the diagnostic list information. This
memory is evenly divided atnong the parameterswithin the list. As
an example, if 4 word parameters are monitored in the circular a
totd of 256 events will be recorded.
The list may be triggered either by a level trigger or mask trigger. In

eithercase, the trigger is compard against the variable selected in
list positionno.1. In a level trigger(> ,( ,= ), the variableis com-
pared with a chosen level. \A/trenthe bit trigger mode is selected,
'l
any bit of variable becoming true causes the list to be taken. Bits
of variable1 may be masked using the mask variable option of the
list.Thelistcan only be triggeredby the leveltriggeror the bit trigger.
\Mrenmore than one trigger has been activated,only the last will
be acceptedby the list function.
5-7
.' , fl
{ ' l
INVERTER
LOADCOMMUTATED
BHEL
to a D/A corrvert or for

The user may aiso tiiieci 'irive varables
chart recorder' 1'he analog
observationon an oscilloscope or
points on the front edge of the
outputs are availablefrom test
a variableto a D/A
printed circuit board HLCB' When assigning
parameters'SCALEand OF-
output,the operatorselectsthe two
exceeclstherange
FSEI.Sincethepossiblerangeof avariableoften
provided to scale ihe variable
of the D/A converter,a tunction is
D/A converter'Trrefollowing
contentsbefore sendingdata to the
Besideeach one is the
tablegivesthe possibleSCRte puttmeters'
are mutiplied before being
value by which the variablecontents
converted if that SCALEfactor is selected'
SCALEPARAMETERS
MULTITIIETER
SCALE MULTTMETER SCALE
0 1
15 113?768
1/16384 1
14
118192 -2
13
1/,1096 -3
12
-4 16
11 112048
111024 -5
10
-6 64
o 11512
-7 128
8 112s6
-8 256
7 11128
-9 ;
6 1164
-10 1021
5 u32
-11 ,*'t_
4 1/16
a 1/16 -12 *n:,_
-13 8192
2 114 _
-14 163.34
I
I
112 ;
-15 327€,8
0 1
5-8
f
f
f ]NVERTER
LOADCOMMUTATED BHEL
An OFFSETmay also be selected during the ASSIGN process - this value is

substractedfrom the variablecontents before the scaling process. This function
may be used when the slight variationsaround a fixed valr-reneed to be examineC
(See example below).
Example:
*< ASSIGN UST
SETTINGS:
1 -smaples;selectsvariablesto be sampled
2 -triglevel;setsup leveltriggeredlist
3 -trig mask;setsup bit triggered test
4 -site :selectssite where data is atken
Choice?1=
NO OF ENTFilES=1; previouslywas set to capture 1 parameter

( NEW VALUE? 3 < cr> ;set to capture 3 parameters
{ ENTRY 1 = FLUXFB;previouslyset to capture FLUXFB
( NEW ENTRY?SPDREF< cr> ;speed reference (no.l)
ENTFil/ 2= OO@H:nullvalue
(
NEW ENTRY?SPDFB< cr> ;speed feedback (no.2)
( ENTRY 3= 0000H;null value
NEW ENTFIY?IAFB < cr> ;armature current feedback(no.3)
*> ASSIGN LIST
SETTINGS:
1 -samples
2 -triq
3 -bit trig
4 -site
Choice? 2
TRIGGER LEVEL = 0
NEW VALUE? 2OO;level of trigger in counts
TRIGGERCONDITION?OFF
NAru VALUE?<; choices €ve ( ,) ,=
*> ASSIGN LJST
5-9
BHEL LOADCOMMUTATED
INVERTER
SETT]NGS
-samples
2 -rrig
-bit trig
- site
Choice?4
TRIGGERSOURCE=OFF;presentdata site
CHOICES(1-5);availabledata sites
SAC, SPLL, LAC, LPLL, BG
NEW VALUE? 1;selects SAC (0 disables list)
SE-rNNGS
-samples
2 -trig
3 -bit trig
4 -site
Ghoice?3
PRESENTMASK OOOO;you must turn off level trigger ,

NEW VALUE? FF;value must be in hexadecimal
*> ASSIGN LlSJgo to choice 4 to select site
*> ASSIGN DA1 < cr> ;choose DA1

[tP2) on HLCB (slot 2Q
ENTRY = SPDREF;thecurrent setup is shown
SCALE= 8
OFFSET=0
ENTRY=ISRC < cr> ;set new parameters-l source
SCALE = 6 < cr> ;divided by 64 to get in range
OFFSET= < cr> ;leaves the offset the same (at O)
*> AS DM < cr> ;choose the DA2fiP3) on HLCB (slot 2Q

ENTRY=SPDFB;thesetup is shown
SCALE= 8
OFFSET=0
ENTRY=< cr> ;still look at speed feedback
SCALE=-2< cr> ;multiply 4 to accent variations
OFFSET=1000 < cr> ;look at fluc'tuationsaround 1000
5-10
LOADCOMMUTATED
INVERTER BHEL
The following notes on using the diagnostic list apply,
1. When using the bit trigger option, the mask must always be entered in
hexadecimal.The bit(s) to trigger the list must be set to a "f in the
appropriatelocation,
2. ln eitherthe bit triggeror magintudetriggermode, entry "f in the variable

selectionsis comparedagainsteitherthe magnitudeor bit triggerword.
3. When usingthe bit trigger option,the word must be re-entered,wherever

selection3 of 'ASSIGNUST" is accessed,othenrisethe mask is reset to
u0u,
4. The list has completedtaking data when the trigger source has returned
to "OFF'afterenteringanotherselection.
5. Ust sites must be selected with care. The list not necessaryfill up il a site
is selectedwhich doesn't operateduring the o be captured.Forexample,
LPLLis diabledwhen the drive'RUN"command is removed.
s-3.2 Display
Function:
to displaycontent of select drive control variablesand circularlists.

.
Severaloptions are allowed in the DISPIAYcommand:
1. DL,to displaycircularlistinformation.
2. Df, to displaythestatusof thefaultand alarmlogic.
3. DS.to displaya conciselist of the drive'sstatus.
The DF command will produce a list of the most resent fault and alarm messges.
This list includes current status indications.
Drive variablesare displayedin their respectiveengineeringunits. Generally,they

,','. ;, ' "::..1{-i.{i:.,;.,
cui'irir.,spaed,etc..).The generalformatin which variable
contents are displayed is:
<varname>=<value>
DC: Displays1 to 3 symbols continuously.lf more than one symbol is required,

they are displayed in columns. The symbol name(s) is repeate after every 20
rows. The display is terminated by any key stroke.
This function is availablein the nrain and tune monitors.
5-11
cf
" l
"ll
f i BHEL LOADCOMMUTATED
INVERTER
i
a t i
Command line: DC < varnatne>{ < varname>}
{,< varname>}< crt
a space may be used in place of the comma
DC::= DISPI.AYCON]INUOUS
DF::= DISPI-AYFAULTS
DU:= DISPI.AYLIST
DS::= DISPI.AYSTATUS
Examples
*> DISP SPDSP < cr>

SPDSP= 472
q
*> D< cr>
t
NAME?SPDSP< cr> \- {'
SPDSP=472
{
&
*> DS< cr>
s
< drive status list>
*> DL< cr> a

I
*> < listing of circular fault log>

(
DF< cr> s
4.
< display of fault and alarm log>
€
I
HELP
Funetion:
To display at the terminal a list of the commands available in the current mode
of monitor operation.
Fxamples:
*> H< cr>
< list of availablecommands>
*> HE[P< cr>

512
G
F
(
(
s€.4 PASSCODE
{
( FuncUon:
To enable the monitor's privilegesfunctions.
NOTE:
For security, the characters are not echoed when entering

the password at the terminal. The present passcode is a car-
riage return, IGESALEM9] will alsoalways work for the
passcode.
Examples:
*> PASSCODE< cr>
PASSWORD:< password> ;PASSWORD
NOT ECHOED
PRIVILEGE ENABLED
to changethe passcode,see SET passwordunder TUNEUP
1 i
5-3.5 QU|T
Functon:
To terminatethe current terminalsession.Upon executionof the QUIT command,

the monitor will print a logout message and then begin idling, waiting for the
cariage return inputs that indicate the start of a new terminal session.
Examples:
*> Q< cr>
MONITOR OFF
r> E(< cr>
MONITOR OFF
5.3.6 RESTART
Funcdon:
To execute a software reset of the microprocesor.
Executingthe RESTART command is essentiallya soft reset.The diagnosticchecks

are run the same as during power-up, and the drive control is re-initializedto
restore the hardware (counters,etc.) to its normal running state.
5-13
BHEL LOADCOMMUTATED
INVERTER
NOTE
To execute RESTAFIT the drive must be stoped. lt the drive

is running,the FIESTAFffroutineswill not run, and the terminal
will print a warning.
&ample:
*> RES<cr>
5.3.7 SYMBOLS
Functlon:
To display at the diagnostic terminal the symbolic names that may be used to
access drive control variables.lf no qualifier is given, the complete list will be
printed;ifa partial name is specified,however,all symbols that match that partial
name are listed.
Examples:
*> SY< cr>
< completesymbol list>
*> SYMBOLSVFI < cr>

VARGAIN
VFII'IME
*> SYM SPDREF < cr>
SPDREF
5.3.8 TERMINAL
Function:
lb examine and possibly modify the terminalformat. The monitor will display the
currentformat (either"hand-held"or "standard"and then ask the operatorwhether
a change is required.EnteringY(ES)will cause the monitor to toggle to the other
terminal format. Any other entry will not cause change.
5-14
LOADCOMMUTATED
INVERTER BHEL
Examples :
*> TERMIML< cr>
HNDH!-D-CHANGEY<cr>
STANDARD FORMAT
*> TER<cr>
SPD-CHANGE?<cr>
STANDARDFORMAT
5€.9 VERIFY
Functon:
Displaythe currentstate of all drive EEPROMsettingsand adiuststo allow the

user to verifyfactory settings.lndividualgroups of variablesmay be displayed
by appeding one or moregroupnamesto the VERIFYcommand
for verification
(seeexample).The groupswill be listed in the order specified.Followingare the
possiblegroup names:
CR CurrentFlegulator
FC-:Field Flegulator
FL- Flux Fleference
FR Flux Fbgulator
Ml- Miscellaneous
OV- OvervoltageRegulator
PR Protection
PF Printer
i r r jpwuu ; aiirlu
SQ- Sequencing
SR- Speed Regulator
Examples:
*> VERIFY<cr>
< grouped list of all software jumpers and adiustments>
*> V SR, FR, SQ < cr>

< list of speed reg. software jumpers and adjustments>
< list of flux reg. software jumpers and adiustments>
< list of software sequencing jumpers>
5-15
F
I
(-
I
d
I BHEL INVERTER
LOADCOMMUTATED
{
i
l
,l 5-4 TUNEUP
I In the TUNEUPmode of monitoroperation,the user able to adjust the performance
of the drive by rnodifying regulator parameters and configurations. A step-by-step
,l
I tuneup procedure is contained in Chapter 6. Following are descriptions of the
commandsthatare usedas partof thisprocedure.Table5-4summarizethe command c
I
I
; syntax for the TUNEUP mode. f
e
For on-linetuneup of any regulator,the background sequencing RUN logic must
I
be satisfied.Monitor commands alone will not allow the drive to run. This mode
II
is intented to be used primarily when the drive is initially installed. G
I (
Table 5-4 Syntax Deflnltlonsfor TUNEUPLevel Commands
f
j APPLY cr>
AP(PLY)<
C
I ASSIGN: "AS(S|GN)
{ USTIDA} \ * (
I *{D(|SP|-AY){<
DISPIAY varname>[C]l k
I STATUSI ?
I UST< listname> l)l t
I DSI
DL< listname>)< cr>
e
I e
I HELP H< cr>
t
II
MODIFY: M(ODlFf)<varnatne>< cr> G
I e
. crt
REF(ERENCB
MODIFYREFERENCE:M(ODIF!) OR MREF
I {
I QUIT {Ql D$ < cr> F
I
REMOVE: REM(OVE)< cr> c

I €
i RESTARTSET PASSWORD
l SAVE: SAV(Q < cr>

< verifyquery> [Yl N] < cr>
t:
.
SAVE D/A: (SDA)< verifyquery> [Y I Nj < cr>
II
I SET PASSCODESeT(PASSCODE)< cr>
I
I
i SYMBOLS: *SY(MBOLS) symbol name qualifier>] < cr>
[<
I
I
TERMINAL *T(ERMINAL)< cr >
I < current forrnat> CHANGE?[Y I Nl < cr>
I
I
I TSY(MBOLS). cr>
TUNEUPSYMBOLS:
i . cr'
TUNEUP: | A(RMATURQI
TUN(EUPiF(IELD)
I
I VERIFY: *V(ERIFY) natne>] . cn
[< symbolgroup
5-16
i| | -l
;
l
g LOADCOMMUTATED
INVERTER BHEL
! *-Also availablein MONITOR mode --see section 5-3 for descriptions.

(
5.4.1 APPLY
Funcffon:
To apply the test generator referenceto the regulator being tuned up.
Fxamples:
T> AP< cr>
T>
5.4.2 HELP
Funetion:
To list the availablecommand set for the TUNEUP mode.
Examples:
T>Hccr>
T>
s-4.3 MODIFY
. Function:
(
( To allow the operatorto modify the contents of selected drive control variables'
( A new valuemay be entered,or the currentvaluemay be incrementor decremented
repeatedly.Aso, the increment (or decrement)step may be selected by placing
(
a new step after the I or D entry (see example below). lf none is specified, the
incrementstep will be one unit of the last significantdigit. Values are displayed
and entered in appropriateengineeringunits.
NOTE
{
Becausemodifying certain memory locations could have ad-
(
verse effects on the drive control operation, the MODlflcom-
I
mand may only be excuted after completing the privilege
enabling sequence.
Examples:
> MOD VRGAIN < cr>
VRGAIN='1.1
NEW VALUE?1S< cr>
\
VAR@IN= 15.0<cr>
( NEW VALUE?<cr>
{ T>
5- 17
T> M VARGAIN<cr>
vAn\rAll\= l. I
NEWVALUE?l<cr>
VARGAIN=1.2
NEW VALUE?| .3< cr>
VARGAIN=1.5
NA/VVALUE?l<cr>
VARGAIN=1.8
NEWVALUE?D<cr>
VAR@IN= 1.5
NEW VALUE?<cr>
T>
NOTE
lAthena tuneupcase is selected,a numberedlist of symbols

associatedwith that case is displayedat the terminal. lMile
running that particular test, a spbol's NUMBffi (from the
list) rather than its nane may be used as the argument in
theMODIFTcommand. This elimatestheneed to laboriousty
type out long symbol namesat the terminalduring a tuneup
sesslon. :
Examples:
T> MOD 3< cr>
FRCTAIN=1.1
NEW VALUE?1.3< cr> ;change gain from 1.1 to 1.3
FFIGAIN=1.3
NEW VALUE?<cr>
T>
54.4 MODIFY REFERENCE
Function:
-fib
modify (customize) an internal reference generator. When a tuneup case is
selected,its correspondingreferencegeneratoris automaticallyselected(seesection
5-4.201.The user then has the option to modify the charactristics of the reference
generatorshown in the following examples.A referencegenerator is a series of
two steps,each with selectableamplitudeand duration.Step durationsare entered
in seconds(i.e.,.05 for 50 milliseconds)and referencelevels are specified in per
unit levels (i.e.,for a current test, the level is in per unit current and for speed
test in per unit speed, etc.).
5-18
LOADCOMMUTATED
INVERTER BHEL
After the steps are fully defined and the test generator is enabled by the APPLY
command,the regulatorspecifiedby the TUNEUPcommand will be excited with
a periodicsignalcorrespondingto the test referencelevelsdefined.Afixed constant
level may be obtainedby setting the amplitudesof both steps to the same vaiue.
The REMOVEcommand disablesthe test generator and moves all excitationto
the specified regulator.
Examples:
(Fixed Reference)
T> MOD REF<cr>
STEP LEVEL(PU)TME(SEC)
0.1001.00
0.0001,00
STEPlLE]/EL=<cr>
STEPIDUFu\TION=<cr>
0.10
STEp 2 1_9161_= ;makelevelsagree
STEP2DURATION=<cr>
T>
(Stepped Reference)
T> MOD REF < cr>
STEP LEVEL(PU)TrME(SEC)
0.1001.00
0.1001.00
STEPlLEVEL=<cr>
STEPI DURATION=<cr>
STEP2LB/EL=<cr> ;setfor 10%step
STEP2DUMTION=<cr>
T>
5-19
?
i
BHEL
5-4.5 OUIT
TheQU|TcommandreturnsthemonitorfromtheTUNEUPmodetotheMoN|ToR
mode.
Fxamples:
T> Q< cr>
T> EX.<cr>
e
5.4.6 REMOVE
t
Thiscommandremovesthetestgeneratorsigna|fromtheregulatorbeingtuned
(
up.
(
BamPles:
T> REM<cr>
T> r S
r C
54.7 SET PASSCODE
e
Thiscommanda|lowstheusertodefinethepassword - u p t o s i x c h a r e c t e r sr
for it to be a permanentchange
{
long. The user must save this input t
r t .
l
t
i
i
l f
For security,passcodesarc not echoed'

t l
; ;
ExamPle:
< cr>
Ol-D PASSCODE=:< OLD PASSCODE>
;password not echoed
< cr>
NEW FASSCODE=:< NBil PASSCODb
;p6sword not echoed
< cr>
NEW PASSCODE=:< NEW PASSCODb
;verifY to enable
change'
T> ;can now save if want permanent
5-4.8 SAVE
Thiscommandstoresthepresentva|uesoftheregulatorvariab|esinthesytem's
nonvolatilememory.Aftermodifyingsystemparameters(forexample,gainsand
timeconstantsduringatuneupsession),theusercantransferthenewva|ues
topermanentstoragewiththeSAVEcommand.Theprevious|ystorageva|ues
arelostduringthisprocess;themonitorpromptsforuserconfirmationbefore
excuting the command'
5-20
C
? BHEL
INVERTER
LOADCOMMUTATED
{
(
NOTE
to excute the SAW comrnand'

Priiteges mustbe enabled switch
hardware W|TE ENMLE
Nso, the DMPB oo""* values can
be in the STORE ENABLEposition before
must
memory'
be stored in the nonvolatile
ExamPle:
*SAVE< cr>
< cr>
ARE YOU SURE?Y
if DMPB switch is on
CONSTANTSSAVED;saved
*>
r,> SAVE< cr>
AREYOU SURE?< cr>
CONSTANTS NOT SAVED
5-4.e SAVE D TO A (sDA)
Thiscommandstoresthepresentva|uesoftheDtoAasignmentvariab|e
thesystem,snonvolatile'"'oo.oJngtun"upmode,theDtoAconverters(1
reassig"*-""'""'01"9
and21arecontinualrv : ^'1"'"1",1H
f'|fi ;ilTT^{il
l*iXmj:;H:I1JJHl"Ii"':1fiff"Jp"'"t"sAVED/Aco
is therefore included'
TomodifytheDtoAasignmentspermanently,the.usermustfirstsetupthe
requiredp.,u'"t","usingthenssrbruDAcommarrd'TheDMPBboard,sWR|TE
ENABLEswitchesmustbeintheWRITEENABLEpositionbeforeva|uescanbe
memory'
stored in the nonvolatile
ExamPles:
*, gp[< cr>
ARE YOU SUftE?f< ct>
'
CONSTANTS SAVE
*, gQ[ < cr>

cr>
ARE YOU SURE?N<
CONSTANTSNOT SAVED
*>
5-21
INVERTER
LOADCOMMUTATED
BHEL
5.4.10 TUNEUP SYI'BOLS

associatedwith current tuneup case'
This command lists all tuneup variables
ExamPles:
T> TSY< cr>
TUNEUP VARIABLESARE:
< numberedsYmbollist> or NONE
T>
5.4.11 TUNEUP
Thiscommandinitiatesaparicu|arregu|artuneupsequence'Theuserfirstspeciftes
whichotsevera|regu|atorsistobetuned,thenselectsthedesiredtuneupcase.
Fxamples of valid commands are:
CR- CurrentRegulator
Fl- FieldRegulator
FL- Flux Reference
FR- Flux Fbgulator
Ml- Miscellaneous
OV- OvervoltageRegulator
PR- ProtectionVariables
RR- SPeedFbmP FtateConditioning
SQ- Generalsequencing
SR- SPeedRegulator
ExamPle:
iCurrent FlegulatorTuneuP)
T> TUNFE=- cr'>
:-
AVAILABLEVARIBALESARE:
i_ Cp4LpHI= 90
2_ CRAUTH2=86
3- CRCiAIN=338
+ 6p16= 0.020
5- CRMIN=0.20
6_ 6pg14g1= .2S
5-22
BHEL
INVERTER
LOADCOMMUTATED
5.4.12 ENGINEERING
TheENGINEER|NGmodeprovidesprimitivefunctions|ikeexaminingandmodify
memoryandinputandoutputports.Abso|uteaddresses,ratherthansymbo|ic
names,areusedtoaccessmemory|ocationandUoports.Tab|es5-3summari
mode of monitor operation'
the command syntax for this
Tab|e5.3SyntaxDefinitionsforENG|NEER|NGLeve|Commands
crt
DISPLAY D[Wl . startaddr> [,< end addr> ]<
HELP: H< cr>
INPUT l[Wl< Portaddr> ,[,"']< cr>
PUT P [ \ M . P o r t a d d r > , [ , " ' ] 'c r t

dest addr> < cr>
MOVE M< start addr> ,< end addr> '<
data> "']' crt

OUTPUT: O[WJ. portaddr> ,< data> ['<
OUIT {QlE$< cr>
newvalue""']< cr>
SUBSTITUTE: SIW< addr> ,[<
< start addr> ::= < pointer>

< port addr> ::= < hex no>
< end addr> ::= < Pointer>
< new value>::= < hex no>
< dest addr::=< pointer>
< data> ::= < hex no>
< addr> ::= < pointer>
5-4.13 DlsPl-AY
Function:
T o d i s p | a y t h e c o n t e n t s o f a m e m o r y | o c a t i o n o frorn'
r a b l oAdditionally'
c k o f m e m othe
r y 'ASCII
Thecur
byte (or word) is listed in hexadecimal
value of each
equiva|ento{tnememoryshownonalineisdisp|ayedinafieldtotherig
ofthestandarddisp|ay'on|yprintableASC||charactersareshown.-othersa
disp|ayedasaperiod(.).TheASCI|disp|ayfunctionissuppressedwhenopera
in the hand-heldterminal format'
Format:
cr>
D[W< startaddr>[,< end addr>]<
ExamPles:
cr>
E> D DS:800<
41
F800:0800
5-23
c
r
(^ BHEL INVERTER
LOADCOMMUTATED
{
{ E>
{ E> DW 2OO.21O< cr>
q6â ooFF 12-"'" 5256 4147 4E4g
ry1nt.n?f!{v_1
(
2020.0020 .u..3 VARGAIN
0OOO:O210 4243 CB CB
E>
t
54.14 HELP G
Funcdon: f
G
To list the availablecommand set for the ENGINEERINGmode.
t
Examples: f
E> H< cr>
< list of availablecommands> f
(
E>
G
s-4.1s INPUT C
Functon:
e
e
To display a byte or word at an input port'
e
Format: (
l[W]< port addr> < cr> t
Examples:
c
E> | 9008< cr> e
7F,
{
7F,
t
7t< cr>
E> {
E> lW 9OO8<cr> f
O77t< cr> {
E>
s-4.16 PUT
Function:
To modifythe contentsof selectedmemorylocations.lVping a comma c€ilIses

- to the nextsequenctial memory
the monitorto remainin the PUTmodeincrement
address.A carriagereturn at the end of a line excutes the current command
(if any) and then returnscontrolto the ENGINEERING level.This cornmandis
. very usefullin writingto EEPROMbecauseno verificationof modifiedinformation
is made.
Format:
P[Wl. addr> < cr>
5-?_4
c
c
(
(
Eramples:
E>PDS:A4Occr>
ru(ru:uArru A5-,
FC0O:0A415A-M< cr>'
E>
E> PW DS:50<cr>
FCOO:0050 OFFF
FC0O:00515A5A-<cr>
E>
s-4.17 MOVE
Function:
To move a block of data from one area of memory to another.Memory contents

are transferedsequentiallyfrom low memory to high.
Format:
M< start> ,< end addr> ,< dest addr> < cr>
Examples:
E> M DS:50,59,CS:00<
cr>
E>
M 800,900,DS:42>
cr.
E>
: {
5.4.18 OUTPUT
i ( Function:
to output a byte or word to an output port.
Format:
O[W]. port addr> ,< data> ,[,< data> ...1. crt
Ramples:
b O 8010.FF<cr>
-F8,
-FO<cr>
E>
s-4.19 QUIT
Function:
to return from the ENGINEERINGmode to the MONITOR mode.
Examples:
E> Q< cr>
E> E(< cr>
5-25
BHEL LOADCOMMUTATED
INVERTER
54.20 SUBSTITUTE
Funcdon:
Toexamineandmodi! the contentsof selectedmemorylocations.Typinga comma

causesthe monitorto remainin the SUBSTITUTE mode and incrementto the
next sequentialmemoryaddres.A caniage return at the end of a line executes
the currentcommand(if any)and then returnscontrolto the ENGINEERING level.
This commandis very usefullin writing to EEPROMbecauseno verilicationof
the modiliedinformationis made.
Format:
S[W< addr>< cr>
Eramples:
-
E> S DS:A4O< cr>
FCoo:0A4OA5-,
Fboo:oAal Z.A-AA< cr>
E>
E> SW DS:50< cr>
FC0O:0050OFFF-7FE
FC0O:00515ASA-<cr>
E>'
5.5 II'ADING DISPI.AY MESSAGES
Customized display messages can be loaded into EE-PROM to identfy the user,
drive, personnelto contact, actions to be taken, and such. Five different messages
can be loaded-startingat the locations below. Each message can be up to 64
characters long (minus 1 for end of message= 6g).
Startng
Address Message Type
3O@:2OO Header- messge printed at power-up
3O0O:240 Requisitionmessageprinted at begining of data logging"
3OOO:280 Requisitionmessageprinted when .Status": pB. used
. 30OO:2C0 Fauhmessageprinted at begining of "Fault, message
3O@:3OO Alarm messageprinted at begaining of Tlarm'message
To load message headers:
5-26
LOADCOMMUTATED
INVERTER BHEL
1. write the messageout on hte from in Figure5-'1.Rememberto leavetwo

spaceslor < cr> < LF> rf you need to force a new line. .
2. convert the charectersto theirASCIIequivalentusing Table58. After the

last c'onvertion,put 00 to signalend-of-message.
3. Usingthe moniorPUTcommand,load the ASCIIequivalents.
NOTE
You can a.lse a "," (comma) instead of a < cr> after each
AlSCll code to increment to the nert location - rather than
reloadind the address.
It is good practice to always include the user's name and the drive/channel#.
For the fault, alarm, and repetition messages,a reminder such as "Long items
in maint book" might be useful.The default messagesshould be okay. lt should
only be necessayto add user's name and drive l.D to the begining (if sufficient
space) or to the end (will need to move "0O" of the default message).
Fxamples:
MONITOR OFF < cr> ; From in figure Sl and 5-2 should be filled out.
*> PASSSWORD I
PASSWORD?<cr>
PRIVENABLED
*> ENG<cr>
E> PUT 3@0:200< cr> ;Enable EEPFIOMwrite switch
3OO0:200?? - 53,
30OO:201?? - €;Continue 'til all char, done
3ffio:2?? ?? - 00< cr>
5-27
C
t
INVERTER
LOADCOMMUTATED
G BHEL
C
MESSAGE
FORM 581: DEFAULT FOR HEADER
t'
Message TYPe
{ Stardng Mdrosg €fi)O:
t
ASCII(HEq Message Asctt(na(
Message
a Charcctcr
Charecter
01 n 33d
02 n 34
03 n 35i
n_ 36-t_
04
05 n 37_Q_ \ - (
n 38_m_
06_
n 39
07
@ n &j_
n 41_n_
09
10 n 42
11 n € L
'4H-o
12 n_
13 20 4sG
14 n 46
15 n 47_b_
16 n 48o
N 49_o_
17
18 n $_k_
n_ 51< EOM>
19_
n 52
N
21 n 53
22 n *
5-28
o
C
e INVERTER
LOADCOMMUTATED BHEL
{
{
Message Type
t
( Startlng Address -3000:
( Message ASCil(HDq Message ASC[(HE)0

Charecter Charecter
23 20 55
24 20 56
25 20 57
26< cr> OD 58_
27< ft> OA 59
28_R_ 52 60
29_e_ 65 61
30_c_ 63 62
31_o_ 6F 63
32J- 72 64< EOM> 00
i '
(
(
5-29
FORM 5B-2: ASCII CHARECTER SET
Charectet ASCII Charecler ASCII
A 41 a 61
B 42 b 62
43 c 63
D 44 d 64
E 45 e 65
F 46 I 66
G 47 s 67
H 48 h 68
49 i 69
J 4A i 6A
K 4B k 6B
L 4C I 6c
M 4D m 6D
N 4E n 6E
o 4F o 6F
P 50 p 70
o 51 q 71
R 52 f 72
s 53 s 73
T 54 t 74
U 55 u 75
56 76
w <7 w 77
X 58 x 78
qo
v 79
z 60 z 80
0 30 <spaca> 20
1 31 <cr> OD
z 32 <if> OA
3 33 # 23
4 34 & 26
5
,lq
2C
36 2D
5t 2E
8 38 3A
?a @ 40
, 5-30
INVERTER
LOADCOMMUTATED BHEL
CHAPTER6
INSUI.ATTONAND STARTUP GUIDE
It is assumedthat all interconnectingwires and cablesare place and are connected.

The erection and alignmentof the motors not described here, nor is the routine
checkou of the circuit interrupters.lt is advised that a deatiled installationlog
be maintained for each drive.
Check all external cabling is as per, cable schedule.
6.1 PREUMINARY CONSIDERAIIONS
a. Verifythe variablecomponent values in the SEM per sheet DA of the drive

elementary.
b. Veiify berg jumper locations as shown on drive elementarysheet DA.
c. Inspect all compartments for loose hardware/debrisremoving any such

materialprior to appyingpower.Checktightnessof allconnections (bus-
bars3 , wiringetc), placementand crimpingof connectorsetc.
, -
j d. Inspectall stab connectionsin the equipmentfor tightness.
e. Open dl circuit breakers;refer to drive elementary'
f. Open or turn off all switches and power supplies.
g. Partialyextract all PWE]'sfrom the SEM.
system-.
6-2 I/|EGGER TESTS
6-2.1 Ar cooled brldge:
a. Disconnect the ribbon cable to each HPTK card in the converter leg
modules.
b. Diconnectthe groundconnectionto the HP|Kand XPTNcards in each leg

module.
c. Diconnectthe load bridgeac filter neutralground in the fan compartment.
6-2-2 Water cooled brldge:
a. Disconnect the ribbon cable at the NATL (JV) attenuator boards in the
sourceand load bridges.
6- 1
c
r
fl BHEL LOAD COMMUTATEDINVERTER
{
b. RemoveNATLground (GND)JG stab.
c. Disconnectthe load bridge ac filter neutralground at the top of the load

bridgecompartment.
6.2.3 Megger power busses:
a. Confirmthat both the sourceand load side circuit interruptsare open.
b. Temporarilyjumper togthersourceside bussesAC1,AC2,AC3;dc busses

P1,P2,N1,N2; and load bussesM'|,M2,M3.Allbussesshouldnow be tied
together,
c. Meggerfrom any bus to ground using a 1OO0volt (or higher) megger'

Indicatedresistanceshould be greaterthan 1OOmegohmsfor air cooled,
2-5 megohmsfor watercooled. \ - €
d. Removejumpersand reconnectthe ribbonsand chassisgrounds.Recon-

nect the load ac filterground. i
t
e. jumper its output terminalstogether
lf the drivehas a load side interrupter,
and meggertoground.Indicatedresistanceshouldexceed10Omegohms'
Fbmove jumpers. n
t e
,
6€ CHECK CONTINUITYACROSS CELI-S
I
Using a multimeter,check across each SCR in the bridge. Measurementsshould I
indicate approximately10K ohms. lf greater, check the 10K equililng resistors

'l0O ohms check for defective snubber capacitor
across each cell. lf less than
or SCR.
6-4 APPLYAI.,'XUARYFOWER
powersupplycircuitbreaker.
a. Opentheelectronic
b. Applycontrolpower,aftercheckingincomingvoltage,
c. On air cooleddrives,checkbridgecoolingfansfor properdirectionof

rotation. andexitthe
Airshouldenterthefrontof thebridgecompartments
top of theblowercompartment(s).
6-5 CHECK SIGNAL INPUT POWER SUPPLY
Measurethe output of the P1O5volt power supply on the l/O module and confirm
that output is approximately105 Vdc.
6-2
.j..i.:.---.:,,
C
C
e INVERTER
LOADCOMMUTATED BHEL
66 CHECK ELECTRONICSPOWER SUPPLY

i a. Partialyextarct all the cards in the electronicsmodule(s)
b. Tum on controlpowersupply,PSFF.
( c. Verifypresenceof P5,P15,N15and c"28atthe test rings on the electronics

moduleheader(top).
d. check/adjustvoltage as follws:
AdjustR1on NPPBuntilP5= + 5.0 + 0.1 volts'

AdjustR6 on NPSKuntilP15= + 15.0t O'2volts.
AdjustFI/ on NPSKuntilN15= -15.0t 0'2 volts'
e. Insertthe cards and verifythat the power supply voltagesremainconstant.

Readjustvoltages if necessarY.
Using a DVlrI,measureTPa(FACR),TP5(FCBR), and TP6(FBAR)on NUB

cards in slots lC and tD with a DVlrrlin the millivolts dc range. Adiust dc
offset pots R1, R2 and ffi, respectivelyon the NUB main board so that
TP4,TPs, and TP6 read 0.0 millivoltsdc(t 5).
(
{
WARNING
( Thisprocedureshouldbe performedwheneverthe NLIBcard

or the PFt power suPPlYis rePlaced
I
6-7 CHECK GATING POWER SUPPLY
\brify that the output of the 70 voh gating power supply (PS7, located in the
bridge) is 84 Vdc* 5 Vdc.
i
6-8 Ft-FCTBOf{fCS MODULF lNlTlAlJzATloN

I
a. Turn off the electronicspowersupply and check that PROMsareinstalled

in the HMPG/DMPB(2R.
b. Fb-insertthe HMPBiDMPBand power up the electronicsmodule.The bus

hog LED on the HMPGmay come on if there is no HTCAcard in slot lF.
This is normaluntilEEPROMis properlyinitialized.
c. Connectthe terminalfurnishedwith the driveand attemptto communicate

with the processor.lf communicationcannot be established,then it is
necessayto initializeEEPRoM memory asfollows:
6-3
to DCOM
1. Jumpertestpintl1NOon HLCB-2E
2,Turnonthewriteenab|e(WREN)switchontheDMPB.TheWFIENLEDo
the DMPBshouldcomeon'
onthecardfront
theHMPGby shortingtheFtsTandDcoM testrings
3. Fleset
edgetogethermomentarily.Waittwominutesforthedown|oadinto
EEPROM'
d. Establishcommunicationwith the terminaland all the tuneupsettings

usingstheverifycommand.Comparetheseva|uestothosegivenon
systeme|ementarysheetslDE-lDG.UsingtheMoD|FYcommand,update
tuneupstomatchtheelementary,andexecuteaSAVEcommand.Turnoff
the WFIENswitchand resetthe processor'
6-9 SET UP DOOR PRINTER
consultthepanelprintermanualtoenablebatterybackup(clock),thenthetime
minutes'
and date. Also set the interval greater than 60
6-10 PERFORM CONTROL SELF TEST
Turn.on(up)NLoBtestswitch.FlesetHMPGbyjumperingTPl(FsT}toTP2(DcoM)
investigate any faul message'
momentarily. fullow the indicated instruction and
Flepeat until Passes all tests'
6-11 SET ADJUSTMENT POTS PER ELEMENTARY

RTD' U\n' OSP test rings
Measure and set the voltage for all the OV SUPB
as tabulated in the elementary sheet 1EC'
6-12cHEcKBR|DGECURRENTFEEDBACKCAL|BRAT|oN
6-12.1 Ar Cooled Brldge

system elementary sheet
Verify resistors and Berg iumpers on the XTFH aganist
XTFH' Measure the resistance
DA. FlemovecT lead plugs JR and JT from the -R BUFIDEN
should equal the
across each of the burden resistorson the XTFH; it
pot to fine tune'
- sErTNG" value per the elementary.Adjust the corresponding
Fb-connect Plugs JR and JT
6-12.2 Water Cooled Brldge

against system elementary
verify resistors and Berg jumpers on the xDcK card
sheetDA.RemoveCT|eadplugsJW,JE,JXandJDfromtheXDCK.Measure
on the xDcK it should equal
the resistanceacross each of the burden resistors
Adjust the corresponding
the ,,R BURDENSETTING"value per the elernentary.
JD'
pot to {ine tune. Re-connectplugs JW iE' JX and
'6-4
INVERTER
LOADCOMMUTATED BHEL
6.13 PERFORM SCR GATE TESTS
Refer to the paragraph entiled GAI1NG TESTS in Chapter 7 tor a description of

procedure.
Verify that the source and load (if used) circuit interrupts are open. Follow the
procedure described in GATING TESTS.
6.14 SOURCENO I-oAD FULL VOLTAGETESTS
Thetestsin thissectionrequirethatthe sourcepowerbe connectedand available.

Verifythat the SWGRrelayonthe l/O modulewill trip the incomingswitchgear
in the event a fault is detectedby the control.
Apply the control power,resetthe SEM and check that the IMOK LEDSare on,
and clear any indicatedfaults.Null
Checkfor any lault indications.Investigate
all meters.
6.14.1 Source vdtage dgnal phaslng and balanclng:

Observethat all sourceside bridge
a. Gose sourcesidecircuitinetrrupter.
neonlamPsareilluminated'
b. Connectan oscilloscopeto simuttaneouslyobservethe waveformson the

pointsTPl(\tsA),TP80rcB),and TP9(VAC) on the NsFc.2c. Confimthat
the phasesequenceis 1-2-3and that all theseare approximatelyequal.
(\tsA leads\68leads VAC)
Theactualsystemvoltage= (ATrNRAI]O)XVAC
whereATTNFATIOis givenon the systan elementarysheet1EA'
Usinga DVM,measurethe DCvoltageoffsetat test pointsVBA,\rcB and VAC.

Thisvalueshouldbe lessthan5 millivolts.
NOTE:
Must measurebetweenTPand ACOM testpointan the card.
c. connectanRMS-measure on theNUB-IC.Adiust
voltmeterto TP4(FBAR)
to obtainvoltageas follows:
R1(FIJ(AB)
6-5
r
I
BHEL INVERTER
LOADCOMMUTATED
VOLTAGE
ACTUALSYSTEM
FBAR= -. x4.75\,/AC Rl,,lS
SYSTEM\O LTAGE
NORIVIAL
f.
Nominalsystemvoltageis giveb on the system elem.sh, 1EA. 6
Now connect the voltmeter to TPS(FCBR)and adjust R2(Ftj(E}C)for the same c

rms rclatge as above. Repeatfor TP3(FACR and R3(FI-)(CA).Balance signals €
as accuratelyas possible (t 5 millivolts).Check that dc offset at TP4, TP5 and
*
TP6 of NLIBis < 100millivolts.
G
d. Connectthe measureTPI3(VABS)on the NUB-IC and check that the (-) {
dc voltage level is approxmately2.2A XVAC at TP9 of NSFC- 2C.
C
6-14.2 Set source under vottage debcdon: \ - e
Gonnect an ocilloscopeto backplace pin 1C-55; this should be at logic zero. c
Turn FB(uV) slowly cw until pin 55 just transitions high'(may alternate high an c
low).' €
. See system elementary sheet 1DCfor per unit source undervoltagesetting required G
(typically.7 p.u). ObserveTP1$1C (t-|\/)and adjust W (rc)-lC so that the measured €
value is as follows: (
I.IALSOUrcEVOLTAGE
NOMI t
W = x p.u.trip reqd x tripvalue
ACTUALSOURCEVOLTAGE t
t
6-14.3 Set source overuoltagedetecton:
Connectthe voltmeterto TP18(OVR) on the NLIB-1C.Turn R8 (OV)slowly

' 'O\f t
untilthe
counterclockwise LEDcomeson. The sourceside interruptershould
trip.
SeeelementarysheetDCfor per unitsourceovervoltageseftingrequired.Observe

the dc voltagein TP-18and re.adjustFl8so that the measuredvalueis as follows:
NOMINALSOUFCEVOLTAGE
OVA= xp.u.trip req'dx tripvalue
ACTUALSOUFICE
VOLTAGE
6-6
I
lr
f r
i r INVERTER
LOADCOMMUTATED BHEL
{ 6-14.4 Source slave brldge phaslng (serles 12 pulse only):
a. Usingan oscilloscope,observethewaveformson NSFC (2J):VBe (TP7),

(
VCB ilPS), and VAC (TP9).Confirm ihai ihe phase sequence is TP7, TP8,
( TPg.
Use a DVfrIto measurethe voltage- record each voltage.
1P7= TF8= TP9=
TheactualL-Lmeasurethe voltage= (ATTNRAT]O)XVll measured@ test point.

ATTNRATIOis given on system elementarysheet EA.
b. Using an oscilloscope, observe TFI(VBA)-NSFC(2C)and TP7(VBA)-

NSFC(aJ).Check whether the master (2C) leads or lags slave (2A) by 3O
degrees.check that tuneup variablesoDRTsT bit A is set appropriate for
masterleadingor lagging.
6.15 II'AD TESTS USING VOLTAGE SIGNALS FROM SOURCE SIDE BRIDGE
{
Trip source circuit iterrupter.Disconnectribbon cable JA from NSFC-2Band move
the ribbon cable JA from NSFC-2C to NSFC-2B.Connect a test jumper from
backplanepins 1C- 55 to 1C-1to disablethe source undervoltagefault if necessary
t ; to prevent source breaker trip.
6-15.1 load voltage signal phadng and balance:

i
Close source circuit interrupter.
a. Connect oscilloscope to simultaneouslyobserve the waveforms on test

points 1P70/B4, TP8(VCB),and TP9(VAC)onthe NSFC-2B.Confirm that
the phase sequence is 1-2-3 and all balanced. The test points should
measurethe same as for the source-side.Using a DVM,me€Furethe DC
vottageoffsetat TPI,TP8 and TP9.This valueshoud be lessthan 5 millivolts.
b. connect an RMS-measuringvoltmeterto TP4 (FBAR)on the NUB-1D.

Adjust R1(FU(AB)to obtain voltageas follows:
ACTUALSOURCEVOLTAGEx LOADATTN RAIIO x FRQM x 4.75

FBAR =
NOMINALMOTORVOLTAGExSRCATTNRAT]Ox 6o
\Mere FRQM=basefrequency.
Attenuationratiosand nominalmotor volts are given on elementarysheet 1EA.
6-7
BHEL INVERTER
LOADCOMMUTATED
Nowconneetthe voltmeterto TPS(FCBFI} and adjustR2(FU(BC)for the same

rms voltageas above.Repeatfor TP3(FACR) and RS(FLXCA). Balancesignals
Check
as accuratelyas possible(t Smillivolts). for < 10Omillivoltsof dc offiset
at TP4,TPSandTP6of NLIB.
c. Connectthevoltmeter to measure TP13(VABS) on theNLIB-1Dandcheck

thatthe DCvoltagelevelis the sameas for thesource-side2.229xVACat
TP9ol NSFC-2B.
6-15.2 Set load overuoltagedetecdon:
Connectvottmeterto 1P18(OVR) on the NUB-ID.Turn R8(OV)slowlyccw until

the ,OVA' l€D comes on. The motor contactor (if used) should trip. Observe
the dc vottageon TP18and readjust ffi so that the voltageon TP'OVA' is
as follows:
SffiATTN RATI
RATEDMOTORVOLTSX
'OVA= xl.2xtripvalue
ACTUAL UNE VOLTSX LOAD ATTN RAT]O
6-15.3 Set motor speed and voltage Indlcatone:
Since speed is drived from the frequency of the motor voltage, the source 50
or 6O Hz signals can be used as a relerence.to set the speed signal scaling
and the oversPeed detector'
8-15.4 }lotor 3peed slgnal:
Close-in line contactor (if already). Connect a voltmeter to TP1- 1E(SPD).Adiust

m (SPD) as follows:
TPl= 10.0 Vdc X Fsource /FRQMM, where Fsource= ratd source frequency and
FFTQMM= marcimummotor speed.
6-15.5 Speed Indicadons:
Adjust R4(SPM)- 1E so that the speed indicator on the control panel reads the
correct motor speed for 5O or 6O Hz, whichever applies.
6-15.6. Motor voltage Indlcatlon:
Adjust \nvl(RZ)-lD on DUB so that the motor voltmeter reads:
LOADATTNRATIO
Actual line voltagex
SOUFCEATTN RATIO
6-8
LOADCOMMUTATED
INVERTER BHEL
6-15.7 Set Overspeed:
Turn pot OSP (R4) - 1E tully cw Connect voltmeterto test point OSP OP10)-1E
ar-rdsiowiyiurn OSP(R1)-1Eccw uniiiihe OSP l€D comes on. Tne voliageonTPlO
should be as follows at the trip point;
TP10= 10.0 Vdc X Fsource/FRQMM,where F source= rated source frequency

and FFIQMM= ma(imum motor speed.
See elementarysheet EC for per unit overspeed.
Adjust OSP until TPIO= [per unit overspeed] X trip level
6.16 B(CITATION TESTS
These tests verify the operation of the exciter voltage controller(BrC).
Verifythat the burdenresistorson the NHVLboardin the EVCare per elementary

sheet 1EA.
6-16.1 Phase SequenceCheek:
Apply power to the source bridge and to the ElrC input terminals.Connectan
simuftaneouslyobserve
oscilloscopeto thewaveforms ontestpointsATTEI$A|CfPl),
ATTEN-BIfiP3), and ATTEN-CIflPs) on the NHVLboard.Confirm'that the phase
sequenceis 1-2-3and that all three signalsare balanced.
Withpoweronthesourcebridge,usganocilloscope to comparesourceVAC[IP9-2C)
'
againstE\rcL VACffPg-2A).Measurethe numbaerof degreesLVAC(2A) leads(-)or
l4s (+ ) VAC(ZC).Flecordthis valueand saveinto tuneupsettingFANGIAGusing
the terminal.Allowablevaluesfor FANGTAGusing using the terminal.Allowable
vdues for FANGLAGrang'efrom -45 degreesto + 45 degrees.
6.18.2 EVC Power Test
Close in source bridge power and EVC input power.Aitach a voltmeteracross

one phaseof the exciteroutput.Attacha clamp-onammeteraroundone of the
output lines.&ecute the test as follows:
1. At the local drive control panel,select LOCALoperationand set the local

referencepot to minimum.
6-9
II
- l
INVERTER
LOADCOMMUTATED
BHEL
2'openthef|uxregulatorandselectEVctestmodebysettingtuneup
SQFECto 2 usingthe terminalas follows:
MONITOR OFF < cr> ;lnput carriagereturns
LCIMONITOR ;MonitorresPonds
*> P< cr> ;InvokePasswordProcedure
PASSWOFID?<q> ;EnterPassword(=< cr> )
PRIVENABLED
*> TUN< cr> ;Selectthe tune uP mode

I
T> M SQFEC<cr> ;SelectSQFECfor modification
SQFEC= 1 ;Gurrentvalue cf SQFEC
VALUE?=2< cr> ;Cunent ac E\E test mode

a
Thefie|dcontactorshou|dc|oseandEVCouputcurrentshouldbezero'
pot' Usingthe local
The EVICfiringis norvcontrolledby the localspeed
allowable
speedpot, increasethe excitercunenl' Stop when mar<imum
excitercurrentfeedbrckat test pbinttfA-zl readasfollows:
MeasuredBrC Current
IFB = x 5Vdc
Rated EVC Ctlrrent
4. Usingthec|amp-onandvo|tmeter,verrfythata||threeoutputcurrentsand
voltagesare equal.
back to its original
5. Reduce exciter current to zero and modiify SQFEC
value.
6-17 CROWBARTEST
Thecrowbartestpermitscontrollabledc linkcurrentto becirculatedwithoutinvolving

circulatesthroughone or
the motorwindings.on the load-sidethe dc current
signalsto be observedon
more diametriccell pairsby passingthe motor.The
whetherthe source'sidecTs are phasedcorrectly'
the oscilloscopewill indicerte
a. Fleseltheelectronicsrnoduleandapplysourcepowerto the bridge.clear

all existingfaults.
6-10
G
?
e LOAD COMMUTATEDINVERTER- BHEL
b. Connecta terminalto the HMPGRS232port.
! c. MODIFYthefollowingEEPROMvariables(SeeBamole G1):
{ 0
CRMIN to
SQDRTST to 4for driveswith tach feddback
SQDRTST to 68 for driveswithout tach feedback
CFSTART to 0
d. Connectchannelone of an oscilloscopeto NSFC-2CSlGl ffPl).

"OlA.
Connectchanneltwo of the oscilloscopeto NUB-1C 6fp111.
Triggeron channelone.
e. Initiatea run sequence;i.g, sequencethe drive to pick-up the software

'FIUN'.The current regulatorshould now be active but regulat-
logic ladder
ing zero cunent. check that MoDEFLGbits 4 and 5 are set to 1 (Seeelem.
"RUN*logic).
sh. lFFfor software
Usingthe MODIFYcommand,set CFFTARTto '1 p.u (10% current com-

mand).Checkthe currentfeedbacksignalIFB-1C(TP7)for -0.5 Vdc * 0.2
Vdc. current signal at IFB should appear stable when viewed on an
oscifloscope.For driveswith series12 pulse source, check lFB2 - lH on
NB|Efor the same voltage and waveshape.
g. IncreaseCRSTARTto.2p.u.using the modfi command. current should

now be continous;ie, not going to zero. Observethe test point pairs for all
three cunents and gating signds as indcated in Figure G1. Note that if the
drive has a series 12 pulse source that the three source slave currents and
gating signalsmust also be checkedper Figure&1. lf any of the current
signals are invertedfrom what is shown in the figure then the ct signal is
inverted.lf any current pulse are missingthen an scR leg is not firing.
Example&2
MONITOROFF < cr>

*> PASSWORD
PASSWORD?< cr>
PRIV ENABLED
*> TUN < cr>
T> M SQDRTST< cr>
SQDRTST= 18
VALUE?4< cr>
6-11
ii:i
INVERTER
LOADCOMMUTATED
BHEL
T> MCRSTART<cr>
6p514p6 = 0,5
VALUE'I O< CT>
IFB
cRsTARr= 0.0 ;Start drive and check
:lncreasebY 0'1
VALUE?1.1<cr>
6gg14gf = 0.1
bY0'1
:lncrease
VALUE?l< cr> current
:Checkfor continoits
cmTAffr = 0.2 to increasecurrent
VALUE?l< cr> ;Continue
calibration
cRsTAKr= 0.5 ;CheckIFBandammeter I until
andincrease
l< cr>
VALUE? 'OO,r"rtrtP to minimum
0'7
;tripat aPProximatelY P'u'
should
thecrowbarmode' current
Wen circulatingcunentin above
tO """onds whenoperating
be applied forno more'h*
.33 P.u. current'
h. Ammeter Calibration:
p'u using the MODIFYcommand'
1. lncreaseCRSTARTto'5
read -2'5 Vdc
voltage at test point IFB - 1C' This voltage should
2. Checkthe ammeterequal
pot lM - lC to obtain a readingon the door
t .25Vdc' Adjust rated motor
X rati motor current' See elementary sheet EAfor
to .2 X ffg
currentvalue'
the motor under
calibration should be rechecked later with
3. The ammeter
procedure'
heavy load using the same
:
(Overcurrent)
SourceHardwareSuppression
CW)'
on NUB to minimum(tulty
1. ACiustpot SUPP-1C
INVERTER
LOADCOMMUTATED BHEL
stGl +zEV
NSFc-zc-l
fS=1P.U.CURRENT
0tA
NLIB- 1C
SIGJ +26V
NSFC-2C
tLl
0e
NUB-1C
SIG5 +zgv
NSFC-2C
Qtc
N L IB -1 C
Figure 6-l Fidng Signal and Current Signals.
2. Initiatecurrentflow in crowbarmode and increaseCffiTARTtoward .75p'u.

/'r+,êcrltQT-.6n ir * 'tEn.rrthcStlPP/ressinnl lFDonNL|B lCshotdd
come on and source breaker should trip.
3. Fte-adjustpot SUPP - 1c for the value shown on system elementarysheet

rc.
i. MoDIFYtuneupsSQDRTSTCreTARTand CRMINbackto their original
Removeany
values.SAVEthechangesandthenresetthemicroprocessor.
jumpersinstalled
for test.
6-13
4
c
(" INVERTER
LOADCOMMUTATED
BHEL
(
6-18 RUN MOTORUNCOUPLED:
6-18.1 Conslderatons:
B e a r i n g m o n i t o r i n g p r o t e c t i o n s h o u l d b e f u n c t i o n i n g a t t h i s p o i n t t o p r o t e c t t h!e
startedand bearingtemperature
motor.Themotorshouldbe runto fullspeedonce
, 1
rise.vibration,magneticcenter'andoilrings(slingers)checked'
6-18.2 Test connecuons: !
to a channelchartrecorder:
1. Makethefollowingconnections i
CH1to DA1 slot2E$nl (O- + SVdc) 3

i
- ii t
-
1DfIPl1)
CH2toOlAslot 0- t SVdc)
\-l €
1Dfres)
CH3toFCBRslot (5 Vrc rms) , €
I
GH4to olOslot 1D [TPs) (0-t sVdc)
a
6
CHSto IFBslot 1C [IPT) (0 - -s Vdc)
0 - 10 Vdc)
i
&
CHGto SPDslot 1E$Ps)
(
;( 2. MOD|FYthefollowingEEPrcM variables:
I
SRGAIN to 2.0 e
(
tO 1.0 e
( SRTC
i
I MTRFMIN to 25
{ 2s
FLUXS to ' v :
to 30
{ CRSTART
{ "F:u
FI-ASEN to
!
to 1.1
FLPBRK1
to 1.1
t Fl-PtsRl€
t
. tO 0.5
FLPMAX1
{
FLPMAX2 tO 0.5
{
SFil/llNR to 0.1
SQDFTTST tO &1
6-14
t ?
r f
f LOAD COMMUTATEDINVERTER BHEL
(
{
Drives with tach feedback are initially run without tach until
the integrity of the tach signal is verified.
3. ASSIGNLMODEtoD/A# 1 -2E
Scale= -5
Offset = 0
6-18.3 Start and Run Motor:
1, Checkthat auxiliaryand control power is applied.
2. Clearallalarmsand faults.
3, Close source circuit interrupterand rack-inload circuit interrupterif ap-

plicable.
4. Selectlocal speedreferenceand set it to minimum.
6-18.4 Motor Starting Notes:

t {
Motor starting torque is proportionalto motor field strengh and stator current
l.
{ level. Stator current at start is set by tuneup CRSTARI. Field strength is set
l1
i by tuneup FFISTAHTbut the value of FFTSTART required to obtain full output
voltagefrom the EVCis generallylessthan 1 p,u. due to the power of the brushless
exciter being less than unity. El/C output is a fairly linear function of the value
of FRSTARTup to the point where the EVC output reaches maximum. Field
strength at stad also depends on the arnount of time the field is applied before
start. This is controlledby FCDETAYand generallyis set for 10 seconds, which
is about three time constants for a typical motor field.
tf the motor will not start, increase both CRSTARTand FESTARTby 0.1 p.u. on
succesiveattempts.Do not increaseCRTSTARTbeyond 0.75 p.u. Do not increase
FRSTARTbeyond the point that givesmaximumallowableexcitercurrent (measured
with a clamp on) at standstillas given on elementarysheet EA. lf the motor runs
backward or alternatelybackward and forward, there is a good chance that one
of the inverter legs is not firing or shorted.
Adjust FRSTARTto give 0.8 to 1.0 pu flux measured at FCBR - 1DfIP5) shortly
after motor starts.
5. Initiaterunfrom the localcontrolstationby depressingSTAF|Tpushbutton.

Note that all normalrun permissives must be satisfied.Motor should start
and begin accelearating to minimumspeed. check directionof motor
rotationand changemotor statorwiring to correct if necessary'
6-15
INVERTER
LOADCOMMUTATED
BHEL
drive
(chaneel1 of the recorder)while the
Monitorl_tvloDEchangeson DA1-2E
WODE shouldchange as follows:
is accelaratingto minimumspeed'
MODEDA1OUTPUTOPERATIONMODE
0 0.0Vdc ldle mode,no current.
1 2.5Vdc Forcedcommutation,segmentfiring
2 5.0Vdc Forcedcommutation,PLL based
3 7.5Vdc Selfcommutation
speed pot and verify that the speed

contror the motor speed with the
followsthe reference'
the
the currentand gating signalsfor
7. Wth the motor running,check that -
on NSFC- 28 and NUB 1D'
load are per Figure&1' Check signals
and the motor shouldcoast to a
Initiatestop from the local control station
stop.
with Tach Only):

6.18.5 Tach6meter Set Up (For Drive
pin 10
differentialoutputs' connect backplane
lf the tachometerdoes not have logic 0/1
establish the correct threshold for
of the HTCA card to pin 5 (P15) to
sensing'
l . F t r r n t h e m o t o r a | 1 O o / o - 2 o % s p e e d a n d a d j u s V c h e c k t h a tlft aBcleads
hchanne|B
TP+1 F by 90 degrees'
HT.A Tpz-lF tagstach channelsA HTcA
Athatthetachconnectionsatthedrivemustbeswapped.Thesigna|s
shoulda|sohaveafio/odutycyc|e.|fthetachisatoothedwhee|andpick
pulses'
up, adiustthe pickupto give 5O%duty
2.ModifytuneupvariableSQDRTSTto2toenab|ethefeedbackcalcu|ation.
Notethatatachrea|teda|armmaybeprintedoutatthistime.Ftesetthe
alarm' if required'
3.DisplayvariablesSPEEDarrdTSPDcontinuityusingtheDCcommandto
'checkthetachspeedca|ibration.TSPDshou|dbereadasfo||ows:
x 28ooo
TSPD = (SPEED l1o24l x (60/FRQMM)
TSPDshou|dbewithintl4ocountsoftheca|cu|atedva|uearrdshou|dbea
Positivenumber'
LOADCOMMU,TATED
INVERTER BHEL
Graduallyrunthe rnotorto top speed,checkingthe calibrationof TSPDat

severalpoints.Check the waveshave of the A and B channelsignalsfor
magnitudeand duty cycle.
For tachometerswith a once per revolutionmarker pulse, the marker

location realtiveto motor A-N voltage must be determined.Since it is
imparaticaltomechanically alignthetachometerto the machinepoles,the
drive control is used to determinethe angular relationshipbetweenthe
markerand the motor A-N voltage,This angularrealtionshipis set in the
control by tune up variableMKPHASE.The followingproceduredeter-
minesthe anglebetweenthe markerand the A-N voltage.
a, Run the motor at top speed, no load with SQDRTSTset to 2 and with no
load.
'18.
b. ModifySQDRTSTto
c. the
Initiatethe test by modifyingSQDRTSTto26. The controlwillcalculate
correct valuefor MKPHASEand set SQDRTSTback to 18. The calculated
valueof MKPHASEwill overwritethe peviousvalue,Permanentlystorevalue
of MKPHASEby issuinga SAVEcommand.
6. Mrile the motor is runningat top speed, DA1 to TSPD (scale= 4, offset
= O)andmodify SRNFIC to 0.1. Connect brush to DA1-2Ewithzero on
center line and 25 volts full scale. Start the burdh at 5 mm/sec and initiate
a drive top. ObserveTSPD on the brush and verify that the trace of TSPD
is smooth as the motor coaststo a top.
7. On a 12 pulse drive, check the tach and MKPHASEsetting for both

channels.
8. Modify SQDRTSTto tuneup value given in drive elementarywhen tach

checkingis comPlete.
6-18.6 Speed Range Test:
Start the drive and gradually increase the drive speed to base speed (-Ihis is
the speed correspondingto the tuneup value FRQM,or alternativelyis the speed
at which the motor is designedto reach rated voltage).lf the motor voltagebegins
to collapseabovea certainspeed,the brushlessexciterphasesequenceis incorrect
and two of the three power leads will have to be swapped. Note that the motor
will only reach 5O% voltage at base speed because of the tuneup seftings.
6-18.7 Speed Ramp Test:
Start the drive with the local referencepot set to minimum. Rapidlyincreasethe
local referenceto maximum while recording the speed signal. Verify that the ac-
celarationrate is correct per the tuneup settingsgiven in the elementary.RR6PA0
- RR6PA5. RRBPO-4.
6-17
(*
fr
B H EL LOAD COMMUTATEDINVERTER
Fbpidlyreducethe local referenceto minimumwhile recordingthe speed signal.

Verify that the deceleration rate is correct per the elementary tuneup settings.
6-18.8 Remote Operadon:
Hace drive control in remote and verify drive follows remote reference and remote
stop/start commands.
6-18.9 12 pulse Check Out:

't. Onceonechannel of a 12pulsedrivehascompleteduncoupled running
tests,the secondchannelshouldbe done prior to attempting12 pulse 6
operation.Normallythe valuesof tuneupsFANGLAG,MKPHASE(if ap-
plicable),and SQMCHwill be differentbetweenthe 2 channelsSQMCH t
selectswhichis themasterand is normallyset trueon the masterchannel €
only. c
testsarecompleteon the secondchannel,the 12 pulse
2. Afteruncoupled C
linkbetween
channelsmustbe tested.StartA andrunto minimumspeed. C
\lerf DA+2E(HLCBTPs)on channelA is equalto 12P-1E(NLCBTP2)on c
channelB.
:F-. C
3. StartchannelB andverifythatthe currentsof the two channebh equal. (
FUn the drive to full speed, checkingthat currents,and vqltage
'E' are
€
balancedbetween thetwo channles.
C
4. Startandstopchannelsand maketransferbetweenchannelsas desired' t
e
(
6-19 RUN WITH MOTOR COUPLED
Modify tune up variables set strictly for uncoupled operation back to the tuneup t
valuesgiven in the elementary.Thesevariablesinclude SRGAIN,SRTC,MTRFMIN,

{
FLUXS, CRSTART FLPBRKI, FLPBRK2, FLPMAXI, FLPMAX2, SRMINR ANd
t
SODRTST
6.19.1 Test Connections:1
1. Makethe followingconnectionsa six channelchart recorder:
CH1 to DA1slot 2E (-IP2)(o- + 5 Vdc)

CHz to 0lA slot 1D 6fe11)(0- * 5 Vdc)
CH3to FCBRslot1D fiPs)(sVac rms)
CH4 to OlCslot lD fiPg)(0 - t 5 Vdc)
CH5 to IFB slot lC (-rF4(0 - -s Vdc)
CH6 to SPDslot 1E (.IPs)(0- 10 Vdc)
6-18
#
f
f' INVERTER
LOADCOMMUTATED BHEL
6-19.2 Startlng Tune-uP:
The start up of the LCI should be optimizedby varying EEPROMtuneup variables

FRSTARI CRSTAKI STIM and MTRFMIN.
FRSTARTsets the field controller (El/C) firing angle at start, during forced com-
mutation, and sets the initial field strength when restarting on the fly.
CRSTARTsets the stator current at start and for the first few firings in forced
commutatedoperationon driveswitouttachometers.On driveswith tachs.CRSTART
sets the maximum amount of stator current availableat start. In this case, the
drive current will ramp up until rotation is detected.
ST1Mis proportionalto the period of the startingfrequency applied to the motor

until flux sensed for drives without tachometers.For most drives, ST]M should
besettol-2seconds.
MTRFMINis the level of flux required to transition from open loop starting at
fixed frequency to segment firing mode of operation. MTRFMINis typically se
to .5 p.u. but be set as high as .8 p.u. on drives with unusuallyhigh inertia.
Initially set these tuneups to the values given in the sytem elementary.
The procedure is as follows:
1. Attemptto start drive and monitorchart recorder.
2. lf motor failsto rotate,increaseCRSIARTuntil motor begins rotating.For

a typical fan type load it should not be necessary to increase oRSTART
beyond .75 p.u. For a drive with tach feedbackand with high break away
torque,lt shouldnot be necessaryto increaseCRSTARTbeyond 1.5 p.u.
3. lf LCI stillfailsto rotate,increaseFRSTARTuntil motor beginsto rotate.In

any case,obsevethe levelof flux afterstart at approximately2.5 Hz motor
't'0
frequency.For a fanlpump load, FRSTARTshould be set to give '8 -
p,u. flux at this frequency.For a constanttorque loadwith high breakaway
torque,FRSTART shouldbe set to give 1.2- 1.4p.u.tlux at thisfrequency.
4. MonitorLMODEchangeson DA1-2E(channel1 of the recorder)while the

driveis accelaratingto minimumspeed.LMODEshouldchangeas follows:
A,1q
INVERTER
LOADCOMMUTATED
BHEL
6-19.3 Drlve wlthout tach:

DAl OUTPUT OPERATINGMODE
LMODE
g 0'0 Vdc ldle mode,no current
2'5 Vdc Forcedcommutation,segment

1
firing
5'0 Vdc Forced commutation, PLL

2
based
7.5 Vdc Setfcommutation
6-19.4 Drlve wlth tach:
DAl OUTPUT OPERATINGMODE

I-ITODE
0'0 Vdc ldle mode,no current

6
5.0 Vdc Forcedcommutation,no sPeed

6
regulation
4'4 Vdc Forced commutation, sPeed

7
regulator active
1.9 Vdc Setfcommutationusing PLLfor

3
firing and tach for sPeed feed-
back
up ln a
between modes smoothly or hangs
lf the control; does not transition
particularmode,lowerMFITFMIN'ltshouldnotbenecessarytolowerMTRFM|N
below .4 P'u.
5'|teratethroughstepsl-4severa|timestoinsurethatstartingisconsistent'
complete stop between start attempts'
Be sure that the motor comes to a
RegualatorTunrup:
6.19.5 Forced Gommutaton Current
Thepurposeofthisprocedureistominimizethetimerequiredforthedrivecurrent
tobere-estab|ishedduringrecoveryfromaforcedcommutation.Thevariab|es
tobesetuparecRAlfHlandCRALPH2.cRALPl-.|lsetsthefiringang|efor
thefirstsourcefiringdtera|orcedcommutatedcurrentzero.|dea||yCRALPH1
issettogetthedccurrentbacktoitsfina|va|ueinonefiring'GMLPH2sets
thefiringang|eforthesecondSourcefiringandisadjustedtosustainthecurren
estab|ishedbyCRALPHl.onthethirdandsubsequentfirings,thecurrentregulato
,6-20 becomesactiveandremainssounti|anotherforcedcommutationoccurs.
LOADCOMMUTATED
INVERTER BHEL
For applications wherethe requiredtorquein forcecicommutationis .25 p.Ll.or

less (as indicatedby valueof tuneup SRCLFC),settingsof 86 for CMLPHl and
90 for CRALPH2are adequate and no tuneup is required.
For applicationsrequiringhigh torque in the commutatedmodes of operation

(O - 10% speed) the followingprocedureis required:
1. ModifytuneupvariablesSRMINRand RRMINLto .05 p.u. Set the local

speedadjustpot to minimumand startthe drive.Thedriveshouldstartand
run in forcedcommutationat 5o/"speed.
Loadthe driveto appximately.5 p.u. currentor to the forcedcomutated

currentlimitSRCLFC(whichis lower)as measured on IFB with a DW.
Run he chart recorder at 125mm/secand obtain a trace of lFB. Compare
the trace obtainedwith the shown in Figure 6-2 and 6-3 and change
CRALPH1and CMPLH2 as indicated.
-- --
qP1-t trr-
Jt\vLt v
tl
LL-- O CURRENT
Figure 6-2 IFB during SEGFIRE.
6-19.6 Motor Flux Feedback Calibration Check:
1, Startthe driveand run up to some speed between50%and 75%.Connect

oscilloscopeto testpoint'VAC'fl-P7-28).The waveformshouldappear as
shown in Figure6-4:
Use a DVMto measureVac peak
Calculatemotor volts/f-lz(flux).
< attnratio> < Vpk/(1.41x)f>

VlHz=
< ratedmotor volts> /FRQM
Theflux signalsFBAR,FCBRand FACRon NLIB-1D(TP4,5,6)should then have
RMSvoltagesof:
\-:)..:: '
LOADCOMMUTATED
INVERTER BHEL
For applications wherethe requiredtorquein forcecicommutationis .25 p.Ll.or

less (as indicatedby valueof tuneup SRCLFC),settingsof 86 for CMLPHl and
90 for CRALPH2are adequate and no tuneup is required.
For applicationsrequiringhigh torque in the commutatedmodes of operation

(O - 10% speed) the followingprocedureis required:
1. ModifytuneupvariablesSRMINRand RRMINLto .05 p.u. Set the local

speedadjustpot to minimumand startthe drive.Thedriveshouldstartand
run in forcedcommutationat 5o/"speed.
Loadthe driveto appximately.5 p.u. currentor to the forcedcomutated

currentlimitSRCLFC(whichis lower)as measured on IFB with a DW.
Run he chart recorder at 125mm/secand obtain a trace of lFB. Compare
the trace obtainedwith the shown in Figure 6-2 and 6-3 and change
CRALPH1and CMPLH2 as indicated.
-- --
qP1-t trr-
Jt\vLt v
tl
LL-- O CURRENT
Figure 6-2 IFB during SEGFIRE.
6-19.6 Motor Flux Feedback Calibration Check:
1, Startthe driveand run up to some speed between50%and 75%.Connect

oscilloscopeto testpoint'VAC'fl-P7-28).The waveformshouldappear as
shown in Figure6-4:
Use a DVMto measureVac peak
Calculatemotor volts/f-lz(flux).
< attnratio> < Vpk/(1.41x)f>

VlHz=
< ratedmotor volts> /FRQM
Theflux signalsFBAR,FCBRand FACRon NLIB-1D(TP4,5,6)should then have
RMSvoltagesof:
\-:)..:: '
F i
> i
INVERTER
LOADCOMMUTATED
BHEL
n r CRAPH1
I \\'/,/--
cRALPfi
/-1 rooLlow
| >/ |
rooHrGH/
t tI / /a I _
?s6rffif-l_?56151
Flgure 6€ CRALPH1/2TUNEUP
Vf= (V/Hz)*4'75Vrms
of FBAR'FCBR' FACR;ie' signals
2. Checkfor accuratereconstruction
SeeFigure6'5for illustration'
shouldbe verysinusoidal'
6-19.7 Flux Regulator ResPonee:
l.Checkthefluxvesusspeedprofi|eovertheful|speedrange.Connecta
DV|vttotestpointFCBRonNUB-ID.operatethedrivefromminimum
speedtofu||speed,rneasuringtnenuxamplitudeatse|ectedspeedsto
verifythatitisfo||owingttreprontegivenonsystemelementarysheetEA.
Fbted flux - 4'75Vac rms FCBR'
2.Startthedriveandrunituptoapproxima|e|y7o"/"speed.\Mtenspeedis
steady,usethetermina|todisp|aythefluxsetpoint.F|J(secontinuously
and record the value'
'
3. Set up to step the flux regulator:
a' FromTUNEUPmode:
mode
T> TUN FR< cr> ;Selectflux regulatortuneup
AVAILABLEVARIABLESARE:
(listof variables)
6-22
a
f
f INVERTER BHEL
LOADCOMMUTATED
a.
:-7
i
,l
L
.aul
I
-
I
I
Flgure6-4 Motor Llne to Une VoltageWaveform.
b. monitorcr; ch?rt recorder.

AssignDA1to outputthe FLUXFBKsignaland
T> AS DAl< cr> ;ChooseDA1 on HLCB 2E
ENTFIY= FLUXFBK ;Defaultsettings for DA1
SCALE= 6
OFFSET= 0
ENTRY= FLUXFBK :Enter desired variable

< cr>
SCALE= 3< cr> ;DivideFLU)GBKby 8
CFFSET= ***< cr> i***= currentvalueof FIXSP
6-23
BHEL LOADCOMMUTATED
INVERTER
c. stepfunction
Setup the reference
T> MREF<cr>
STEP LEVE-(PU) IME(SEC) ;Defaultstep settings
1 0.05 2
2 0.00
STEP 1 LEVEL = O.O5<cr> ;5% step up
STEP1 TIME = 1O<cr> ;10 sec durationstep up
STEP2 LEVEL = O.(Xl<cr> ;Step down to zero
STEp2 TIME = 1O<cr> ;1O sec duration step

I
down
d. Monitor the flux feedback at DA1-2Eon the chart recorder.The recorder

should be set for 10 v full scale,zero center.Run the chart at 25 mm/sec and
apply the steP reference.
T> APP< cp ;Apply the step reference
4. Observe the response of the flux feedback. The response ol the:llux

regulator should be critically damped at 5 (+ 2, -0) radians as shown in
figure 6-6. (check system elementary sheet EA for regulator response
desired).
5. lf the response is too fast (or too slow), decrease (or increase) tuneup
variableFRGAINuntilthe nearestdesiredresponseis:obtained.
6. lf the responseis over damped (or underdampd), decrease(or increase)

FRTCto obtain criticaldamping. lf damping is now correct but response v
is not, return to step 5.
7. Whendesiredtuneuphas been achieved,remove step and SAVEtuneup

variablesnecessarv.
T> REM< cr> ;Removethe referencestep
6-19.8 Speed RegulatorResPonse:
1. Startthe driveandrunit up to approximately7O%speed.Wtrenthespeed

hasreacheditsfinalvalue,verifythatvariableCCMND(torquecommand)
is greaterthan variableCURLL(cunent lower limit) and that variable
ALPHSrcOis zero,Thisinsuresthatthe loadcsntrolis firingas lateas
possibleandthatthesourcefiringis not at advancelimit.
6-24
INVERTER
LOADCOMMUTATED BHEL
2. DisplayvariableSPDSTR(speed reference)continuouslyand record its

value,
3. Set for speeclregualtortune uP:
a. Enterthe tune up mode and executethe following:
T> TUN SR< cp ;Selectthe speed regualtorfor tume up
AVAILABLEVARIABLESARE:
(listof variable)
b. AssignDA1to outputspeedfeedback(SFDBR and monitor the signalon a

chart recorder.
T> AS DAl< cr> ;ChooseDA'l on HLCB-2E
ENTF|/= )0OO(H ;Monitordiplayscurrent
SCALE= X ;set up of DA1
OFFSET= 0;
ENTRY= SFDBK< cr> ;Enter the desired variable
SCALE= 0< cr> ;Divideby 1 (no scaling)
OFFSET= ***< cr> ;* = pr€s€ntSPDSTRvalue
c. Set up the referencestep function
T> MREF<cr>
STEP LEVEL(PU) IME(SEC) ;Defaultstep settings
1 0.05 5
2 0.00 5
STEP 1 LEVEL = O.02< cr> ;2o/ostep up
STEP1 TIME = 1o< cr> ;10 sec durationstep up
STEP2 LEVEL = O.(Xl<cr> ;Step down to zero
STEP2 T]ME = 1O< cr> ;10 sec durationstep down
6-25
{. BHEL INVERTER
LOADCOMMUTATED
d, Monitortest point DA1(HLCB-2E) on the chart recorder.Set up the recorder I

to 5v full scale, zero center,and run at 5 mm/sec' Apply the step reference
to the speed regulator.
T> APP< cr> ;Applythe step reference
The chart recordershould show approximaelya 3 Vdc change when the

step is applied.
4. Observethe step responseand adjust SRGAINand SRTCfor a 1 radian

(typical)criticallydampedresponseas shown in Figure6- 7. (check sytem
elementarysh. EAto confirmthat a 1 radianresponseis desired).lt should t:
only be necessaryto modify SRGAINto achivethe desired response.
i:
5. Removethe step as follows: .*. {i
f
T> REM< cr> ;Removethe referencestep
Savethe valuesfor SRGAIN,SRTCinto EEPROM.
6-19.9 Load lnverdon Umlt Tune UP:
Whenunderload,theloadconverternormallyopertesso thatthefiringis controlled

to give a constant20 degreemarginaftercommutation. Sincethe commutation
angleis a functionof currentand flux, it is necessxy tor the load firing angle
to adapt to these parameters.lt should be noted that the load firing angle is
dfected by othercontrolroutineswhenoperatingat light load,low sourcevoltage,
or higherthan normalmotor voltage'
Flgure 6-5 ldeal Flux Wave
6-26
€
rf INVERTER
LOADCOMMUTATED BHEL
{
I
FINAL VALUE
FLUX
SIGNAL F - 63% OT FINALVALUE
| . tNtTtALVALUI
l , /
I
F--- AT -. .?_StC TlMt

I
Flgure 6-6 Flux RegulatorResponse.
FINAL VALUE
FLUX I
VALUI
stcNALl
AT : SSIC TIME
Flgure 6-7 Speeci Regulator Response'
load possible'
It is desireableto tune up the invertion limit under the heaviest
cuRLL, CCMND,
Run the drive to any convenient speed and check variables
equals zero'
and ALPHSrcO. ll ccMND is greater than CURLL and ALPHSFiCO
L: iU rudu L- l r ri'r il-
waveform should
Connect an oscilloscopeto test point VAC on NSFC-2B'The
be similar to that shown in figure 6-8'
regardless
y= marginangle,Propertuneup resultsin this angle remainingconstant
of load.
place'
p= commutationangle or angle during which commutationis taing
F= angle of advance
the loi:d firing angle
TuneupvariableLII4ARGsets the amount of compensationof
reactanci: LIMARG
due to cui-rent!eve!arrd is equal to the motct' commutatinq
is defined by the follcwing equatior''
6 - 27
BHEL LOADCOMMUTATED
INVERTER
LfMARG = 1.o47llD* {V/n; * (COSy-COSB)
Wrere:
UMARG=per unit commutatingreactance
lD= per unit current= lFBlS
V/H = per unit motor flux
lf the margin angle is les than 18 degrees,increasethe value of UMARG. lf the

margin angle is greater than 22 degrees, decrease the value of UMARG. The
margin angle should reamin constant regardlessof current if UMARG is tuned
correctly.lf original value 16 changed, then SAVEthe new value into EEPROM.
6-19.10 Source-sideUne lmpedance:
Normallythe source.sideoperates in the rectifyingquadrant. However,when the

drive is forced to slow down the source converter may have regerate (invert).
To avoid commutationfailures in this case, the source inversion limit angle must
be programmedas a function of current.Since a regeneratingcondition is diflicult
to hold steady-state,a measurmentof system impedancewill be made and this
value will be programmed into EEPROM.
The tune up variableused is SfMARGand is similar in function to the load tune

up variable UMARG. SIMARG is equal to the source (primary the transformer)
per unit commutatingreactanceand is calcllated using the following equation:
SIMARG = (VLUID) * [cosr:r- cos(ct+p)]
Where:
VLL- per unit line- line load voltage
lD= ps unit current= IFB/S
(r= sourcefiringangle,alpha
p= sourcecommutatingangle
Run the drive to some convenientspeed(thehigher the better),Gonnect channel

1 of oscilloscopeto testpoint \/AC" -2C.Connectchannel2 to to testpoint"OlA"--1C.
The signals should be sirnilar to those shown in figure 6-9.
VLL= (attn ratio)*(Vpki1.a1a)&nom
whereVnom= transformernominalvoltage.
i{ecordc,p, lD ar:dcalcuiateSIMARGusingthe equationgivenprevrously. UMARG

should calculateto be approximatelyequal to the iscaltiontransiorrnerper unit
rmpedace. Rounij up ihe resuit to the nearest .01 and SAVE into EEPFIOM.
6-28
INVERTER
LOADCOMMUTATED Bl-.lEL-
7
FACR
Flgure 6-8 Load Slde FALAP
6-29
€
Bt""{ft-
lNVr:RTEFI
LOADCOMMUTATED
f
'flF5lElEql@ffi:_rc:
t'
Flgure&9 SourceSide Flrlng Angle.
as
To test the tune up value, run the drive to top speed and decelerali-'as fast
possible. lf drive trips on overcuurentor source commutationfailuie, increase
the value of SIMARG and try again'
6-l9.tt Dual Cltsnnel Tests:

,:s qivr-r ::i
Siart dri'ie chanrre!A and run to maxmum single channel speed
possii''!e.
tuneup tiiihlF-x6i? L.oad channel A to rated currenvpower if
+s iri:t*'vrr*i'
Slar{ciari;'r::lB i "vihtA alreadyrunningland check that current baian'
'' r,,,,1,.-:fii-is. !
, - . j ^ , 5, q
: .î :r, , , R u t t C r i v e u pa r i c ld o w t ' ri n s p e e d c l - r e c k i i rig' l ' , i g r . ' : t " '
balance.
'rhen lestaft
and
Run iire drive to rnaximum single chanllel speed, stop channel A,
channel A-
The rlrive speed

Run the drve t0 approximately rated speed and stop channel A'
B shoriid continue
should clecrease to rnaximum single channel speed and channel
- instead.
to run. Repeat test but drop off channel B at full speed
stop the motorand startdualchannel.Verifythat currentappearssim,ritaneously

in both channelsand that startingis relaible'
f
f;
f, INVERTER
LOADCOMMUTATED BHEL
i
6-19.12 Source Mlnlmum Angle Control:
{
( 1, Modify and variables FLALENand FLASENto the values given in the
system elementarY.
'f,
2. lf FLALEh|= run the drive to a speeclgreaterthan that corresponding
to variableFLEARLY(givenin Hz). DisplaycontinuousvariableFLUXADJ.
lf FLLjXAD.J> 0 thetrthe functionis working'
': j{ it is ner--,csr-ary tz:ctsrandloiharmonics,it may be done

pcJwer
ro rrteasure
at this time.
6-19.13 Calibrate Powei iileter/Romote Power Slgnal:
The panel pcwer meter (eitlierhorsepoweror kilowatts)should be calibratedwhen

the clrive is above half load, and shotild be checked at several load conditions.
Power delivery to the motor shaft is equal to lhe power delivered across the dc
link minus the inverter and motor losses, Since it is relativelyeasy to calculate
cJciirrk power, the prefered methocjfor determing motor power output is to first
determinedc link power and grultiplyit by motor etficiencyto arrive at shaft power.
Dc link power is determineas the product of dc link current anci dc link voltage.
DC link current is proportionalto the voltage measuredat test-poini IFB on the
I
load NUB card. DC link voltage is proportionalto the volatge measured at test
r. point - Vdc on the load NSFo card. The produce is as follows:
1
a. rneasurethe dc voltageat test point IFB on NUB-1C. Also
Using a DVf."4
measurethe tlc voltageon test point -Vdc on NSFC-2C.
b. Calculatedc link kilowatts:
DCI(VV= .0002565" lM * -VDC* IFB* ATTENRAT1O
Where:
lM= rated motor winding currerlt,ac rms
ATTEN RATIO= volatge attenuation ratio
See elementarysh EA for these values
c. Calculateoutput kilowattsor horsepower:
l.0rV=DCIQV* EFF
HP= DCI$!'* EFFI.TK'
typically.97
rvirer*EFF= motor efficiency,
6-3'1
BHEL LOADCOMMUTATED
INVERTER
d. Adjustpot HPM on DLCB-IEto givwecorrect readingon panel HP or tOV

meter.lf the remote {2A r,a HP//K\/signai is used, check iis calibration
againstthe panel meter.lf requied,the 42Oma signal can be calibrated
usingpot HPMand the panelrnetercalibrationcan be fine tuned usingthe
adjustmentpot on the back of the meter.
6.19.14 Callbrate Panel Ammeter I Remote Arnpere Signal:
The motor currentis proportionalto the dc link currentderivedfrom the dc voltage

reading at test point IFB on NLJB-IC. Flead IFB - 1C using a DVIri and adjust
pot lM - lC such that:
Ammeter reading = .2 * IFB * lM
Where lM= Rated motor winding current, ac rms
6-32
LOADCOMMUTATED
INVERTER BHEL
/||-t lr|TErl .t
\rnAf I En t
DIAGNOSTICAND TROUBLESHOOTING
7.1 SELF TEST
7-1.1 Baslc Structure
The setftest routinesare procdures which may be executedby the HMPG resident
in the LCIcontrolto test individualHruBsand functions.Theseroutinesare executed
upon power-upif the TESTswitch on the NLCB is in the up poisition.The function
oi the self test is to test most of the control panel for the LCl, with great emphasis
placed on the testing of the ntrBs in the SEM/MEM.
Testing of the panel begins by performance tets of the hardware elements within
a neighborhoodof the HMP& microprocessorand continuesto testsof increasingly
remote hardware.All of the tests incorporated within the self test may be classed
into 3 groups:
1. - specifictests
FryVB
2. PairedP\ffEltests
3. Fanel-level
tests
7-1.1.1 PWB - speclflc tests
A great amount of effort has been placed on performing tests that will pinpoint
problems on specific Pv!tss first. lf any easily diagnosed problem exists, it will
be clearly spelled out to the operator.Test such as these comprise the pwb -
Specific test group.
7-1.1.2 Paired PWB Tests
icsrswnrcirdeireiroori lne operattonot severalPWBSare classedwithin the pairexl

PWEIgroup. Diagnosticmessagesfor test failures will indicate a functional problem
and also a list of possible solutions which may be general in nature.
7-1.1.3 Panel-level Tests
Panel-leveltests also require correct operation of several PWBs or modules, how-

ever, these tests are segregated to allow the user to perform either a module-level
test (involvingonly the control SEM/MEM)or a complete panel-leveltest would
include this last category of procedures.
7-1
BHEL INVERTER
LOADCOMMUTATED
From a practical point of view, the sequence of testing within the control SEM
progresses in the following rnanner:
1. HMPG
2. HLCB
3. HAIA
4. NSFC (source)
5. NSFC (load)
6. NSFE
7. NLCB
8. NLIB (source)
9. NLIB(load)
10. HtsA
11. HRDA
,
12. HTCA(if used)
Furthertestswhich includeHffBs outsidethe SEM/MEM,optionaltest for for series

12, - pulse and tach feedback circuits progress in the following sequence:
1. Cableloadingfrom the SEM.
2, The l/O Module.
3. HLCB.slot 2H
4. SourceslaveNSFC
5. NBIE (series12-pulseonly)
6. HrcA (tachoption)
7. Fieldexcitermodule
8. Door rnodule
7-2
s
*
t
INVERTER
LOADCOMMUTATED BHEL
{
I
7-'|.2 Execudng the Tegts

i
The self routine may be initiated by by resetting the HMPG with the TEST switch
I
(on the NLCB)in the UP position.The entire test is completed in approx 2Oseconds.
At its completion,status infonnation will be printed out at the door-mounted printer.
Upon successfullcompletion of the self test, the drive will operate in the gate
test mode. To returnto normal operation,the NLCBstest switch must be returned
to the normal position and the HMPG must be reset.
cAlrnoN
*lf test et<ercisethe output relalp; thereforethe outputterminal
boards should be disconnected trom the I/O module and/or
source and load breaker should be racked-out drive stopped
before pertorming the test.
7-1.3 DlagnoCnglallures
As mentionedabove,faitureof the setf test procedureswill produce a diagnostic

messages:
DATE ]]ME FAILED AA=TESTNUMBER

(aabb) DURINGTEST OF bb=SUB-TESTNUMBER
description of test
PROBLEM: problem statement
POSSIBLE SOLUTION:
solution 1
solution 2
solution 3
Usually,a failurecan easily be diagnosedby the problem statement.At least one

solution will be suggested in the print out. lt is suggested that troubleshooting
be performed at the F{A/E}level (Fbplace the FlffB not its component}. Although
the diagnostic messagemay indicate specffic failures,itis not recommeded that
F\A/E}components be raplaced or repaired (write or attach the diagnosis to the
card).
7.3
BHEL INVERTEB
LOADCOMMUTATED
The TEST NUMBERand SUB-TESTNUMBERuniquely define a failure within the

(hex) as
seff test procedure. The TEST NUMBER is incremented from 1 to 36
vary
the test progress. For different test numbers, the SUB-TESTparameter will
of
froml up to the number of sub-testswithin that rnaior test. The description
to
lbsts section that follows details the complete self test procedure according
the TESTNUMBERand SUB-TESTNUMBER parameters'
7-1.4 DescrlPdonof Tests.
The tests listedcover the followingstandardelectronicmoduleversions:
1. LCGX-AC E(CTERLCISEM
2 LGJX-DCE(CTERLCISEM
3 MEM
LC[X- SERIE1z-PULSE
Jbst are identicalon all versionsup to test 2D'
The followinglist all tests availablewith sub-testinformation:
Test DescriPtion
Pos-
to F0O0:FFF)'
O. HMPGROMTST Readsallof RAMmemory(FO@:0
siblefailuresare
.0- BusHog error
.1- Read error
1. to 0:3FFF)pcssible
HMPGRAMTST Fteadallof RAM memory (OOO0O:
failuresare:
.0- BusHog error
.2 Read error
.3- Write error
2 HMPGINTFTTST
.1 Verifies control and data lines to HMPGs 8259 interrupt

controller
LOADCOMMUTATED
INVERTER BHEL
3. HMPG-TMR
.1 -Verifies addr lines & daA bit 6 & 7
.2 -Verifies addr lines & data bit 6 & 7
.3 -Verifies addr lines & data bit 6 & 7
.4 -Verifies data bit 5-0 with walking 'l pattern
.5 -Verifies that all outputs are free to toggle
.6 -FOR TMRO;Checks for null count = 1
.7 -FOR TMRO; Load TMR; checks for null count = O
.8 -FOR TMRO;Verify TMR time out
.9 -FOR TMRO;verify TMR reloads
.A -FOR TMRI; Checks for null count = 1
.B -FOR TMRI; Loads TMR; checks for null count = 0
.C -FOR TMRI; Verify TMR time out
.D -FOR TMRl;Verify TMR reloads
.E -FOR TMR2: Checks fo null count = 1
.F -FOR TMR2; Loads TMR; check for null count = O
.10 -FOR TMR2; Verify.TMR time out
.11 -FOR TMR2:VerifiTMR reloads
d Hr.dPG*SfO_patrS
.1 - Check that trans and rec butfers are empty
5 HMPG STALL
.1 - Verify software reset of stall circuit
.2 - Initiate stall timer; checks for no stall after 1O0 ms
.3 - Verify stall asserted after 1.5 seconds
7-5
f'
t'
{'
r BHEL INVERTER
LOADCOMMUTATED
t
6 HMPG-INTR
.1 - Verify operation of bus hog interrupt
'2.Veritythatbushogdoesnotoccurforlegitimateread
.3 - Verify operation of time tic interrupt
7 DMPts
.1 - Checks that write enable switch is not asserted
.2 - Checks for no bus hog during EEPROM reads
.3 -Checks for expected pattern in EEPROM
S HLCB-PRES
.1 - Enable IMOK checks for OIMOK = O
.2 - Disable IMOK checks for OIMOK = 1
9 HLCB-DAK
.1 - Checks for no bus hog during reads of HLCB
A. HLCB-TMR-U2z
.1 - Verify addr lines & data bits 6 & 7
.3 -Verfi addr lines & data bits 6 & 7
.4 - Verifv data bits 5 - 0 with walking 1 pattern
.5 - Verify that all outputs are free to toggle
.6 -FOR TMRO; Checks for null count = 1
.7 - FOR TMRO; Loads TMR; checks for null count = 0
.8 FORTMRO;VerifYTMR time out
.9 - FORTMR0;VerifYTMR reloads
.A - FORTMRI; Checksfor null count= 1
7,4
?
r
BHEL
INVERTER
LOADCOMMUTATED
x
(
(
count = o
.E - FOR TMRI; LoacisTMR; checksfot null
t:
I
.c - FORTMR1;VerifYTMRtimeout
I
.D - FORTMRI;VerifYTMR reloads
=
.E - FOR TMR2;Checksfor null count 0
count =1
.F - FOR TMR2;LoadsTMR; checksfor null
out
. 1 0 - FORTMR2;VerifYTMR time
reloads
. 1 1 - FORTMR2;VerifYTMR
HLCB-TMR-U23
.2 -Verify addr lines & data bits 6 & 7
pattern
'4 - Verify data bits 5-0 with walking 1
.5 -Verfi that all ouputs are free to toggle

=
.6 -FOR TMRO; Checks for null count 1 .
count = O
.7 - FOR TMRO;Loads TMFI checks for null
.8 -FOR TMRO;VerifYTMR time out
.9 - FOR TMRO;VerifYTMR reloads

= 1
.A - FOR TMRI; Checkslor null count
null count = o
.B - FOR TMRI; Loads TMR; checks for
.C - FOR TMRI; VerifYTMR time out
.D - FOR TMRI; VerifYTMR reloads

= 1
.E - FOR TMR2; Checks lor null count
count = 0
.F -FORTMRA LoadsTMR; checksfor null
7-7
BHEL LOADCOMMUTATED
INVERTER
.10 - FOR TMR2; Verify TMR time

out
.ii - FOR TMR2; Venfy TMR retoads
.12 -FOR TMR2; Intializeto Mode O; verify

status
.13 - FOR TMR2; Load with 10 ms delay;

verify status
.14 - FOR TMR2; After 4 ms verify status
.15 - FOR TMR2; After 15 ms verify time

out
.16 - FOR TMR2; Check that count = O
C HLCB_INTR_PRES
.1 - Vedfy addr and data lines to HLCBs

8259
D HLCB-SIO
.1 - Intializeand check status of HLCBs g251
.2 - Verfi that singre byte of data is

sent by sensing status
.3 - Verifr transfer of data pattern

.
E HAIA-DM
.1 - Checks for no BusHog during

, reads of HAIA
.2 _ Checks for no BusHog during

writes to HAIA
F HAIA-PRES
.1 - Checks that HAfA is present \.-

by reading single bit
10 HAIA.TMR
.1 - Verify addr lines & data bits

6 & Z
.2 - Verify addr lines & data bits

6 & Z
.3 - Verify addr lines & data

bits 6 & 7
.4 - Verifies data bits 5-O with

walking 1 pattern
.5 - Verifies that all outputs are

free to toggle
7-8
BHEL
INVERTER
LOADCOMMUTATED
=
.6 - FOR TMRO;Checksfor null count 1
count = 0
.7 - FoR TMR0;LoadsTMR; checkslor null
lime out
- FOR TMRO;VerifYTMR
.8
.9 - FORTMRO;VenfYTMR reloads
=1
.A - FOR TMRI; Checksfor null count
count = 0
'B - FOR TMRI; LoadTMR; checksfor null
.C - FORruFil; VerilY TMR time out
.D - FORTtrl|RI;VerrfYTMR reloads
= 1
.E ' FORTMR2;Ghecksfor null count
count d)
.F - FOR TMR2;toads TMR: checksfor null
time out
.10 ' FORTMR2;VerifYTMR
reloads
.11 -.for TMR2;VerifYTMR
11. FIAIA-cot{vEFHoN
=1
.1 ' Start Ay'Dconversion;check that BUSY
2 - Checkthat IDAVAL = 0
that BUSY =
.3 - Wait for conversionto complete;check
o
-4 - Check that IDAVAL = 1
12. HAIA_PSUPPLY
.1 - Check that N15 supply is read correcdy
.2 - Check that P15 supply is read correcdy
13. NSFC_S-PRES
.1 - Set IMOK true; read back IMOK signal'
.2 - Set IMOK False; read back IMOK signal'
+-1
?
e
e
( BHEL LOADCOMMUTATED
INVERTER
14. NSF;-S-TMR_PffiS
.l _ Verifies addr lines & data bits 6

& 7
.2 - Verifies addr lines & data bits 6 & 7
3 - Verifies addr lines & data bib 6 & 7
.4 - Verities data bits 5-0 with watking 1 pattern
.5 - Verifies that all outputs are free to toggle
15. NSFC_S_ruODE
.1 - FOR TMRO; Checks for null count = 1
.2 - FOR TMRO;LoadsTMR; checksfor null count = O
.3 - FORTMRO;VerifyTMR time out

it
.4 - FORTMR0;VerifyTMR reloads rs
t"
t
.5 - FOR TMRI; Checksfor nutt count = 1
6
.6 - FOR TMRI; LoadsTMR;checksfor nult count = O f

v
,7 - FORTMRI; VerifyTMR time out
€
.8 - FORTMR1;VerifyTMR reloads
.9 - Performoperationto set pulse train to 0; verify
.A - In TESTMode;writeall on pattern,expectechoof same
.B - In TEST Mode;Watk 1 thru primary& firing latch
.c - In TEST MODE;See if plusetrain is stucktow
.D - In TEST MODE;See if plusetain is stuck high
.E - In TESTMODE;Checkthat plusetain is toggting I
I
l f
7-10
?
?
r INVERTER
LoAD coMMUTATED BHEL
'(
16. NSFc L PRES
{
.1 - Set IMOKbue; readbackIMOKsignle
{
1 .2 - Set IMOKfalse;read back IMOKsignal
17.NSFCL ruR PRES
.2 - Verifyaddr lines & data bits 6 & 7
.4 - Verfy data bits 5-0 with walking 1 pattern
.5 - Vedfy that all outputsare free to toggle

!
18. NSFCL TMODE
i .1 - FOR TMRO:Checksfor null count = 1
.2 - FOR TMRO;LoadsTMR; checksfor null count = O

1
.3 - FORTMRO;Verfi TMR time out

,
{ .4" - FoR TMRo;vertfYTMR reloads
5 - FOR TMRI; Checlisfor null count = 1

l
!. .6 - FORTMRI; LoadsTMFI checksfor null count = O
! .7 - FoR TMRI; VerE TMR time out

I
.8 - FORTMRI; VerifyTMR reloads
.9 - Performoperationsto set pulsetrain to O; verify

i .
.A - In TEST Mode, write all on pattern, expect echo of same
i .B - In TEST Mode, Wdk 1 thru primary & firing latch
\ .C - In TEST Mode, See if pulse is stuck low

I
.D - In TEST Mode, See if pulse is stuck high
(
( .E - In TEST Mode, Check that pulse train is toggling
(
t
7-11
BHEL LOADCOMMUTATEDINVERTER
19. NSFE_PRES/NSFF-PRES
.1 - Set IMOKtue; readbackIMOKsignal
.2 - Set IMOKfalse;read back IMOKsignal
1A NSFC-TMR_PRES/NSFF-TMR-PRES
.1 - Verifiesaddr lines & data bits 6 & 7
.3 - Verifiesaddr lines & data bits 6 & z
.4 - Verifiesdata bits $o with wdking 1 pattern
.5 - Verifiesthat all ouput are free to toggle
1B NSEF-TMODE/NSFF-TMODE
.1 -- FOR TMRO;Checksfor null count = 1

.2 - FOR TMRO;LoadTMR; checksfor null count = O
.3 - FORTMRO;VerifyTMR time out
.4 - FORTMR0;Verfi TMR retoads
.5 - FOR TMRI; Checksfor null count = 1
.6 - FOR TMRI; LoadsTMR: checksfor null count = O
.7 - FORTMRI; Verify TMR time out
.8 - FORTMRI; VerifyTMR retoads
.9 - Performoperationsto set pulse bain to O; verify
.A - In TESTMode,writeallon pattern,expectechoof same
.B - ln TEST Mode,walk I thru primary& firing latch
.C - In TEST Mode,see if pulse is stuoklow
.D - ln TEST Mode,see if putseis stuck high
.E - In TEST Mode,Checkthat pulsetrain is toggling
7-12
INVERTER
LOADCOMMUTATED BHEL
1C NSFC-S_PLL
. .1 - FOR TMR2: Enables PLL; Checks for null count = 1
'2 - FOR TMR2: Loads TMR2; checks for null count = o
.3 - FOR TMR2: VerifYTMR time out
.4 - FOR TMR2: VerifYTMR reloads
lD NSFC-L-PLL
.1 - FOR TMR2: Enables PLL; Checks for null count = 1
.2 - FOR TMR2: Loads TMR2; checks for null count = 0
.3 - FOR TMR2: VerifYTMR time out
.4 - FOR TMR2: Verufy TMR reloads.
lE NSFE-PLUNSFF-PLL
.1 - FOR TMR2: Enables PLU Checks for null count = 1
.2 - FOR TMR2: Loads TMR2; checks for null count = O
.3 - FOR TMR2: Verify TMR time out
. .4 - FOR TMR2: Verufy TMR reloads
.IF
ROLL-CALL
.1 - Test for ribbon cable connectingHAIA(JA)to SEM(JG)
.2 - Enable NLCB IMOK check for IMOK true
.3 - Disable NLCB IMOK check for IMOK false
.4 - Brable NUBS IMOK check for IMOK true
.5 - Disable NUBS IMOK check for IMOK false

,
.6 - Enable NLIBL IMOK; check for IMOK tue
.7 - Disable NLIBL IMOK; check for IMOK false
7-13
?
C
C
BHEL LOADCOMMUTATED
INVERTER
f
{
20. NLCB-DIFFJMPS
T
t- .1 - Tesi for 0 voits ai REFO
.2 - Test for O volts at TREFO
.3 - Test for 0 volb at 12PREFO
.4 - lnjectcurrentin REFOcircuit;test for changein output
.5 - Injectcurrentin TREFOcircuit testfor changein output
.6 - lnjectcurrentin
l2PREFOcirct.tiBtestforchangeinoutput i
7 - Test for 0 volb at SP (speed)

f
.8 - Reset exitingfaulb; test for 1OSP (overspeed)=O {

t.
21. NSFEjf{ALOq/NSFF_rANAISG
6
.1 - Resetfor El(excitercunent) = 0 volts

*
.2 - Test for no currentimbalance 6
B
.3 - Inject signal in cunent circuit;testfor output change
f
.4 - Again,test for cunent imbalance

6
.5 - Excitercunent circuitW55 Hz input; wdfi current im-

balance is detected f
.6 - Wait 100 ms; verify no cunent imbalancecondition
22. HLCB SQ WAVES
.1 - Test for absenceof SQ wav€swith oscillatoroff
.2 - Test for any activity(gourceor load) with oscillatoron
.3 - Checkfor activityon each of the 3 source channels
,4 - Verifysourceside VA channelactive
.5 - Verrfysourc€side VB channelactive
.6 - Verify sourceside VG channelactive
.7 - Test phasesequenc€of source SQ waws
.8 - Checkfor activityon each of the 3 load channels
7-14
c
c
C LOADCOMMUTATED
INVERTER BHEL
( .9 - Verify load side VB channel active

(
.A - Verify load side VB channel active
(
( .B - Verify load side VB channel active
' .C -Test phase sequence of source SQ waves

(
23, NUB S ANALOG
r .1 Reset existing faults; verify UV & not OV condition
.2 - Verify not SUPPressioncondition
3 -VerifylUVTO=O
!
.4 - Test C17 tor time delay (Undervoltagecircuit)
.5 - Test C37 tor time delay (Overvolta$e circuit)
{ .6 - Test for 0 volts at IFBS
7 - Test for 0 volts at FLUX BAS

i
.8 - lnject cunent in source current conditioncircuit. Detect
t
change in IFBS.
/ -
.9 - Detect change FLUX BAS
t
( .A - For FLUX BAS: Check for 0 volts dc offset
{
.B - For FLUX BAS: Check level of positive peak
i .C - For FLUX BAS: Check level of negative peak
24. NUB-L.AMLOG
I
.1 - Reset existing faults; verify UV & not OV condition
( - Verity not SUPPressionennditiop

.2
{
.3 - Verify 1UW0 =0
.4 - Test C17 tor time delay (Undervoltagecircuit)
.5 - Test C37 tor time delay (Overvoltagecircuit)
.6 - Test for O volts at IFBL
7-15
BHEL LOADCOMMUTATEDINVERTER
.7 - Test for 0 volts at FLUX BAL
.8 - Injectcunent in sourcecurrentconditioncircuit. Detect

^L^6^^ i^ tEEc
urrqrr!,g lll ll 9v'
.9 - Detect change FLUX BAL
.A - For FLUX BAL: Check for 0 volts dc offset
.B - For FLUX BAL: Check level of positive peak
.C - For FLUX BAL: Check level of negative peak
.D - For FLUX CBL: Check for O votts dc ofiset
.E - For FLUX CBL: Check level of positive peak
.F - For FLUX CBL: Check level of negative peak \-
.10 - For FLUX ACL' Check for O volts dc offset
.11 - For FLUX ACL: Check level of positive peak
.12 - For FLUX AGL: Check level of negative peak
2s. HLCB_|NA
.1 - Enabletest oscillator;
venfyoccurrence
of sourcezero
crossinginterrupt(slaveintenupt O)
.2 - Verify frequencyof source zero crossingintenupt
.3 - Enabletestoscillator;
verifyoccurenceofloadzerocross-
ing interrupt(slaveinterrupt1)
.4 - Vertfyfrequencyof load zero crossinginterrupt !
.5 - Verifyoccurrehceof sourcefiring interrupt
.6 - Verify occurence of load firing interrupt
.7 - Verifyoccurrenceof field liring interrupt
26. NLCB_SPEED
.1 - Enabletest oscillator;verifyspeedcicuitsreads55 Hz
.2 - Verifyno overspeedcondition.
27. HISA_PRES
.1 - Disable IMOK; verify by reading backbit
.2 - Enable IMOK; verify by readingbackbit
7-16
INVERTER
LOADCOMMUTATED BHEL
28. CABI-E_CONT
.1 - Testsfor continuityin ribboncablefrom SEM, JA, to

l/6 llazllla
l, v alrvss.e
.2 - Testsfor continuityin ribboncablefrom SEM, JK to

' l/O Module
.3 - Tests for continuityin ribbon cable from SEM, JH, to

l/O Module
.4 - Tests for continuityin ribbon cable from SEM, JB, to

door Module
29. HtSA_lO
1 - Set all inputsfrom UQ Modulehigh; verfi by reading

back input to HISA
.2 -Setall inputsfrom l/O Modulelow; verifyby readingback

input to HISA
?A PIOs-SUPPLY-CHECK
;1 -Checkthat 105 volt dc powersupplyis OK
28 HROA-IA-IO:
In sequence;pick up signalrelayson the HROAin slot 1A of the VO

module.Expectfeedbick signalto indicatechange.
.1 - Forceall HROA(IA)retaysto dropout; verfi byfeedback
.2 - Force 105 Vdc relays to pick-up;venfy by feedback
.3 - Dropout 105Vdc relays,wait 4Oms, verify by feedback
.4 - Pick-upsingle 28 V relay;verify by feedback
.5 - urop-outali lelays,venty by leedback
.6 - Pick-upsingle28 V relay:verifyby feedback
.7 - Dropout all relays;verify feedback
.8 - Pick up single 28 Y relay;verify by feedback
.9 - Drop out all relays;verify feedback
.A - Pick-upsingle28 V relay;verifyby feedback
.B - Drop-outall relays;verify feedback
7-17
BHEL LOADCOMMUTATED
INVERTER
2C HROA_1B_|O:
In sequencerpick up single relays on the HROA in stot 1A of the l/o

nnodule.Expectfeedbacksignalto indicaiechairge. .
.1 - Forceall HROA(IA) relaysto drop-out;verify byfeedback
.2 - Force 105 Vdc relays to pick-up; verify by feedback
.3 - Drop out 105 Vdc relays,wait 4O ms, verify by feedback
.4 - pick-up single 2g V relay; verify by feedback
.5 - Drop-out all relays; verify by feedback

t
.6 - Pick-upsingle 28 V relay;verify by feedback
.7 - Drop-out all relays; veirify.feedback

F
.8 - Pick-up single 28 V relay; verify by feedback n

:.
.9 - Drop-out all relays; verify by feedback
6
.A - Pick-up single 28 V relay; verify by feedback €
.B - Drop-out all relays; verify feedback

e
2D NLCB_R_DVR
€
.1 - Verify presenceof HROA in slot 18 of VO Module e
.2 - Verifypresenceof HROAin slot 1A of UO Module

:
.3 - Forcerelaydriverson NLCBon; verifyresponsefrom
l/O Modulevia feedback
.4 - Force relays drivers on NLCB on; verify response from

l/O Module via feedback
2gLCG, LGJ HrcA PRES
.1 - Disabte IMOK; verify by reading back bit
.2 - Enabte IMOK; verifr by reading back bit
2FILCG, LC.' HTCA 829 TST
.1 - Check for U1 timer present
.2 - Check for U1 timer 1 ok
7-18
C
?
?
INVERTER
LOADCOMMUTATED BHEL
(
.5 - Check tor U2 timer present
{
( .5 Chcck tor U2 timei-1 ok
(
.7 - Check tor U2 timer 2 ok
I
.8 - Check Ior U2 timer 3 ok
3O/LCG LGJ HrcA TACH COUNT TST
.1 - Free run counterand verifythat each counterbit toggles
.2 - Sets each bit in the max count register and watches

countermaximum
.3 - Loads2 differentbit patternsinto count registerand looks

to verify that the patterns ere properly loaded
3ULCG LCJ HrcA_PS12-TST
.1 - Check that the +12 Vdc tach power supply is ok
3ALCG LCJ HTCA-CABLE_TST
.1 - Check that the cable is plugged in JA of HTCA card
33/LGJ FLD_E(C_MODiTTEN (DC Field Only)
.1 - Check for presenceof ac on SFG/SFH Module, via the

cell state sensors
.2 - Verify line voltage present bit (HAIA 9OOA:7)is zero
.3 - Verify all cells are not on, via the cell state sensors
.4 - Verify celf 1 turns off, via the cell stale sensors

i
.5 - Verify cell 3 furns off, via the cell state sensors
.6 - Verify cell 5 tums off, via the cell state sensors
.7 - Verify cell 4 turns off, via the cell state sensors

(
i r .9 - Verify cell 2 turns off, via the cell state sensors
\ .A - Check negativelevel (3.15- 5.64 Vrms) of the ac input

voltage
.B - Check positive level of the ac input voltage

:
7-19
INVERTER
LOADCOMMUTATED
BHEL
ac input voltage
.C . Check dc offset ol the
.D-Gheckthatexciteroutputvoltage(EV)is<0'5
is < 0'5
'E - Gheck that exciter output voltage
is < 0'5
.F - Check that exciter current (B)
0'5
.10 - Check that exciter current is <
for cells 1'3'5
- While sampling cell state sensor pattems
'11
are operational
verify that cell state sensor
thru cells 1'3' and 5
12. - Verify phase A zero-crossing
cell
A by finding correct second
'13 - Verity phase C follows
data)
state Patterh (in samPled
cell
C by finding colect'third
'14 - Verify phase B tollows
data' (Gomplete phase
tt"iJ p"o*n in sanrpled
reversal check')
pattems for cells 4'6'2
.15 - While sampling cell state sensor
are operational
u"'if in"t'cell state sensors
celb 1'3' and 5
.16 - Verify phase A zero-crossingihru
A by finding correct second

-17 - Verity phase C lollows
Pattern
pattern
C by finding conect third
.18 - Verify phase B follows
3 4 l L c G F L D _ E ( o - M o D A C J T T N ( A C F i e l d o n l y ) v
the SFFJSFFmodule'
.1 - Check for no absence of ac on
via the cell state sensors
the cell state sensors
.2 - Verify presenceof ac phase A' via

.3 - Verify presence ol ac phase B' via

'4 - Verify presenceof ac phase C' via
.5 - Check level of the ac input voltage
voltage
.7 - Check dc offset of the ac input
is equal to 0
.8 - Check that exciter output voltage
INVERTER
LOADCOMMUTATED BHEL
.9 - Check that exciterouput voltageis equal to O
.A - Check that excitercunent is equal to 0
.B - Check that excitercunent is equal to 0
.C - While samplingcell state sensor pattems,vedfy that

cell state sensorsare operational
.D - Venfy correctcell state patternis in sampleddata
.E - Verifyphasesequenceof SFUSFF Moduleinputvoltage

by finding correct seQondcell state pattern in
sampleddata
.F - Venfyphasesequenceof SFEISFFModuleinput
voltageby finding correct third cell state pattem in
sampleddata (Coppletionof phase reversalcheck)
34LC., F|-O-D(C-MOD-1PI{ASE(DC Field Only)

nsingle phaseoperationof SFGISFHmodule,A-B*
.1 - Waitingfor negalivelevel of field excitersync signal
2 - Waiting for positive edge of field exciter sync signal
.3 - After delay, fire conect SCR pair, verify via cell state
sensors then tum-off all cells
.4 - After 5 cycles, veri! that el<citercunent < 0.5 per unit
.5 - Waitingfor positivelevel of field excitersync signal
.6 - Waitingfor negaliveedge of field excitersync signal
.7 - After delay, fire correctSGR pair; verify via cell state

sensorsthen tum-off all cells
.8 - After 5 cycles,verifythat excitercunent < 0.5 per unit
r€ingle phaseoperationof SFG|/SFHmoduleB-Cn
.9 - Waitingfor negativelevel of field excitersync signal
.10 - Waitingfor positiveedge of field exciter sync signal
.11 - After delay, lire correct SCR pair; verify via cell state
sensorsthen turn-offall cells
.12 - After 5 cycles,verifythat excitercurrent< 0.5 per unit
7-21
(-
e
INVERTER
LOADCOMMUTATED
r BHEL
(
signal
.13 - Waiting for positive level of field exciter
exciter signal
.14 - Waiting for neoative edge of field
verify via cell state

'15 - After delay' fire correct SCR pair;
cells
sensors' then turn-off all
current < 0'5 per unit
'16 - After 5 cyclas' verify that exciter
*€ing|ephaseoperationo|SFG/SFHmodulec-A*
sync signal
.17 - Waiting for negative level of field exciter
sync signal
'18 - Waiting for positive edge of field exciter
via cell state
.19 - After delay' fire correct SCR pair; verify
sensors then turn-off all cells
per unit
that exciter Current < O'5
.20 - After 5 cycles' verrty
signal
level of field exciter sync
.21 - Waiting for positive
signal
edge of field exciter sync
'22 - Waiting for negative
.2g-Afterdelay'firecorrectSGRpair;verifyviacellstate
cells
sensors then turn-off all
< O'5 per unit
.24 -After 5 cycles' verify that exciter current
(AC Field Onlv)

35/LCG FLD-E(C-MODAC-IPHASE
A-Bs
**Single phase operation of SFFJSFFmodule'
exciter sync signal

.1 - Waiting for negative level of field
exciter sync signal

.2 - Waiting for positive edge of field
verify via cell state

.3 - After delay' fire correct SGR pair;
sensors
sync signal
.4 - Waiting for positive level of field exciter
exciter sync signal

.5 - Waiting for negative edge of field
.6 .Afterde|ay,firecorrectSCRpair;verifyviace||state
sensors
1
< O'5 per unit

.7 - After 5 cycles,verifythat excitercurrent
*€ingle phaseoperationof SFBSFFmodule'B-Cn
7-22
C
?
f INVERTER
LOADCOMMUTATED BHEL
( - Wailingfor negativelevel of field excitersync slgnal

.8
(
.9 - Waitingfor positiveedge of field excitersync slgnal
{
( .A - After delay, fire correct SCR pair; verify via cell state
sensors
.B - Waitingfor positivelevel of field excitersync signal
.C - Waitingfor negativeedge of field excitersync signal
.D - After delay, fire correct SCR pair; verify via cell state
sensors
.E - After 5 cycles,verifythat excitercurrent< 0.5 per unit
*€ingle phaseoperationol SFE/SFHmodule,C-A*
.F - Waitingfor negativelevel of field excitersync signal
.10 - Waitinglor positiveedge of field excitersync signal
.11 - After delay, fire correct SCR pair; verify via cell state
sensors
.12 - Waitingfor positivelevel of field excitersync signal
.13 - Waitingfor negativeedge of field excitersync signal
sensors
DOOR_MOD-PRES
.1 - Test for CTS asserted
.2 - Test for DSR asserted
2E]LCL HLCB2-PRES
.1 - Enables IMOK checks for 0IMOK = O.
.2 - Disables IMOK checks for OIMOK =1.
aFILCL HLCB2-DM
.'l - Checks for no Bushog during reads of HLCB (2H).
3O|LCL HLCB2_TMR-U22
7-23
.3 - Verifies addr lines & data bib 6 & 7
.4 - Verifies data bits 5-0 with walking 1 pattem
.5 - Verifies that all outputs are free to toggle.
.6 - FOR TMRO: Checks for null count= 1
.7 - FOR TMRO: Loads TMR; checks for null count = 0
.8 - FOR TMRO: Verify TMR time out
.9 - FOR TMRO: Verify TMR.reloads
.A - FOR TMRI: Checks for null count = 1
.B - FOR TMRI: Loads TMR; checks for null count = O
.C - FOR TMRI: Venfy TMR time out
.D - FOR TMRI: Verify TMR reloads
.E - FOR TMR2: Checks for null count = 1
.F - FOR TMR2: Loads TMR: checks for null count = 0
.11 - FOR TMR2: Verify TMR reloads
31/LCL HLCB2-TMR-U23
.4 - Verifiesdata bits 5-0 with walking 1 pattern
.5 - Verifiesthat all ouputs are free to toggle.
.6 - FOR TMRO:Checksfor null count= 1
.7 - FOR TMRO:LoadsTMR; checksfor null count = 0
.8 - FORTMRO:VerifyTMR time out
.9 - FORTMRO:VerifyTMR reloads
7-24
LOADCOMMUTATED
INVERTER BHEL
.A - FOR TMRI: Checksfor null count= 1
.B - FOR TMRI: LoadsTMR; checksfor null count = O
.C - FOR TMRI: Verfi TMR time out
.D - FORTMRI: VerifyTMR retoads
.E - FOR TMR2:Ghecksfor null count = 1
.F - FOR TMR2:LoadsTMR; checksfor null count = O
.10 - FORTMR2:Verifytime out
.11 - FORTMR2:VerifyTMR reloads
.12 - FOR TMR2:Initialiizeto modeO;verfi status
.13 - FOR TMR2:Loadwith 1Oms delay;verifystatus
.14 - FORTMR2:After4 ms, verifystatus
.15 - FORTMR2:After 15 ms, verifytime out
.16 - FOR TMR21:Gheckthat count = O
3?LCL HLCB2_S|O
.1 - Initializeand check status of HLCBs 8251
.2 - Verify that single byte of data is sent, by sensing status
.3 - Vedfy transfer of data pattern
33/LCL NSFC_S-SI.AVE_PRES
.1 - Set IMOK tue; read back IMOK signal
.2 - Set IMOK false; read back IMOK signal
34/LCL NSFC_S-SI-AVE_TMR-PRES
.4 - Verifies data bits 5-O with walking 1 pattem
.5 - Verifies that all outputs are free to toggle
7-25
f:
o
{'
BHEL LOADCOMMUTATED
INVERTER
{
35/LCLNSFCS SI.A\E ruODE AND NSFCS SI-AVEPLL
.1 - FOR TMRO: Checks for null count = 1
.2 - FOR TMRO:loads TMR; checksfor nullcount=O
.3 - FORTMRO:VerifyTMR time out
.4 - FORTMRO:VerifyTMR reloads
.5 - FOR TMRI: Checksfor null count = 1
.6 = FOR TMRI: LoadsTMR: checksfor null count = O

€
7 - FORTMRI: VerifyTMR;time out G
t
.8 - FORTMRI: VerifyTMR;'rdoads
C
.9 - Pedormoperationto set pulse train to O; verfi C
.A - In TESTMode,writeall on pattern,expectecho of same t

c
.B - ln TEST Mode,walk 1 thru primary& firing latch
e
.C - In TEST Mode,see if pulse train is struck low t
- In TEST Mode,chec* that pulse train is struck high €

.D
e
.E In TEST Mode,check that pulse trian is toggling f;
.F FOR TMR2: EnablesPLL Checksfor null count = 1 G

e
.10 - FOR TMR2:LoadsTMR; checksfor null count = O
.11 - FORTMR2:VerifyTMR time out {
.12 FORTMR2:VerifyTMR reloads

{.
36ILCLNB|E_IHJNALOG
.1 - afterreset,verifyno SUPP2or CIB
.2 - forceSUPP2and ClB.fault
.3 - Verifycan clearCIB fault
.4 - Verifycan clearSUPP2fault
3ILCL HTCA-PRES
.1 - Set IMOK true; read back IMOK signal
.2 - Set IMOK false; read back IMOK signal
7.26
C
C
? INVERTER
LOADCOMMUTATED BHEL
f 38/LCL HTCA_8254_TST
(
.1- .11 areforU1
t
( .1 - Verifiesaddr lines & data bib 6 & 7
t .2 - Verifiesaddr lines & data bits 6 & 7

i
I .4 - Verifiesdata bits 5-0 with walking 1 pattern
,5 - Verifiesthat all outputsare free to toggle
.6 - FOR TMRO:Ghecksfor null count = 1

i
.7 - FOR TMRO:LoadsTMR; checksfor nullcount=o
.8 - FORTMRO:VerrfyTMR time out

|'
{ .9 - FORTMRO:VerifyTMR reloads
.A - FOR TMRI: Ghecks for null count = 1

(
.B - FOR TMRI: Loads TMR; checks for null count = O
(
'
.c - FOR TMRI: Verify TMR; time out
.D - FOR TMR1: VerrfyTMR; reloads

(
.E - FOR TMR2: Checks for null count = 1
(
.F - FOR TMR2: Loads TMR; checks for null cou;tt = O

(
. 1 0 - FOR TMR2: Verify time out
. 1 1 - FOR TMR2: Verify TMR reloads

. 21 - .31 are lor U2
I . 2 1 - Verifies addr lines & data bits 6 & 7

{
(
.24 - Verifies data bits 5-0 with walking 1 pattern
.25 - Verifies that all outputs are free to toggle.

(
.26 - FOR TMRO: Checks for null count= 1
I
7-27
BHEL LOADCOMMUTATED
INVERTER
,27 - FOR TMRO: Loads TMR; checks for null count = 0
.28 - FOR TMRO: Verify TMR time out
.29 - FOR TMRO: Verify TMR reloads
.2A - FOR TMRI: Checks for null count = 1
.28 - FOR TMRI: Loads TMR: checks for null count = O
.2C - FOR TMRI: Verify TMR time out
.2D - FOR TMRI: VerifyTMR reloads
.2E - FOR TMR2: Checks for null count = 1
.2F - FOR TMR2: Loads TMR; checks for null count = O
.31 - FOR TMR2: Verify TMR reloads
39/LCL HTCA TACH COUNT TST
.1 - free run counter and verify each counter bit toggles
.2 - set each bit in the max count register watch counter

maximum
.3 load and ver'rtyZdifferentbit patterns into the count register
3A/LCL HrcA_PS12-TST
.1 - check high position count bit 7 for zero (P12 ok)
3B/LCL HrcA-CABLE_TST
.1 - check high positioncount bit 6 for zero (cableconnected

to tab)
3C/LCL FLD_E(C_MODAC_ATTEN(for ac field exciter only)
,1 - check for no absence of ac on the SFESFF module

via the cell statersensors
.2 - Verify presence of ac on phase A via the cell state sensors

{
.3 - Verfy presenceof ac on phase I via the cellstate sensors
i
.4 - Verifypresenceof ac on phase C via the cellstatesensors
7'2e
LOADCOMMUTATED
INVERTER BHEL
.7 - Gheec* dc offset of the ac input voltage
.8 - Checkthat exciter output voltageis equal O
.9 - Checkthat exciter output voltageis equal O
.A - Check that excitercurrentis equal to 0
.B -Checkthat excitercurrentis equalto 0
.C - Whilesamplingcellstatesensorpatterns,verifythat cell
statesensorsare operational
.D - Verify correctcell state patternis in sampleddata
.E - Verifyphasesequenceof SFE moduleinputvoltageby

findingconect secondcell state patternin sampleddata
.F - Venfyphasesequenceoisfe moduleinputvoltageby
finding correct third cell state patterni;r sampleddata
(Completionof phase reversalcheck)
3C/LCLFLD-E(C-MOD-ATTiI(for dc field only)
.1 - Checkfor presenceof ac on SFG/SFHModule,via the

cell state sensors
.2 - Verfy line voltage presentbit (HAIA90044 is zero
.3 - Verrfyall cells are not on, via the cell state sensors
.4 - Verify cell 1 tums off, via the cell state sensors
.5 - Verifycell 3 turns off, via the cell statesensors
.L . Verifyc.:ii 5 {.;:;i;.u{i, via the cell statesensors
.9 - Verifycell 2 turns off, via the cell statesensors
.A - Checknegativelevel (3.15- 5.64Vrms)of the ac input

voltage
.B - Check positive level of the ac input voltage
7-29
t''
BHEL LOADCOMMUTATED
INVERTER
.C - Check dc offset of the ac input voltage
.D - Check that exciter output voltage (E\4 is < 0.5
.E - Check that exciter output voltage is < 0.5
.F - Check that exciter current (El) is < 0.5
.10 - Check that exciter current is < 0.5
.11 - Whilesmaplingcell state.sensorpattemsfor cells 1,3,5

verify that cell stratesensor are operational
12. - Verfi Phase A zero-crossingthru cells 1,3, and 5
.13 - Verify phase C follows A by finding correct second cell

state pattern in sampled data
.14 - Verify phase B follows C by finding correct third cell

i
state pattern in sampled data. (Complete phase reversal
€
check.)
t
.15 - While sampling cell state sensor pattems for cells 4,6,2
t
verify that cell stiate sensors are operational
.1S - Verify phase A zero-crossingthru cells 1,3, and 5
.17 - Verify phase C following A by finding correct second

paftern
- Verify phase B follows A by finding correct third pattern {

.18
3D/LCL FLD_EG_MODAC_IPHASE (for ac field only)
*€ingle phase operationof SFE/SFFmodule,A-B*
.1 - Waiting for negative level of field exciter sync signal
.2 - Waiting for positive edge of field exciter sync signal
.3 - Afterdelay,fire correctSCR pair;verifyviacelstatesensors
.4 - Waiting for positive level of field exciter sync signal
.5 - Waiting for negative edge of field exciter sync signal

{
sensors
.7 - After 5 cycles, verify that exciter current < 0.5 per unit
*Single phase operationof SFVSFF module, B-Cn
7-.30
C
f
? LOADCOMMUTATED
INVERTER BHEL
( .9 - Waiting for positive edge of field exciter sync signal

{
.A - After delay, fire correct SCR pair; verify
via cell state
sensors
(
.B - Waiting for positive tevel of field exciter
{ sync signal
.C - Waiting for negative edge of field excirer sync

signal
.D - After delay, fire correct SCR pair; verity via

cell state
sensors
.E - After 5 cycles, verify that exciter current < 0.5 per

unit
*Single phase operationof SFEISFF
module,C A#
.F - Waiting for negative level of lield exciter sync signal
.10 - Waiting for positive edge of field exciter sync signal
.11 - After delay, fire correct SCR pair; verify via cefl state
sensors
.12 - Waiting for positive level of field exciter sync signal
.13 - Waiting for negativg edge of field exciter sync signal
.14 - After delay, fire conect SCR pair; verify via cell state
sensors
.15 - After 5 cycles, verify that exciter current < O.5 per unit
3D/LCL FLD_EG_MOD_IPHASE (for dc fietd onty)
* Singlephase operation
of SFG/SFHmodule,A-EIfr
i r .2 - Waiting for positive edge of field exciter sync signal
.3 - After delay, fire correct SCR pair, verify via cell state
sensors then turn-off all cells
.4 - After 5 cycles, verify that exciter current < O.5 per unit
.5 - Waiting for positive level of field exciter signal
.6 - Waiting for negative edge of field exciter signal
.7 -Afterdelay,firecorrectSCR pair;verifyvia cellstatesensors

then turn-ofi all cells
.8 - After 5 cycles,rrerifythat excitercurrent< 0.5 per unit
*€ingle phaseoperationof SFG/SFHmodule

B-C*
7-31
BHEL LOADCOMMUTATED
INVERTER
.9 - Waitingfor negativelevel of field excitersync signal
.11 - After delay,fire correctSCR pair; verifyvia cell state

.13 - Waitingfor positivelevel of field excitersignal
.14 - Waitingfor negativeedge of field excitersignal
.15 - Afier delay, fire correct SCR pair; verify via cell state
.16 - After 5 cycles,verifythat excitercunent < 0.5 per unit

*€ingle phaseoperationof SFG/SFHmoduleC-An
.17 - Waitingfor negativelevel of lield excitersync signal
sensorsthen tum-offall cells
z
.2O - After5 cycles,verifythat excitercurrent< 0.5 per unit
.21 - Waitingfor positivelevel of field excitersignal
.22 - Waitingfor negativeedge of field excitersignal
.24 - After 5 cycles,verfi that excitercunent < 0.5 per unit
3E DOOR-MOD_PRES
.1 - Testfor CTS asserted
.2 - Test for DSR asserted
7.2 GATE.TEST.MODE !
\
7-2.1 General
The gate test mode allows off-linetesting of much of the analog signal conditionirq,
i
microprocessor firing control, and gate pulse generation circuitry. In the gd+
test-mode, a local test oscillator supplies 3 phase, approxinmately 60 Hz signds ;
inp|aceoftheattenuatedbussigna|sfromthesourceand|oadbridges..Ihe.-
7-32
INVERTER
LOADCOMMUTATED BHEL
electronic controls can then lock onto these signals and generate signals to 'dry
fire" the thyristors in both bridges. Thyristor gate pulses may then be examined
for proper magnitude and phasing. Firing may be adiusted between advance and
retard limit for each bridge. In the gate-test-mode, the control produces pulse
train firing, thus it is necessay to run the converter ventilating fans for this test.
To perform the following tests, a dual channel osciloscope with voltage probes
and a current probe is required.
7-2.2 GetUng Into Gate-Test-Mode
A. The drive should be stopped,primaryswitchgearandlor transformer

isolationswitch(if any),and loadisolationdevice(if any)shouldbe open.
Checkthesoftwareldder diagramin thesystemelementary for anyother
conditionthatmustbe met.
B. Putthe NLCB(1E)TEST'switch(SW1)in thetestposition.
**NOTE**
Nways use coupling on the oscilloscope channels.
7-2.3 Gate-Test-ilode Checil<out

'FCBFf
A. Connect channel one of the oscilloscopelo NUB (1D) flPs) and
channeltwo of HLCB (2E)1/Al' ffP12).Trigger the scope on channelone
and verify the waveformslook like Figure 7-1.
'FCBFf
B. Connectchanneloneof the oscilloscopeto NUB (1D) fIPs] and
channeltwo to HLCB (2E) [nt13).Trigger the scope on channelone and
verily the waveformslook like Figure 7-1.
C. Connectchannelone of the oscilloscopeto HLCB (2Q :VAl" fIPl2) and

trigger on this signal. Adjust the variable time/ division scale so that one
periodequalssix maiordivisions.(i.e.,6Odegreesper ma;ordivisionor 12
degrees per minor division)
D. One at a time, connect channel two to SlCl thru SlG6 on the source side
NSFC (2C) ffp1 thru TP6) and veritythat the gate pulses are positionedas
in Figure7-2.
For driveswith a seriestwelve-pulsesource, also check SlGl- SIGOon the

source B NSFCcard (slot ill.llerfi that the gate pulse are positioned as
in Figure7-2 except for a 3Odegrees lag or lead depending on the setting
of SQDRTSTbit A.
7-33
BHEL LOADCOMMUTATED
INVERTER
FCBRCTPS)
NUB( tc) .' ( r D)
€
f
e
t
. e
Y r (rPrz)
vA2 0Pr5) (
Hr-cE-(2o'
(
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stcl (fPt) i
l|sFc (2c,
(FUurIw r{CE)
s|GI CTPI)
lrsFc (2C)
(FU[rnErARD)
7-34
C
C
? LOADCOMMUTATED
INVERTER BHEL
T
(
(
(
i
(
(
(
v t ffPlz)
v 2 crPlJ)
H!C8 (28)-
srct fiPl)
NSFC (2C)
(
t
(
I
( srcs(rPJ)
NsFc12ct
(
(
( src4 fiP4)
ilsfc (zct
(
(
sc5 fiPs)
( Nsrc (2ct
{
(
t src6 crPs)
Nsrclzct
{
(.
/
(
7-35
BHEL LOADCOMMUTATED
INVERTER
Note:
The firing angte can be adjusted by wrying the speed demand

reference (place in 'LOCAL'and adjust "LOCAL Rtr),
Connectchannelone of the oscilloscopeto HLCB (2El \lM'fiPl3) and

trigger on this signal.Adjust the variabletime/divisionscale so that one
period equalssix major divisions.(i.e.,6Odegrees per rnaior division or
120degreesper minor division).
One at a time, connect channeltwo to SlGl thru SlG6 on the load side
NSFC (28) (IP1 thru TP6) and verify that the gate pulses are positioned as
inFgureT-2.
Verifythat each of the red gate pulse LEDs on the HPTK cards in the leg
cell modulesis illurninatedindicatingthat the cell getting pulses.
H. Wth a current probe, look at the gate, pulse of each thyristor while
simultaneouslymonitoring the conesponding gate pulse on the NSFC
card. The two signals should line up with each as shown on Figure7-3.
Table 78.1
Gate Lead of Gate Lead of

Each SCR Each SCR
LTMl
STM4 LTM4
STM5 LTM5
t. Connecta currentprobe to the scope and trigger on this channel.Hook

the currentprobe to each of the gate leads (whitewire) of the scFb with
arrow on the current probe pointing toward the SCR. Verify that the
waveformhas the same characteristicsas Figure 7-4. ll the pulse fails this
criterion,the HPTKcard in that leg cell module is most likelythe cause,or
the NTDAconnectionsmay be reversed.
Put the NLCB (2E)'TEST'switch (SWt) in the OFF position.
7-36
ITATEDINVERTER
LOADCO[/lh4I. BHEL
srGX(TPX)
NSFC
CELL'S
GATE CURRENT
Flgure 7€ Tlplcal Flrlng Gate Pulse Tralns
Figure 7-4 Typical Firing Pulse (Celt Gate Current Pulse)
7-37
c
e
o BHEL LOADCOMMUTATED
INVERTER
!
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t
vAt crPtz)
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r{Lc8 (20
srcr fiPl)
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Flgure 7-5 Software lntemrpts - Full Advencs (Sourca)
7-38
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EARTHING FOR SEM RACK
N"
N Aluminium
xtrusion
Aluminium
N Extru
SEM FRONT
v VIEW Cu. Braid
Remove onlv one Nut/Bolt at a time. Check Spring/Plate washer present
l.Removepaint on both sidesof Nut/Boltsmarked'N'.

'S'.
2.Removepaint on Nut sideof 'S' and lacqueron PCB board track(if lacquered)on Headsideof
Testwith mulimeterif in doubt.Generallythis motherboard will not be lacquered.
3.GNDis tinnedcoppergroundbus in C & ExePanet(Regulationpanelin highcurrent rectifier).
Make connection'Y' at site(ifnot alreadypresent)with 25-sq.mm. Aluminium or coppercablewith lugs
on both sides.Checkif 'Z' cablecopper/PVCalreadyexists.If not makeconnection(Z'.Cable'Z'is 16
sq.mm,Copperbraid/PVCcable,connectionmay alreadydoneat BHEL/EDN in Panel.
[^;-]
.-",1 tl"".u Front
l "o ll
\
I
SEM SIDE SEM SIDE SEM BACK
VIEW VIEW COVER
'An and oB'. Exercise caution as the motherboard

4.Scrapepaint on both sideson plate of nut/bolt
pins may get bent accidentally when doing this.
5 Scrape paint on back cover on head side of screws'C'.
6.The objective of these points I to 5 is to ensure that PCB(mother board) ground track mentioned in
point 2 is perfectly connectedto tinned copper earth bus in C & Exe, panel(Regulation
Panel in high current rectifier).
7. Atl Nut Bolts to have spring and plate washers.Only plated washers to be in contact with paint
scraped surfaces only. Replace if biting/toothed washers are present. Replace one at a time.
8. Check that the PCB motherboard pins have not been bent.
'S' and ground
9. Re-check all points I to 8 above have been done. Check for continuity between
copper flat.
l0.Install SEM back cover carefully.
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[ *

CommandsAttentionto an operatingproceedure, practice,

Commandsattentionto an essentialoperatingor main-

CAUTION 1. Do not attemptto repairPrintedCircuitBoards(PCB)at site.

2. Do not attemptto replacleThyristorin a powermodulewhere

AC ADJUSTABLE SPEED DRIVES

1-1 BASIC LCI SYSTEM 1-1

1-2 BASIC POWER CONVERTEROPERAT]ON 1-2

1-3 LCI CONTROL 1-6

1-3.1 BasicOperation 1-6

1-3.2 Starting/Force Modes

1-4, TWELVE.PULSEOPERA]]ON 1-11

1-5. SEFUESTWELVE- PUISE OPEBAT1ON

Power Equipment 2-1

2-1.1 1.2 l$/ Air Cooled Bridge 2-1

?-1.2 2 l(/ Air Cooled Medium voltage Bridge 2-2

2-1.3 4 l(/ Air Cooled Medium voltage Bridge 2-2

2.1.4 2l<\ll4l{l Water Cooled Medium Voltage Bridge 2-5

2-2 TI-IYRISTOR MODULES 2-5

\ 2-2.1 Air Cooled MVB Thyristor Modules 2-5

2-2.2 Water Cooled MVB Thyrlstor Modules 2-12

2-3 CIATE DRIVER TRANSFORMER 2-12

2-4 GATE DRIVER CARD (HPTI$ 2-13

2-5 VOLTAGE FEEDBACK ATTENUATOR CARD 2-1s

2-6 AIR COOLED MVB SIGNAL DISTFUBUNON 2-14

Control ElectronicsPanel 3-1

3-1 INTRODUCTION 3-1

3-2 ELECITION|CSMODULE(LCG,LCL) 3-1

3-3.1 Basic principles 3-3

3-3.2 Pulse Locked LooP OPeration 3-7

3-3.3 ElectronicsModule Printed Wiring Board (PWB) Descriptions 3-7

3-3.4 Microprocessor- HMPC{DMPB 3-7

3-3.5 ROM DMPB

3-3.6 LCI Processor Exciter Board - HLCB 3-8

3-3.7 Analog/Digital Intedace Card HAIA 3-10

3-3.8 Flux lntegrators- NLIB 3-1s

3-3.8.1 VOLTAGE INTEGRATORS 3-15

3-3.8.2 UNE / LOAD CT RECEVERS 3-15

3-3.8.3 VOLTMETER DRIVER 3-18

3-3.8.4 OVER VOLTAGE PROTECTION 3-18

3-3.8.5 UNDER VOLTAGE SENSING 3-18

3-3.8.6 SUPPRESSION 3-18

3-3.8.7 CURRENT METER DRIVER 3-18

3-3.9.1 R BUS INTERFACE 3-20

3-3.9.2 FIFUNGMASK LArcH 3-20

3-3.9.3 GATE DRIVERS 3-20

3.3.9.4 PULSE TRAIN GENERA'I'ION 3-21

3-3.9.5 BUFFERS 3-21

3.3.9.6 UNE.TO.UNE VOLTAGE SIGNAL CONDITIONS 3-21

3.3,9,7 CELL STATE SENSORS 3-21

3-3.9.8 D-C UNK VOLTS 3-21

3-3.10 Field ExcitationControl Board - NSFE 3-22

3-3.10.1 R BUS INTERFACE 3-24

3-3.10.3 GATE DRIVERS 3-24

3-3,10.4 CURRENT FEEDBACK CONDITIONING 3-24

3-3.10.5 CURRENT UNBAISNCE DETECNON 3-24

3-3.11 AI{ALOG LCI BOARD - NLCB 3-26

3-3.11.1. SPEED FEEDBACK 3-26

3-3.11.2 DfiERNAL SPEED TIEFERENCE 3-26

3-3.11.3 TEST SPEED REFERENCE 3-27

3-3.1.I.4 TORQUE REFERENGESIGNAL CONDI]]ONING 3-27

3-3.11.5 SELF TEST FEATURES 3-27

3_3.11.6 +20 MA S|GNAL DRIVEFIS 3-27