I. INTRODUCTION
r - l
described by Rhyne [ 11. The voltage symbolism technique was
applauded and used extensively in industry since it provided
Obtain the functional logic
direct conversion from AND-OR-NOT expressions (either
Step -i diagrams.
sum-of-products form or product-of-sums form) to circuitry
that used NAND or NOR gates without losing the AND/OR
or OR/AND structure of the expressions. The top-down design
Obtain the realizable
process [2] is an improvement over the voltage symbolism Step 5
design technique. The steps involved in the top-down design
process are illustrated in the flowchart in Fig. 1. 1
The student can apply each design step in a relatively simple
manner, Obtaining logic diagrams to express the functionality
of a set of combination logic equations is the first step
towards understanding how to implement the equations. Once
Steo 0
aottom or im Iewi I
Obtain the aetailed
logic diagrams. I
Fig. 1. Flowchart for the top-down design process for gate-level combina-
the functional logic diagrams are obtained, these diagrams tional logic design.
can easily be converted into realizable logic diagrams using
preferred or readily available off-the-shelf gate-level logic
elements. form). The top-down design process works equally well for
functions expressed in canonical SOP or POS form or in
reduced SOP or POS form. Obtaining a circuit implementation
THE TOP-DOWN
11. TEACHING DESIGNPROCESS
with a minimum number of logic elements requires using
Beginning with Step 1 in the top-down design process, minimum functions, i.e., functions with a minimum number of
the student should first obtain the logic descriptions of the
literals. The designation of an input or an output signal in most
Boolean functions or their complements in either sum-of-
cases is expressed as a single variable such as X or as a more
products form (SOP form) or product-of-sums form (POS
meaningful signal name such as START. An input or output
Manuscript received October 1990; revised October 1991. signal can also be expressed as a complemented variable such
The author is with the Department of Electrical Engineering, University of
Wyoming, Laramie, WY 82071. as or STOP using an overbar €or the complement, or for
IEEE Log Number 9201007. in-line notation ANSI/IEEE Std 991-1986 [3] suggests the
0018-9359/92/0800-$03.00 0 1992 IEEE
248 IEEE TRANSACTIONS ON EDUCATION, VOL 35, NO. 3, AUGUST 1992
t I
ctrnit 9
Logic layout part (LLP)
Use the available form of
Step 3a the Boolean function to
write the Boolean function
m
clrcoit 4
using only the available
signals (remove the overbars).
?;I ?g
--
PL
PL
circuit 2
8
c
T 1
Avdable
conventlons signais
B,r
‘:.
I PL F1
1
Negation indication part (NIP)
Use the available form of the
Boolean function. For positive
Step 3b logic sign&, list 1 for each
Fig. 2. Representation of the signal logic conventions and available signals unbarred literal and 0 for each
for (1). barred literal. For negative
logic signals, list 0 for each
unbarred literal and 1 for
-
symbol 1 or can be used preceding the signal name and each barred literal.
results in the following examples for complemented variables:
-A, - A , T S T O P , “ S T O P . In this paper, when a signal is
accessible at an input or an output it will be referred to as Fig. 3. Design documentation procedure for diagrams using the positive
logic convention.
an available signal. An accessible or available signal can be
written as an uncomplemented variable or as a complemented
variable. For signal names that are complemented, we will Step 1 in design form (available form-in a form that uses
use the notation “VARIABLE. When a function is written the accessible signals required for the design).
using the accessible signals for the problem, we refer to the The next step, step 3, in the top-down design process is to
function as being written in design form (available form). obtain the design documentation for the circuit. The design
As an example, assume a student wants to implement the documentation procedure illustrated in Steps 3(a) and 3(b)
following reduced Boolean function for Circuit 3 shown in in Fig. 3 are used to accurately document the steps required
Fig. 2. to draw functional logic diagrams using the positive logic
convention. A summary of Steps 1 through 3 in the top-down
Fl= A.B.C+X.C. (1) design process is presented below for (1).
Step 1: FI =A.B.C+A.C
Fig. 2 illustrates that Circuit 3 is dependent on the available
signals coming from Circuit 1 and Circuit 2; that is, positive Step 2: Signal list: F1, A , B . C
logic (PL) signals A , B, and C. In addition, Circuit 3 is Step 3(a) : Logic Layout Part (LLP) :
required to supply the available signal required by Circuit 4; F1= A . B . C +A.C
that is, positive logic (PL) signal F1. Since the variables in
Step 3(b) : Negation Indication Part (NIP):
(1) are presently written in terms of the accessible or available
signals needed at the inputs and output of Circuit 3, we refer 1 1 1 0 0 1
to (1) as being written in design form (available form). This Obtaining the logic layout part (LLP), step 3(a), of the
completed Step 1 in the top-down design process. design documentation just requires removing the overbars
Step 2 (the next level down) in the top-down design process above the available signals in (1) as illustrated above. Since
is used to document the available signals, i.e., the accessible there are only positive logic signals in the signal list for
signals, in an organized list as (l), a 1 is listed under each available signal in Step 3(a)
List of available signals: Fl, A , B, C for each unbarred literal in (l), and a 0 is listed under each
available signal in Step 3(a) for each barred literal in (1).
or Signal list: F1, A , B,C.
This completes the negation indication part (NIP), step 3( b) of
The available signals in the signal list are implied to the design documentation as shown above. Notice in Fig. 3,
be positive logic signals unless otherwise stated. The vast step 3(b), that the design process for negative logic signals
majority of designs in industry involve positive logic signals is the complement of the design process for positive logic
as opposed to negative logic signals; however, the top-down signals. This should be quite evident since a positive logic
design process can be used when the signal list contains signal A can be obtained from a negative logic signal A by
all positive logic signals, all negative logic signals, or a simply adding an inverter (complementing the negative logic
mixture of positive and negative logic signals that are either signal) as illustrated in Fig. 4.
complemented or uncomplemented. To accommodate such a The functional logic diagram using the positive logic con-
variety of available signals requires writing the functions for vention for (l), step 4, can now be easily drawn and labeled
SANDIGE: TOP-DOWN DESIGN PROCESS 249
Negauve
logic
,
I
I
Postive
lopc
Device
names AND elenieni symbols OR elemenl symbols
convention I
I
I
convention
OUT= A
Positive lopic
4XD gales
a-=-
.4
I
I
-
A OUT
I
I
-
,
A = l = L
.4=O=H
1
I
I
A
-= O = L
A = l = H
A = I =H
A=O=L *==cr
Dc4lorg;in eauivaienr sjmaoir Dsrs book bvmbols
Fig. 4. Converting a negative logic signal .to a positive logic signal .-I
I
LLp:+NLp:
D m coo& s! inoois Dehlorgm equivnlenr symoois
A
B m
F1
Positive logic
convention (ac) Fig. 6. Equivalent AND and OR element symbols for normally available
devices.
Fig. 5. Functional logic diagram for (1) using the positive logic convention.
TABLE I
A -B C -D F2
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
PLC 0
0
0
1
1
0
1
0
0
1
0 1 0 1 1
0 1 1 0 0
AND/OR form 0 1 1 1 0
I 0 0 0 1
(a)
1 0 0 1 0
1 0 1 0 I
1 0 1 I O
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
,
--, -3
1 -E o r - Direct polarity
convention @PC)
Use the available form of the
Boolean h a l k m . For poeitive Fig. 11. Functional logic diagram for (2) using the direct polarity conven-
Step 3b logic signals, Est H for each tion.
unbarred literal and L for each
ImmdIIted. Fornegative
logic signah, Hst L for each
unbarred kmal and U for
each b a n d IiternL
Fig. 10. Design documentation procedure for diagrams using the direct
polarity convention.
logic diagrams. From these functional logic diagrams, the High-speed CMOS Logic Data Book. Texas Instruments Inc., 1989.
student can use equivalent AND and OR element symbols and ALSIAS Logic Data Book, Advanced Low-Power Schottky, Advanced
Schottky. Texas Instruments Inc., 1986.
substitute equivalent signal lines to obtain realizable circuits S.H. Washburn, “An application of Boolean algebra to the design of
for the desired gate types. electronic switching circuits,” Trans. AIEE, p. 380, 1953.
S. P. Asija, “Instant logic conversions,” IEEE Spectrum, vol. 5, no. 12,
p. 77, 1968.
ACKNOWLEDGMENT V. Ennis, “Positive and negative logic,” Comp. Design, vol. 9, no. 9,
p. 79, 1970.
The author would like to thank A. Elken at McGraw-Hill P.M. Kintner, “A simple method of designing - - NOR logic,” Control
Publishing Company for his help in soliciting peer reviews Eng., p. 77, 1963.
M. P. Marcus, Switching Circuits .for Engineers.
I Englewood Cliffs, NJ:
for the top-down design process during the time the text Prentice-Hall, 1962.
Modern Digital Design was being written. He would also like W. I. Fletcher, An Engineering Approach to Digital Design. Englewood
Cliffs, NJ: Prentice-Hall, 1980.
to thank the following reviewers for their helpful comments F. P. Prosser and D. E. Winkel, The Art of Digital Design. Englewood
and suggestions concerning the top-down design process: Cliffs, NJ: Prentice-Hall, 1987.
S. W. Director, Carnegie-Mellon University; P. I. P. Boulton,
University of Toronto; T.-S. Chung, University of Kentucky;
J.D. Dixon, University of North Dakota; C. Druzgalski,
California State University-Long Beach; D. Ernie, University
of Minnesota; P. T. Hulina, Pennsylvania State University; Richard S. Sandige (S’63-M’64-SM’90) received
the B S.E E and M S E.E degrees from West Vir-
D. J. Johnson, University of Washington; E. C. Jones, Jr., ginia University, Morgantown, in 1963 and 1969,
Iowa State University; C. R. Kime, University of Wisconsin- respectively, and the Ph D degree in electrical en-
Madison; P. Noe, Texas A&M University; and P.D. Stigall, gineering from Texas A&M University, College
Station, in 1978.
University of Missouri-Rolla. He is currently an Associate Professor in the
Depdrtment of Electrical Engineering, University
REFERENCES of Wyoming, Laramie Prior to joining the staff
dt the University of Wyoming, he worked for ten
[ 11 V. T. Rhyne, Fundamentals of Digital Systems Design. Englewood years as a Member of the Technical Staff in the
Cliffs, NJ: Prentice-Hall, 1973. Research and Development Laboratory dt Hewlett-Packard, Fort Collins, CO
[2] R. S. Sandige, Modern DigitalDesign. New York: McGraw-Hill, 1990. His research interests include PLD’? and FPGA’s and their applications in
[3] ANSIiIEEE Std 991-1986, IEEE Standard for Logic Circuit Diagrams. digital design and microprocessor systems He currently supports the research
New York: The Institute of Electrical and Electronic Engineers, 1986. dnd development activities of Minc Incorporated, a technology leader in
[4] PLDesigner Student Version (User’s Guide). Colorado Springs, CO: programmable logic synthesis tools He recently wrote a textbook entitled
Minc Inc., (licensed by McCraw-Hill), 1990. Modern Digital Design (McGraw-Hill, 1990)